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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2004/01/17 18:38:11  mohor
// cpu_tall_o is set with cpu_stb_o or register.
//
// Revision 1.3  2004/01/17 18:01:24  mohor
// New version.
//
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:31  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
// Top module
module dbg_cpu(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                cpu_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
 
                // CPU signals
                cpu_clk_i,
                cpu_addr_o,
                cpu_data_i,
                cpu_data_o,
                cpu_bp_i,
                cpu_stall_o,
                cpu_stall_all_o,
                cpu_stb_o,
                cpu_sel_o,          // Not synchronized
                cpu_we_o,
                cpu_ack_i,
                cpu_rst_o
 
 
              );
 
// JTAG signals
input         tck_i;
input         tdi_i;
output        tdo_o;
 
// TAP states
input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;
 
input         cpu_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;
 
 
// CPU signals
input         cpu_clk_i;
output [31:0] cpu_addr_o;
input  [31:0] cpu_data_i;
output [31:0] cpu_data_o;
input         cpu_bp_i;
output        cpu_stall_o;
output        cpu_stall_all_o;
output        cpu_stb_o;
output [`CPU_NUM -1:0]  cpu_sel_o;
output        cpu_we_o;
input         cpu_ack_i;
output        cpu_rst_o;
 
 
 
reg           tdo_o;
 
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_cnt_en;
reg     [5:0] addr_cnt;
reg     [5:0] addr_cnt_limit;
wire          addr_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg     [5:0] data_cnt;
reg     [5:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
wire          status_cnt_end;
reg           status_cnt1, status_cnt2, status_cnt3, status_cnt4;
reg     [3:0] status;
 
reg           crc_match_reg;
wire          enable;
 
reg           read_cycle_reg;
reg           read_cycle_reg_q;
reg           read_cycle_cpu;
reg           read_cycle_cpu_q;
reg           write_cycle_reg;
reg           write_cycle_cpu;
wire          read_cycle;
wire          write_cycle;
 
reg    [34:0] dr;
wire    [7:0] reg_data_out;
 
wire          dr_read_reg;
wire          dr_write_reg;
wire          dr_read_cpu8;
wire          dr_read_cpu32;
wire          dr_write_cpu8;
wire          dr_write_cpu32;
wire          dr_go;
 
reg           dr_read_reg_latched;
reg           dr_write_reg_latched;
reg           dr_read_cpu8_latched;
reg           dr_read_cpu32_latched;
reg           dr_write_cpu8_latched;
reg           dr_write_cpu32_latched;
reg           dr_go_latched;
 
reg           cmd_read_reg;
reg           cmd_read_cpu;
reg           cmd_write_reg;
reg           cmd_write_cpu;
reg           cycle_32_bit;
reg           reg_access;
 
reg    [31:0] adr;
reg           set_addr;
reg           cpu_ack_sync;
reg           cpu_ack_tck;
reg           cpu_ack_tck_q;
reg           cpu_stb;
reg           cpu_stb_sync;
reg           cpu_stb_o;
wire          cpu_stall_tmp;
 
wire          go_prelim;
wire          crc_cnt_31;
 
 
 
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <= #1 2'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 2'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_cnt <= #1 6'h0;
  else if (update_dr_i)
    addr_cnt <= #1 6'h0;
  else if (addr_cnt_en)
    addr_cnt <= #1 addr_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <= #1 6'h0;
  else if (update_dr_i)
    data_cnt <= #1 6'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end  & (~write_cycle) | (data_cnt_end & write_cycle));
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <= #1 6'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 6'h0;
end
 
 
// Upper limit. Address/length counter counts until this value is reached
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))                                   // (current command is WB_STATUS or WB_GO)
        addr_cnt_limit = 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_cnt_limit = 6'd32;
    end
end
 
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_cnt_end = addr_cnt == addr_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign crc_cnt_31 = crc_cnt  == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q  <= #1 crc_cnt_end;
  cmd_cnt_end_q  <= #1 cmd_cnt_end;
  data_cnt_end_q <= #1 data_cnt_end;
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & read_cycle |
           crc_cnt_end & (~read_cycle)
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
assign status_cnt_end = status_cnt4;
 
 
 
 
// Latching address
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (~dr_go_latched)
        begin
          adr <= #1 dr[31:0];
          set_addr <= #1 1'b1;
        end
    end
  else
    set_addr <= #1 1'b0;
end
 
 
assign cpu_addr_o = adr;
 
 
// Shift register for shifting in and out the data
always @ (posedge tck_i)
begin
  if (reg_access)
    begin
      dr[31:24] <= #1 reg_data_out;
    end
  else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
    begin
      if (cycle_32_bit)
        dr[31:0] <= #1 cpu_data_i;
      else
        dr[31:24] <= #1 cpu_data_i[7:0];
    end
  else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
    begin
      dr <= #1 {dr[33:0], tdi_i};
    end
end
 
 
assign dr_read_reg    = dr[2:0] == `CPU_READ_REG;
assign dr_write_reg   = dr[2:0] == `CPU_WRITE_REG;
assign dr_read_cpu8   = dr[2:0] == `CPU_READ8;
assign dr_read_cpu32  = dr[2:0] == `CPU_READ32;
assign dr_write_cpu8  = dr[2:0] == `CPU_WRITE8;
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
assign dr_go          = dr[2:0] == `CPU_GO;
 
 
// Latching instruction
always @ (posedge tck_i)
begin
  if (update_dr_i)
    begin
      dr_read_reg_latched  <= #1 1'b0;
      dr_read_cpu8_latched  <= #1 1'b0;
      dr_read_cpu32_latched  <= #1 1'b0;
      dr_write_reg_latched  <= #1 1'b0;
      dr_write_cpu8_latched  <= #1 1'b0;
      dr_write_cpu32_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_read_reg_latched <= #1 dr_read_reg;
      dr_read_cpu8_latched <= #1 dr_read_cpu8;
      dr_read_cpu32_latched <= #1 dr_read_cpu32;
      dr_write_reg_latched <= #1 dr_write_reg;
      dr_write_cpu8_latched <= #1 dr_write_cpu8;
      dr_write_cpu32_latched <= #1 dr_write_cpu32;
      dr_go_latched <= #1 dr_go;
    end
end
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cmd_read_reg    <= #1 1'b0;
      cmd_read_cpu    <= #1 1'b0;
      cmd_write_reg   <= #1 1'b0;
      cmd_write_cpu   <= #1 1'b0;
      cycle_32_bit    <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd_read_reg    <= #1 dr_read_reg_latched;
      cmd_read_cpu    <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
      cmd_write_reg   <= #1 dr_write_reg_latched;
      cmd_write_cpu   <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
      cycle_32_bit    <= #1 dr_read_cpu32_latched | dr_write_cpu32_latched;
    end
end
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <= #1 6'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))
    begin
      if (dr_read_cpu32_latched | dr_write_cpu32_latched)
        data_cnt_limit <= #1 6'd32;
      else
        data_cnt_limit <= #1 6'd8;
    end
end
 
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle_reg <= #1 1'b0;
  else if (cmd_read_reg & go_prelim)
    read_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle_cpu <= #1 1'b0;
  else if (cmd_read_cpu & go_prelim)
    read_cycle_cpu <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  read_cycle_reg_q <= #1 read_cycle_reg;
  read_cycle_cpu_q <= #1 read_cycle_cpu;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle_reg <= #1 1'b0;
  else if (cmd_write_reg & go_prelim)
    write_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle_cpu <= #1 1'b0;
  else if (cmd_write_cpu & go_prelim)
    write_cycle_cpu <= #1 1'b1;
end
 
 
assign read_cycle = read_cycle_reg | read_cycle_cpu;
assign write_cycle = write_cycle_reg | write_cycle_cpu;
 
 
 
// Start register access cycle
always @ (posedge tck_i)
begin
  if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
    begin
      reg_access <= #1 1'b1;
    end
  else
    reg_access <= #1 1'b0;
end
 
 
 
// Connecting dbg_cpu_registers
dbg_cpu_registers i_dbg_cpu_registers
     (
      .data_i           (dr[7:0]),
      .data_o           (reg_data_out),
      .addr_i           (adr[1:0]),
      .we_i             (write_cycle_reg),
      .en_i             (reg_access),
      .clk_i            (tck_i),
      .bp_i             (cpu_bp_i),
      .rst_i            (rst_i),
      .cpu_clk_i        (cpu_clk_i),
      .cpu_stall_o      (cpu_stall_tmp),
      .cpu_stall_all_o  (cpu_stall_all_o),
      .cpu_sel_o        (cpu_sel_o),
      .cpu_rst_o        (cpu_rst_o)
     );
 
 
 
assign cpu_we_o   = write_cycle_cpu;
assign cpu_data_o = dr[31:0];
assign cpu_stall_o = cpu_stb_o | cpu_stall_tmp;
 
 
 
// Synchronizing ack signal from cpu
always @ (posedge tck_i)
begin
  cpu_ack_sync      <= #1 cpu_ack_i;
  cpu_ack_tck       <= #1 cpu_ack_sync;
  cpu_ack_tck_q     <= #1 cpu_ack_tck;
end
 
 
 
// Start cpu access cycle
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cpu_stb <= #1 1'b0;
  else if (cpu_ack_tck)
    cpu_stb <= #1 1'b0;
  else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) | read_cycle_cpu & (~read_cycle_cpu_q))
    cpu_stb <= #1 1'b1;
end
 
 
 
// Synchronizing cpu_stb to cpu_clk_i clock
always @ (posedge cpu_clk_i)
begin
  cpu_stb_sync  <= #1 cpu_stb;
  cpu_stb_o     <= #1 cpu_stb_sync;
end
 
 
// Latching crc
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <= #1 crc_match_i;
end
 
 
 
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
    status <= #1 4'h0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
    begin
    status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
    end
  else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
    begin
    status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
    end
  else if (shift_dr_i & (~status_cnt_end))
    begin
    status <= #1 {status[0], status[3:1]};
    end
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1'b0
// 3. bit:          1'b1
// 4. bit:          1'b0
 
 
 
// TDO multiplexer
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or data_cnt_end or data_cnt_end_q or
          read_cycle or crc_match_reg or status or dr)
begin
  if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
    begin
      tdo_o = crc_match_i;
    end
  else if (read_cycle & crc_cnt_end & (~data_cnt_end))
    begin
    tdo_o = dr[31];
    end
  else if (read_cycle & data_cnt_end & (~data_cnt_end_q))     // cmd is already updated
    begin
      tdo_o = crc_match_reg;
    end
  else if (crc_cnt_end)
    begin
      tdo_o = status[0];
    end
  else
    begin
      tdo_o = 1'b0;
    end
end
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	108	simons	`// Revision 1.4 2004/01/17 18:38:11 mohor`
47			`// cpu_tall_o is set with cpu_stb_o or register.`
48			`//`
49	104	mohor	`// Revision 1.3 2004/01/17 18:01:24 mohor`
50			`// New version.`
51			`//`
52	102	mohor	`// Revision 1.2 2004/01/17 17:01:14 mohor`
53			`// Almost finished.`
54			`//`
55	101	mohor	`// Revision 1.1 2004/01/16 14:53:31 mohor`
56			`// * empty log message *`
57	100	mohor	`//`
58			`//`
59	101	mohor	`//`
60	100	mohor
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "dbg_cpu_defines.v"
65
66			`// Top module`
67			`module dbg_cpu(`
68			`// JTAG signals`
69			`tck_i,`
70			`tdi_i,`
71			`tdo_o,`
72
73			`// TAP states`
74			`shift_dr_i,`
75			`pause_dr_i,`
76			`update_dr_i,`
77
78			`cpu_ce_i,`
79			`crc_match_i,`
80			`crc_en_o,`
81			`shift_crc_o,`
82			`rst_i,`
83
84	101	mohor	`// CPU signals`
85			`cpu_clk_i,`
86			`cpu_addr_o,`
87			`cpu_data_i,`
88			`cpu_data_o,`
89			`cpu_bp_i,`
90			`cpu_stall_o,`
91			`cpu_stall_all_o,`
92			`cpu_stb_o,`
93			`cpu_sel_o, // Not synchronized`
94			`cpu_we_o,`
95			`cpu_ack_i,`
96			`cpu_rst_o`
97	100	mohor
98	101	mohor
99	100	mohor	`);`
100
101			`// JTAG signals`
102			`input tck_i;`
103			`input tdi_i;`
104			`output tdo_o;`
105
106			`// TAP states`
107			`input shift_dr_i;`
108			`input pause_dr_i;`
109			`input update_dr_i;`
110
111			`input cpu_ce_i;`
112			`input crc_match_i;`
113			`output crc_en_o;`
114			`output shift_crc_o;`
115			`input rst_i;`
116	101	mohor
117
118			`// CPU signals`
119			`input cpu_clk_i;`
120			`output [31:0] cpu_addr_o;`
121			`input [31:0] cpu_data_i;`
122			`output [31:0] cpu_data_o;`
123			`input cpu_bp_i;`
124			`output cpu_stall_o;`
125			`output cpu_stall_all_o;`
126			`output cpu_stb_o;`
127			output [`CPU_NUM -1:0] cpu_sel_o;
128			`output cpu_we_o;`
129			`input cpu_ack_i;`
130			`output cpu_rst_o;`
131
132
133	100	mohor
134			`reg tdo_o;`
135
136			`wire cmd_cnt_en;`
137			`reg [1:0] cmd_cnt;`
138			`wire cmd_cnt_end;`
139			`reg cmd_cnt_end_q;`
140			`wire addr_cnt_en;`
141			`reg [5:0] addr_cnt;`
142			`reg [5:0] addr_cnt_limit;`
143			`wire addr_cnt_end;`
144			`wire crc_cnt_en;`
145			`reg [5:0] crc_cnt;`
146			`wire crc_cnt_end;`
147			`reg crc_cnt_end_q;`
148			`wire data_cnt_en;`
149			`reg [5:0] data_cnt;`
150			`reg [5:0] data_cnt_limit;`
151			`wire data_cnt_end;`
152			`reg data_cnt_end_q;`
153			`wire status_cnt_end;`
154			`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
155			`reg [3:0] status;`
156
157	102	mohor	`reg crc_match_reg;`
158	100	mohor	`wire enable;`
159
160			`reg read_cycle_reg;`
161	101	mohor	`reg read_cycle_reg_q;`
162	100	mohor	`reg read_cycle_cpu;`
163	101	mohor	`reg read_cycle_cpu_q;`
164	100	mohor	`reg write_cycle_reg;`
165			`reg write_cycle_cpu;`
166			`wire read_cycle;`
167			`wire write_cycle;`
168
169			`reg [34:0] dr;`
170	101	mohor	`wire [7:0] reg_data_out;`
171	100	mohor
172			`wire dr_read_reg;`
173			`wire dr_write_reg;`
174			`wire dr_read_cpu8;`
175			`wire dr_read_cpu32;`
176			`wire dr_write_cpu8;`
177			`wire dr_write_cpu32;`
178			`wire dr_go;`
179
180			`reg dr_read_reg_latched;`
181			`reg dr_write_reg_latched;`
182			`reg dr_read_cpu8_latched;`
183			`reg dr_read_cpu32_latched;`
184			`reg dr_write_cpu8_latched;`
185			`reg dr_write_cpu32_latched;`
186			`reg dr_go_latched;`
187
188			`reg cmd_read_reg;`
189			`reg cmd_read_cpu;`
190			`reg cmd_write_reg;`
191			`reg cmd_write_cpu;`
192	101	mohor	`reg cycle_32_bit;`
193			`reg reg_access;`
194	100	mohor
195	104	mohor	`reg [31:0] adr;`
196			`reg set_addr;`
197			`reg cpu_ack_sync;`
198			`reg cpu_ack_tck;`
199			`reg cpu_ack_tck_q;`
200			`reg cpu_stb;`
201			`reg cpu_stb_sync;`
202			`reg cpu_stb_o;`
203			`wire cpu_stall_tmp;`
204	101	mohor
205	100	mohor	`wire go_prelim;`
206			`wire crc_cnt_31;`
207
208
209	101	mohor
210	100	mohor	`assign enable = cpu_ce_i & shift_dr_i;`
211			`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
212			`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
213
214
215			`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
216
217
218			`// Command counter`
219			`always @ (posedge tck_i or posedge rst_i)`
220			`begin`
221			`if (rst_i)`
222	108	simons	`cmd_cnt <= #1 2'h0;`
223	100	mohor	`else if (update_dr_i)`
224	108	simons	`cmd_cnt <= #1 2'h0;`
225	100	mohor	`else if (cmd_cnt_en)`
226			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
227			`end`
228
229
230			`assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);`
231
232
233			`// Address/length counter`
234			`always @ (posedge tck_i or posedge rst_i)`
235			`begin`
236			`if (rst_i)`
237	108	simons	`addr_cnt <= #1 6'h0;`
238	100	mohor	`else if (update_dr_i)`
239	108	simons	`addr_cnt <= #1 6'h0;`
240	100	mohor	`else if (addr_cnt_en)`
241			`addr_cnt <= #1 addr_cnt + 1'b1;`
242			`end`
243
244
245			`assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle \| crc_cnt_end & read_cycle);`
246
247
248			`// Data counter`
249			`always @ (posedge tck_i or posedge rst_i)`
250			`begin`
251			`if (rst_i)`
252	108	simons	`data_cnt <= #1 6'h0;`
253	100	mohor	`else if (update_dr_i)`
254	108	simons	`data_cnt <= #1 6'h0;`
255	100	mohor	`else if (data_cnt_en)`
256			`data_cnt <= #1 data_cnt + 1'b1;`
257			`end`
258
259
260			`assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end & (~write_cycle) \| (data_cnt_end & write_cycle));`
261
262
263			`// crc counter`
264			`always @ (posedge tck_i or posedge rst_i)`
265			`begin`
266			`if (rst_i)`
267	108	simons	`crc_cnt <= #1 6'h0;`
268	100	mohor	`else if(crc_cnt_en)`
269			`crc_cnt <= #1 crc_cnt + 1'b1;`
270			`else if (update_dr_i)`
271	108	simons	`crc_cnt <= #1 6'h0;`
272	100	mohor	`end`
273
274
275			`// Upper limit. Address/length counter counts until this value is reached`
276			`always @ (posedge tck_i)`
277			`begin`
278			`if (cmd_cnt == 2'h2)`
279			`begin`
280			`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
281			`addr_cnt_limit = 6'd0;`
282			`else // (current command is WB_WRITEx or WB_READx)`
283			`addr_cnt_limit = 6'd32;`
284			`end`
285			`end`
286
287
288			`assign cmd_cnt_end = cmd_cnt == 2'h3;`
289			`assign addr_cnt_end = addr_cnt == addr_cnt_limit;`
290			`assign crc_cnt_end = crc_cnt == 6'd32;`
291			`assign crc_cnt_31 = crc_cnt == 6'd31;`
292			`assign data_cnt_end = (data_cnt == data_cnt_limit);`
293
294			`always @ (posedge tck_i)`
295			`begin`
296			`crc_cnt_end_q <= #1 crc_cnt_end;`
297			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
298			`data_cnt_end_q <= #1 data_cnt_end;`
299			`end`
300
301
302			`// Status counter is made of 4 serialy connected registers`
303			`always @ (posedge tck_i or posedge rst_i)`
304			`begin`
305			`if (rst_i)`
306			`status_cnt1 <= #1 1'b0;`
307			`else if (update_dr_i)`
308			`status_cnt1 <= #1 1'b0;`
309			`else if (data_cnt_end & read_cycle \|`
310			`crc_cnt_end & (~read_cycle)`
311			`)`
312			`status_cnt1 <= #1 1'b1;`
313			`end`
314
315
316			`always @ (posedge tck_i or posedge rst_i)`
317			`begin`
318			`if (rst_i)`
319			`begin`
320			`status_cnt2 <= #1 1'b0;`
321			`status_cnt3 <= #1 1'b0;`
322			`status_cnt4 <= #1 1'b0;`
323			`end`
324			`else if (update_dr_i)`
325			`begin`
326			`status_cnt2 <= #1 1'b0;`
327			`status_cnt3 <= #1 1'b0;`
328			`status_cnt4 <= #1 1'b0;`
329			`end`
330			`else`
331			`begin`
332			`status_cnt2 <= #1 status_cnt1;`
333			`status_cnt3 <= #1 status_cnt2;`
334			`status_cnt4 <= #1 status_cnt3;`
335			`end`
336			`end`
337
338
339			`assign status_cnt_end = status_cnt4;`
340
341
342
343
344			`// Latching address`
345			`always @ (posedge tck_i)`
346			`begin`
347			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
348			`begin`
349			`if (~dr_go_latched)`
350			`begin`
351			`adr <= #1 dr[31:0];`
352			`set_addr <= #1 1'b1;`
353			`end`
354			`end`
355			`else`
356			`set_addr <= #1 1'b0;`
357			`end`
358
359
360	101	mohor	`assign cpu_addr_o = adr;`
361	100	mohor
362	101	mohor
363	100	mohor	`// Shift register for shifting in and out the data`
364			`always @ (posedge tck_i)`
365			`begin`
366	101	mohor	`if (reg_access)`
367	100	mohor	`begin`
368	101	mohor	`dr[31:24] <= #1 reg_data_out;`
369			`end`
370			`else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)`
371			`begin`
372			`if (cycle_32_bit)`
373			`dr[31:0] <= #1 cpu_data_i;`
374			`else`
375			`dr[31:24] <= #1 cpu_data_i[7:0];`
376			`end`
377			`else if (enable & ((~addr_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle) \| (crc_cnt_end & (~data_cnt_end) & read_cycle)))`
378			`begin`
379	100	mohor	`dr <= #1 {dr[33:0], tdi_i};`
380			`end`
381			`end`
382
383
384			assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
385			assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
386			assign dr_read_cpu8 = dr[2:0] == `CPU_READ8;
387			assign dr_read_cpu32 = dr[2:0] == `CPU_READ32;
388			assign dr_write_cpu8 = dr[2:0] == `CPU_WRITE8;
389			assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
390			assign dr_go = dr[2:0] == `CPU_GO;
391
392
393			`// Latching instruction`
394			`always @ (posedge tck_i)`
395			`begin`
396			`if (update_dr_i)`
397			`begin`
398			`dr_read_reg_latched <= #1 1'b0;`
399			`dr_read_cpu8_latched <= #1 1'b0;`
400			`dr_read_cpu32_latched <= #1 1'b0;`
401			`dr_write_reg_latched <= #1 1'b0;`
402			`dr_write_cpu8_latched <= #1 1'b0;`
403			`dr_write_cpu32_latched <= #1 1'b0;`
404			`dr_go_latched <= #1 1'b0;`
405			`end`
406			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
407			`begin`
408			`dr_read_reg_latched <= #1 dr_read_reg;`
409			`dr_read_cpu8_latched <= #1 dr_read_cpu8;`
410			`dr_read_cpu32_latched <= #1 dr_read_cpu32;`
411			`dr_write_reg_latched <= #1 dr_write_reg;`
412			`dr_write_cpu8_latched <= #1 dr_write_cpu8;`
413			`dr_write_cpu32_latched <= #1 dr_write_cpu32;`
414			`dr_go_latched <= #1 dr_go;`
415			`end`
416			`end`
417
418			`// Latching instruction`
419			`always @ (posedge tck_i or posedge rst_i)`
420			`begin`
421			`if (rst_i)`
422			`begin`
423			`cmd_read_reg <= #1 1'b0;`
424			`cmd_read_cpu <= #1 1'b0;`
425			`cmd_write_reg <= #1 1'b0;`
426	101	mohor	`cmd_write_cpu <= #1 1'b0;`
427			`cycle_32_bit <= #1 1'b0;`
428	100	mohor	`end`
429			`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
430			`begin`
431			`cmd_read_reg <= #1 dr_read_reg_latched;`
432			`cmd_read_cpu <= #1 dr_read_cpu8_latched \| dr_read_cpu32_latched;`
433			`cmd_write_reg <= #1 dr_write_reg_latched;`
434			`cmd_write_cpu <= #1 dr_write_cpu8_latched \| dr_write_cpu32_latched;`
435	101	mohor	`cycle_32_bit <= #1 dr_read_cpu32_latched \| dr_write_cpu32_latched;`
436	100	mohor	`end`
437			`end`
438
439
440			`// Upper limit. Data counter counts until this value is reached.`
441			`always @ (posedge tck_i or posedge rst_i)`
442			`begin`
443			`if (rst_i)`
444			`data_cnt_limit <= #1 6'h0;`
445	101	mohor	`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))`
446	100	mohor	`begin`
447			`if (dr_read_cpu32_latched \| dr_write_cpu32_latched)`
448			`data_cnt_limit <= #1 6'd32;`
449			`else`
450			`data_cnt_limit <= #1 6'd8;`
451			`end`
452			`end`
453
454
455			`assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);`
456
457
458			`always @ (posedge tck_i)`
459			`begin`
460			`if (update_dr_i)`
461			`read_cycle_reg <= #1 1'b0;`
462			`else if (cmd_read_reg & go_prelim)`
463			`read_cycle_reg <= #1 1'b1;`
464			`end`
465
466
467			`always @ (posedge tck_i)`
468			`begin`
469			`if (update_dr_i)`
470			`read_cycle_cpu <= #1 1'b0;`
471			`else if (cmd_read_cpu & go_prelim)`
472			`read_cycle_cpu <= #1 1'b1;`
473			`end`
474
475
476			`always @ (posedge tck_i)`
477			`begin`
478	101	mohor	`read_cycle_reg_q <= #1 read_cycle_reg;`
479			`read_cycle_cpu_q <= #1 read_cycle_cpu;`
480			`end`
481
482
483			`always @ (posedge tck_i)`
484			`begin`
485	100	mohor	`if (update_dr_i)`
486			`write_cycle_reg <= #1 1'b0;`
487			`else if (cmd_write_reg & go_prelim)`
488			`write_cycle_reg <= #1 1'b1;`
489			`end`
490
491
492			`always @ (posedge tck_i)`
493			`begin`
494			`if (update_dr_i)`
495			`write_cycle_cpu <= #1 1'b0;`
496			`else if (cmd_write_cpu & go_prelim)`
497			`write_cycle_cpu <= #1 1'b1;`
498			`end`
499
500

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