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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_cpu.v] - Blame information for rev 101

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2004/01/16 14:53:31  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
// Top module
module dbg_cpu(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                cpu_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
 
                // CPU signals
                cpu_clk_i,
                cpu_addr_o,
                cpu_data_i,
                cpu_data_o,
                cpu_bp_i,
                cpu_stall_o,
                cpu_stall_all_o,
                cpu_stb_o,
                cpu_sel_o,          // Not synchronized
                cpu_we_o,
                cpu_ack_i,
                cpu_rst_o
 
 
              );
 
// JTAG signals
input         tck_i;
input         tdi_i;
output        tdo_o;
 
// TAP states
input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;
 
input         cpu_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;
 
 
// CPU signals
input         cpu_clk_i;
output [31:0] cpu_addr_o;
input  [31:0] cpu_data_i;
output [31:0] cpu_data_o;
input         cpu_bp_i;
output        cpu_stall_o;
output        cpu_stall_all_o;
output        cpu_stb_o;
output [`CPU_NUM -1:0]  cpu_sel_o;
output        cpu_we_o;
input         cpu_ack_i;
output        cpu_rst_o;
 
 
 
reg           tdo_o;
 
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_cnt_en;
reg     [5:0] addr_cnt;
reg     [5:0] addr_cnt_limit;
wire          addr_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg     [5:0] data_cnt;
reg     [5:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
wire          status_cnt_end;
reg           status_cnt1, status_cnt2, status_cnt3, status_cnt4;
reg     [3:0] status;
 
wire          enable;
 
reg           read_cycle_reg;
reg           read_cycle_reg_q;
reg           read_cycle_cpu;
reg           read_cycle_cpu_q;
reg           write_cycle_reg;
reg           write_cycle_cpu;
wire          read_cycle;
wire          write_cycle;
 
reg    [34:0] dr;
wire    [7:0] reg_data_out;
 
wire          dr_read_reg;
wire          dr_write_reg;
wire          dr_read_cpu8;
wire          dr_read_cpu32;
wire          dr_write_cpu8;
wire          dr_write_cpu32;
wire          dr_go;
 
reg           dr_read_reg_latched;
reg           dr_write_reg_latched;
reg           dr_read_cpu8_latched;
reg           dr_read_cpu32_latched;
reg           dr_write_cpu8_latched;
reg           dr_write_cpu32_latched;
reg           dr_go_latched;
 
reg           cmd_read_reg;
reg           cmd_read_cpu;
reg           cmd_write_reg;
reg           cmd_write_cpu;
reg           cycle_32_bit;
reg           reg_access;
 
reg [31:0] adr;
reg set_addr;
reg [199:0] latching_data_text;
reg cpu_ack_sync;
reg cpu_ack_tck;
reg cpu_ack_tck_q;
reg cpu_stb;
reg cpu_stb_sync;
reg cpu_stb_o;
 
wire          go_prelim;
wire          crc_cnt_31;
 
 
 
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_cnt <= #1 'h0;
  else if (addr_cnt_en)
    addr_cnt <= #1 addr_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end  & (~write_cycle) | (data_cnt_end & write_cycle));
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <= #1 'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
 
// Upper limit. Address/length counter counts until this value is reached
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))                                   // (current command is WB_STATUS or WB_GO)
        addr_cnt_limit = 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_cnt_limit = 6'd32;
    end
end
 
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_cnt_end = addr_cnt == addr_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign crc_cnt_31 = crc_cnt  == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q  <= #1 crc_cnt_end;
  cmd_cnt_end_q  <= #1 cmd_cnt_end;
  data_cnt_end_q <= #1 data_cnt_end;
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & read_cycle |
           crc_cnt_end & (~read_cycle)
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
assign status_cnt_end = status_cnt4;
 
 
 
 
// Latching address
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (~dr_go_latched)
        begin
          adr <= #1 dr[31:0];
          set_addr <= #1 1'b1;
        end
    end
  else
    set_addr <= #1 1'b0;
end
 
 
assign cpu_addr_o = adr;
 
 
// Shift register for shifting in and out the data
always @ (posedge tck_i)
begin
  if (reg_access)
    begin
      dr[31:24] <= #1 reg_data_out;
      latching_data_text = "Latch reg data";
    end
  else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
    begin
      if (cycle_32_bit)
        dr[31:0] <= #1 cpu_data_i;
      else
        dr[31:24] <= #1 cpu_data_i[7:0];
      latching_data_text = "Latch cpu data";
    end
  else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
    begin
      dr <= #1 {dr[33:0], tdi_i};
      latching_data_text = "shifting data";
    end
  else
    latching_data_text = "nothing";
end
 
 
assign dr_read_reg    = dr[2:0] == `CPU_READ_REG;
assign dr_write_reg   = dr[2:0] == `CPU_WRITE_REG;
assign dr_read_cpu8   = dr[2:0] == `CPU_READ8;
assign dr_read_cpu32  = dr[2:0] == `CPU_READ32;
assign dr_write_cpu8  = dr[2:0] == `CPU_WRITE8;
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
assign dr_go          = dr[2:0] == `CPU_GO;
 
 
// Latching instruction
always @ (posedge tck_i)
begin
  if (update_dr_i)
    begin
      dr_read_reg_latched  <= #1 1'b0;
      dr_read_cpu8_latched  <= #1 1'b0;
      dr_read_cpu32_latched  <= #1 1'b0;
      dr_write_reg_latched  <= #1 1'b0;
      dr_write_cpu8_latched  <= #1 1'b0;
      dr_write_cpu32_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_read_reg_latched <= #1 dr_read_reg;
      dr_read_cpu8_latched <= #1 dr_read_cpu8;
      dr_read_cpu32_latched <= #1 dr_read_cpu32;
      dr_write_reg_latched <= #1 dr_write_reg;
      dr_write_cpu8_latched <= #1 dr_write_cpu8;
      dr_write_cpu32_latched <= #1 dr_write_cpu32;
      dr_go_latched <= #1 dr_go;
    end
end
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cmd_read_reg    <= #1 1'b0;
      cmd_read_cpu    <= #1 1'b0;
      cmd_write_reg   <= #1 1'b0;
      cmd_write_cpu   <= #1 1'b0;
      cycle_32_bit    <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd_read_reg    <= #1 dr_read_reg_latched;
      cmd_read_cpu    <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
      cmd_write_reg   <= #1 dr_write_reg_latched;
      cmd_write_cpu   <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
      cycle_32_bit    <= #1 dr_read_cpu32_latched | dr_write_cpu32_latched;
    end
end
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <= #1 6'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))
    begin
      if (dr_read_cpu32_latched | dr_write_cpu32_latched)
        data_cnt_limit <= #1 6'd32;
      else
        data_cnt_limit <= #1 6'd8;
    end
end
 
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle_reg <= #1 1'b0;
  else if (cmd_read_reg & go_prelim)
    read_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle_cpu <= #1 1'b0;
  else if (cmd_read_cpu & go_prelim)
    read_cycle_cpu <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  read_cycle_reg_q <= #1 read_cycle_reg;
  read_cycle_cpu_q <= #1 read_cycle_cpu;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle_reg <= #1 1'b0;
  else if (cmd_write_reg & go_prelim)
    write_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle_cpu <= #1 1'b0;
  else if (cmd_write_cpu & go_prelim)
    write_cycle_cpu <= #1 1'b1;
end
 
 
assign read_cycle = read_cycle_reg | read_cycle_cpu;
assign write_cycle = write_cycle_reg | write_cycle_cpu;
 
 
 
// Start register access cycle
always @ (posedge tck_i)
begin
  if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
    begin
      reg_access <= #1 1'b1;
    end
  else
    reg_access <= #1 1'b0;
end
 
 
 
// Connecting dbg_cpu_registers
dbg_cpu_registers i_dbg_cpu_registers
     (
      .data_i           (dr[7:0]),
      .data_o           (reg_data_out),
      .addr_i           (adr[1:0]),
      .we_i             (write_cycle_reg),
      .en_i             (reg_access),
      .clk_i            (tck_i),
      .bp_i             (cpu_bp_i),
      .rst_i            (rst_i),
      .cpu_clk_i        (cpu_clk_i),
      .cpu_stall_o      (cpu_stall_o),
      .cpu_stall_all_o  (cpu_stall_all_o),
      .cpu_sel_o        (cpu_sel_o),
      .cpu_rst_o        (cpu_rst_o)
     );
 
 
 
assign cpu_we_o   = write_cycle_cpu;
assign cpu_data_o = dr[31:0];
 
 
 
 
// Synchronizing ack signal from cpu
always @ (posedge tck_i)
begin
  cpu_ack_sync      <= #1 cpu_ack_i;
  cpu_ack_tck       <= #1 cpu_ack_sync;
  cpu_ack_tck_q     <= #1 cpu_ack_tck;
end
 
 
 
// Start cpu access cycle
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cpu_stb <= #1 1'b0;
  else if (cpu_ack_tck)
    cpu_stb <= #1 1'b0;
  else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) | read_cycle_cpu & (~read_cycle_cpu_q))
    cpu_stb <= #1 1'b1;
end
 
 
 
always @ (posedge tck_i)
begin
  cpu_stb_sync  <= #1 cpu_stb;
  cpu_stb_o     <= #1 cpu_stb_sync;
end
 
 
 
 
 
 
endmodule
 

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_cpu.v] - Blame information for rev 101

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	101	mohor	`// Revision 1.1 2004/01/16 14:53:31 mohor`
47			`// * empty log message *`
48	100	mohor	`//`
49			`//`
50	101	mohor	`//`
51	100	mohor
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "dbg_cpu_defines.v"
56
57			`// Top module`
58			`module dbg_cpu(`
59			`// JTAG signals`
60			`tck_i,`
61			`tdi_i,`
62			`tdo_o,`
63
64			`// TAP states`
65			`shift_dr_i,`
66			`pause_dr_i,`
67			`update_dr_i,`
68
69			`cpu_ce_i,`
70			`crc_match_i,`
71			`crc_en_o,`
72			`shift_crc_o,`
73			`rst_i,`
74
75	101	mohor	`// CPU signals`
76			`cpu_clk_i,`
77			`cpu_addr_o,`
78			`cpu_data_i,`
79			`cpu_data_o,`
80			`cpu_bp_i,`
81			`cpu_stall_o,`
82			`cpu_stall_all_o,`
83			`cpu_stb_o,`
84			`cpu_sel_o, // Not synchronized`
85			`cpu_we_o,`
86			`cpu_ack_i,`
87			`cpu_rst_o`
88	100	mohor
89	101	mohor
90	100	mohor	`);`
91
92			`// JTAG signals`
93			`input tck_i;`
94			`input tdi_i;`
95			`output tdo_o;`
96
97			`// TAP states`
98			`input shift_dr_i;`
99			`input pause_dr_i;`
100			`input update_dr_i;`
101
102			`input cpu_ce_i;`
103			`input crc_match_i;`
104			`output crc_en_o;`
105			`output shift_crc_o;`
106			`input rst_i;`
107	101	mohor
108
109			`// CPU signals`
110			`input cpu_clk_i;`
111			`output [31:0] cpu_addr_o;`
112			`input [31:0] cpu_data_i;`
113			`output [31:0] cpu_data_o;`
114			`input cpu_bp_i;`
115			`output cpu_stall_o;`
116			`output cpu_stall_all_o;`
117			`output cpu_stb_o;`
118			output [`CPU_NUM -1:0] cpu_sel_o;
119			`output cpu_we_o;`
120			`input cpu_ack_i;`
121			`output cpu_rst_o;`
122
123
124	100	mohor
125			`reg tdo_o;`
126
127			`wire cmd_cnt_en;`
128			`reg [1:0] cmd_cnt;`
129			`wire cmd_cnt_end;`
130			`reg cmd_cnt_end_q;`
131			`wire addr_cnt_en;`
132			`reg [5:0] addr_cnt;`
133			`reg [5:0] addr_cnt_limit;`
134			`wire addr_cnt_end;`
135			`wire crc_cnt_en;`
136			`reg [5:0] crc_cnt;`
137			`wire crc_cnt_end;`
138			`reg crc_cnt_end_q;`
139			`wire data_cnt_en;`
140			`reg [5:0] data_cnt;`
141			`reg [5:0] data_cnt_limit;`
142			`wire data_cnt_end;`
143			`reg data_cnt_end_q;`
144			`wire status_cnt_end;`
145			`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
146			`reg [3:0] status;`
147
148			`wire enable;`
149
150			`reg read_cycle_reg;`
151	101	mohor	`reg read_cycle_reg_q;`
152	100	mohor	`reg read_cycle_cpu;`
153	101	mohor	`reg read_cycle_cpu_q;`
154	100	mohor	`reg write_cycle_reg;`
155			`reg write_cycle_cpu;`
156			`wire read_cycle;`
157			`wire write_cycle;`
158
159			`reg [34:0] dr;`
160	101	mohor	`wire [7:0] reg_data_out;`
161	100	mohor
162			`wire dr_read_reg;`
163			`wire dr_write_reg;`
164			`wire dr_read_cpu8;`
165			`wire dr_read_cpu32;`
166			`wire dr_write_cpu8;`
167			`wire dr_write_cpu32;`
168			`wire dr_go;`
169
170			`reg dr_read_reg_latched;`
171			`reg dr_write_reg_latched;`
172			`reg dr_read_cpu8_latched;`
173			`reg dr_read_cpu32_latched;`
174			`reg dr_write_cpu8_latched;`
175			`reg dr_write_cpu32_latched;`
176			`reg dr_go_latched;`
177
178			`reg cmd_read_reg;`
179			`reg cmd_read_cpu;`
180			`reg cmd_write_reg;`
181			`reg cmd_write_cpu;`
182	101	mohor	`reg cycle_32_bit;`
183			`reg reg_access;`
184	100	mohor
185	101	mohor	`reg [31:0] adr;`
186			`reg set_addr;`
187			`reg [199:0] latching_data_text;`
188			`reg cpu_ack_sync;`
189			`reg cpu_ack_tck;`
190			`reg cpu_ack_tck_q;`
191			`reg cpu_stb;`
192			`reg cpu_stb_sync;`
193			`reg cpu_stb_o;`
194
195	100	mohor	`wire go_prelim;`
196			`wire crc_cnt_31;`
197
198
199	101	mohor
200	100	mohor	`assign enable = cpu_ce_i & shift_dr_i;`
201			`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
202			`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
203
204
205			`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
206
207
208			`// Command counter`
209			`always @ (posedge tck_i or posedge rst_i)`
210			`begin`
211			`if (rst_i)`
212			`cmd_cnt <= #1 'h0;`
213			`else if (update_dr_i)`
214			`cmd_cnt <= #1 'h0;`
215			`else if (cmd_cnt_en)`
216			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
217			`end`
218
219
220			`assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);`
221
222
223			`// Address/length counter`
224			`always @ (posedge tck_i or posedge rst_i)`
225			`begin`
226			`if (rst_i)`
227			`addr_cnt <= #1 'h0;`
228			`else if (update_dr_i)`
229			`addr_cnt <= #1 'h0;`
230			`else if (addr_cnt_en)`
231			`addr_cnt <= #1 addr_cnt + 1'b1;`
232			`end`
233
234
235			`assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle \| crc_cnt_end & read_cycle);`
236
237
238			`// Data counter`
239			`always @ (posedge tck_i or posedge rst_i)`
240			`begin`
241			`if (rst_i)`
242			`data_cnt <= #1 'h0;`
243			`else if (update_dr_i)`
244			`data_cnt <= #1 'h0;`
245			`else if (data_cnt_en)`
246			`data_cnt <= #1 data_cnt + 1'b1;`
247			`end`
248
249
250			`assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end & (~write_cycle) \| (data_cnt_end & write_cycle));`
251
252
253			`// crc counter`
254			`always @ (posedge tck_i or posedge rst_i)`
255			`begin`
256			`if (rst_i)`
257			`crc_cnt <= #1 'h0;`
258			`else if(crc_cnt_en)`
259			`crc_cnt <= #1 crc_cnt + 1'b1;`
260			`else if (update_dr_i)`
261			`crc_cnt <= #1 'h0;`
262			`end`
263
264
265			`// Upper limit. Address/length counter counts until this value is reached`
266			`always @ (posedge tck_i)`
267			`begin`
268			`if (cmd_cnt == 2'h2)`
269			`begin`
270			`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
271			`addr_cnt_limit = 6'd0;`
272			`else // (current command is WB_WRITEx or WB_READx)`
273			`addr_cnt_limit = 6'd32;`
274			`end`
275			`end`
276
277
278			`assign cmd_cnt_end = cmd_cnt == 2'h3;`
279			`assign addr_cnt_end = addr_cnt == addr_cnt_limit;`
280			`assign crc_cnt_end = crc_cnt == 6'd32;`
281			`assign crc_cnt_31 = crc_cnt == 6'd31;`
282			`assign data_cnt_end = (data_cnt == data_cnt_limit);`
283
284			`always @ (posedge tck_i)`
285			`begin`
286			`crc_cnt_end_q <= #1 crc_cnt_end;`
287			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
288			`data_cnt_end_q <= #1 data_cnt_end;`
289			`end`
290
291
292			`// Status counter is made of 4 serialy connected registers`
293			`always @ (posedge tck_i or posedge rst_i)`
294			`begin`
295			`if (rst_i)`
296			`status_cnt1 <= #1 1'b0;`
297			`else if (update_dr_i)`
298			`status_cnt1 <= #1 1'b0;`
299			`else if (data_cnt_end & read_cycle \|`
300			`crc_cnt_end & (~read_cycle)`
301			`)`
302			`status_cnt1 <= #1 1'b1;`
303			`end`
304
305
306			`always @ (posedge tck_i or posedge rst_i)`
307			`begin`
308			`if (rst_i)`
309			`begin`
310			`status_cnt2 <= #1 1'b0;`
311			`status_cnt3 <= #1 1'b0;`
312			`status_cnt4 <= #1 1'b0;`
313			`end`
314			`else if (update_dr_i)`
315			`begin`
316			`status_cnt2 <= #1 1'b0;`
317			`status_cnt3 <= #1 1'b0;`
318			`status_cnt4 <= #1 1'b0;`
319			`end`
320			`else`
321			`begin`
322			`status_cnt2 <= #1 status_cnt1;`
323			`status_cnt3 <= #1 status_cnt2;`
324			`status_cnt4 <= #1 status_cnt3;`
325			`end`
326			`end`
327
328
329			`assign status_cnt_end = status_cnt4;`
330
331
332
333
334			`// Latching address`
335			`always @ (posedge tck_i)`
336			`begin`
337			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
338			`begin`
339			`if (~dr_go_latched)`
340			`begin`
341			`adr <= #1 dr[31:0];`
342			`set_addr <= #1 1'b1;`
343			`end`
344			`end`
345			`else`
346			`set_addr <= #1 1'b0;`
347			`end`
348
349
350	101	mohor	`assign cpu_addr_o = adr;`
351	100	mohor
352	101	mohor
353	100	mohor	`// Shift register for shifting in and out the data`
354			`always @ (posedge tck_i)`
355			`begin`
356	101	mohor	`if (reg_access)`
357	100	mohor	`begin`
358	101	mohor	`dr[31:24] <= #1 reg_data_out;`
359			`latching_data_text = "Latch reg data";`
360			`end`
361			`else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)`
362			`begin`
363			`if (cycle_32_bit)`
364			`dr[31:0] <= #1 cpu_data_i;`
365			`else`
366			`dr[31:24] <= #1 cpu_data_i[7:0];`
367			`latching_data_text = "Latch cpu data";`
368			`end`
369			`else if (enable & ((~addr_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle) \| (crc_cnt_end & (~data_cnt_end) & read_cycle)))`
370			`begin`
371	100	mohor	`dr <= #1 {dr[33:0], tdi_i};`
372	101	mohor	`latching_data_text = "shifting data";`
373	100	mohor	`end`
374			`else`
375			`latching_data_text = "nothing";`
376			`end`
377
378
379			assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
380			assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
381			assign dr_read_cpu8 = dr[2:0] == `CPU_READ8;
382			assign dr_read_cpu32 = dr[2:0] == `CPU_READ32;
383			assign dr_write_cpu8 = dr[2:0] == `CPU_WRITE8;
384			assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
385			assign dr_go = dr[2:0] == `CPU_GO;
386
387
388			`// Latching instruction`
389			`always @ (posedge tck_i)`
390			`begin`
391			`if (update_dr_i)`
392			`begin`
393			`dr_read_reg_latched <= #1 1'b0;`
394			`dr_read_cpu8_latched <= #1 1'b0;`
395			`dr_read_cpu32_latched <= #1 1'b0;`
396			`dr_write_reg_latched <= #1 1'b0;`
397			`dr_write_cpu8_latched <= #1 1'b0;`
398			`dr_write_cpu32_latched <= #1 1'b0;`
399			`dr_go_latched <= #1 1'b0;`
400			`end`
401			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
402			`begin`
403			`dr_read_reg_latched <= #1 dr_read_reg;`
404			`dr_read_cpu8_latched <= #1 dr_read_cpu8;`
405			`dr_read_cpu32_latched <= #1 dr_read_cpu32;`
406			`dr_write_reg_latched <= #1 dr_write_reg;`
407			`dr_write_cpu8_latched <= #1 dr_write_cpu8;`
408			`dr_write_cpu32_latched <= #1 dr_write_cpu32;`
409			`dr_go_latched <= #1 dr_go;`
410			`end`
411			`end`
412
413			`// Latching instruction`
414			`always @ (posedge tck_i or posedge rst_i)`
415			`begin`
416			`if (rst_i)`
417			`begin`
418			`cmd_read_reg <= #1 1'b0;`
419			`cmd_read_cpu <= #1 1'b0;`
420			`cmd_write_reg <= #1 1'b0;`
421	101	mohor	`cmd_write_cpu <= #1 1'b0;`
422			`cycle_32_bit <= #1 1'b0;`
423	100	mohor	`end`
424			`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
425			`begin`
426			`cmd_read_reg <= #1 dr_read_reg_latched;`
427			`cmd_read_cpu <= #1 dr_read_cpu8_latched \| dr_read_cpu32_latched;`
428			`cmd_write_reg <= #1 dr_write_reg_latched;`
429			`cmd_write_cpu <= #1 dr_write_cpu8_latched \| dr_write_cpu32_latched;`
430	101	mohor	`cycle_32_bit <= #1 dr_read_cpu32_latched \| dr_write_cpu32_latched;`
431	100	mohor	`end`
432			`end`
433
434
435			`// Upper limit. Data counter counts until this value is reached.`
436			`always @ (posedge tck_i or posedge rst_i)`
437			`begin`
438			`if (rst_i)`
439			`data_cnt_limit <= #1 6'h0;`
440	101	mohor	`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))`
441	100	mohor	`begin`
442			`if (dr_read_cpu32_latched \| dr_write_cpu32_latched)`
443			`data_cnt_limit <= #1 6'd32;`
444			`else`
445			`data_cnt_limit <= #1 6'd8;`
446			`end`
447			`end`
448
449
450			`assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);`
451
452
453			`always @ (posedge tck_i)`
454			`begin`
455			`if (update_dr_i)`
456			`read_cycle_reg <= #1 1'b0;`
457			`else if (cmd_read_reg & go_prelim)`
458			`read_cycle_reg <= #1 1'b1;`
459			`end`
460
461
462			`always @ (posedge tck_i)`
463			`begin`
464			`if (update_dr_i)`
465			`read_cycle_cpu <= #1 1'b0;`
466			`else if (cmd_read_cpu & go_prelim)`
467			`read_cycle_cpu <= #1 1'b1;`
468			`end`
469
470
471			`always @ (posedge tck_i)`
472			`begin`
473	101	mohor	`read_cycle_reg_q <= #1 read_cycle_reg;`
474			`read_cycle_cpu_q <= #1 read_cycle_cpu;`
475			`end`
476
477
478			`always @ (posedge tck_i)`
479			`begin`
480	100	mohor	`if (update_dr_i)`
481			`write_cycle_reg <= #1 1'b0;`
482			`else if (cmd_write_reg & go_prelim)`
483			`write_cycle_reg <= #1 1'b1;`
484			`end`
485
486
487			`always @ (posedge tck_i)`
488			`begin`
489			`if (update_dr_i)`
490			`write_cycle_cpu <= #1 1'b0;`
491			`else if (cmd_write_cpu & go_prelim)`
492			`write_cycle_cpu <= #1 1'b1;`
493			`end`
494
495
496			`assign read_cycle = read_cycle_reg \| read_cycle_cpu;`
497			`assign write_cycle = write_cycle_reg \| write_cycle_cpu;`
498
499
500	101	mohor
501			`// Start register access cycle`
502	100	mohor	`always @ (posedge tck_i)`
503			`begin`
504	101	mohor	`if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) \| read_cycle_reg & (~read_cycle_reg_q))`
505	100	mohor	`begin`
506			`reg_access <= #1 1'b1;`
507			`end`
508			`else`
509			`reg_access <= #1 1'b0;`
510			`end`
511
512
513
514			`// Connecting dbg_cpu_registers`
515			`dbg_cpu_registers i_dbg_cpu_registers`
516			`(`
517	101	mohor	`.data_i (dr[7:0]),`
518			`.data_o (reg_data_out),`
519			`.addr_i (adr[1:0]),`
520			`.we_i (write_cycle_reg),`
521			`.en_i (reg_access),`
522			`.clk_i (tck_i),`
523			`.bp_i (cpu_bp_i),`
524			`.rst_i (rst_i),`
525			`.cpu_clk_i (cpu_clk_i),`
526			`.cpu_stall_o (cpu_stall_o),`
527			`.cpu_stall_all_o (cpu_stall_all_o),`
528			`.cpu_sel_o (cpu_sel_o),`
529			`.cpu_rst_o (cpu_rst_o)`
530	100	mohor	`);`
531
532
533
534	101	mohor	`assign cpu_we_o = write_cycle_cpu;`
535			`assign cpu_data_o = dr[31:0];`
536	100	mohor
537
538	101	mohor
539
540			`// Synchronizing ack signal from cpu`
541			`always @ (posedge tck_i)`
542			`begin`
543			`cpu_ack_sync <= #1 cpu_ack_i;`
544			`cpu_ack_tck <= #1 cpu_ack_sync;`
545			`cpu_ack_tck_q <= #1 cpu_ack_tck;`
546			`end`
547
548
549
550			`// Start cpu access cycle`
551			`always @ (posedge tck_i)`
552			`begin`
553			`if (update_dr_i)`
554			`cpu_stb <= #1 1'b0;`
555			`else if (cpu_ack_tck)`
556			`cpu_stb <= #1 1'b0;`
557			`else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) \| read_cycle_cpu & (~read_cycle_cpu_q))`
558			`cpu_stb <= #1 1'b1;`
559			`end`
560
561
562
563			`always @ (posedge tck_i)`
564			`begin`
565			`cpu_stb_sync <= #1 cpu_stb;`
566			`cpu_stb_o <= #1 cpu_stb_sync;`
567			`end`
568
569
570
571
572
573
574	100	mohor	`endmodule`
575