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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 158

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/10/23 16:17:00  mohor
// CRC logic changed.
//
// Revision 1.13  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.12  2003/09/17 14:38:57  simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.11  2003/08/28 13:55:21  simons
// Three more chains added for cpu debug access.
//
// Revision 1.10  2003/07/31 12:19:49  simons
// Multiple cpu support added.
//
// Revision 1.9  2002/05/07 14:43:59  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.8  2002/01/25 07:58:34  mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.7  2001/12/06 10:08:06  mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.6  2001/11/28 09:38:30  mohor
// Trace disabled by default.
//
// Revision 1.5  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:08  mohor
// Initial release
//
//
 
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 3
 
// Length of data
`define CHAIN_DATA_LEN  `CHAIN_ID_LENGTH + 1
`define DATA_CNT        3
 
// Length of status
`define STATUS_LEN      4
`define STATUS_CNT      3
 
// Length of the CRC
`define CRC_LEN         32
`define CRC_CNT         6
 
// Chains
`define CPU_DEBUG_CHAIN     3'b000
`define WISHBONE_SCAN_CHAIN 3'b001
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7	81	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	81	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	81	mohor	`//// Copyright (C) 2000 - 2003 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	81	mohor	`// Revision 1.14 2003/10/23 16:17:00 mohor`
47			`// CRC logic changed.`
48			`//`
49	73	mohor	`// Revision 1.13 2003/10/21 09:48:31 simons`
50			`// Mbist support added.`
51			`//`
52	71	simons	`// Revision 1.12 2003/09/17 14:38:57 simons`
53			`// WB_CNTL register added, some syncronization fixes.`
54			`//`
55	65	simons	`// Revision 1.11 2003/08/28 13:55:21 simons`
56			`// Three more chains added for cpu debug access.`
57			`//`
58	63	simons	`// Revision 1.10 2003/07/31 12:19:49 simons`
59			`// Multiple cpu support added.`
60			`//`
61	57	simons	`// Revision 1.9 2002/05/07 14:43:59 mohor`
62			`// mon_cntl_o signals that controls monitor mux added.`
63			`//`
64	47	mohor	`// Revision 1.8 2002/01/25 07:58:34 mohor`
65			`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`
66			`// not filled-in. Tested in hw.`
67			`//`
68	30	mohor	`// Revision 1.7 2001/12/06 10:08:06 mohor`
69			`// Warnings from synthesys tools fixed.`
70			`//`
71	27	mohor	`// Revision 1.6 2001/11/28 09:38:30 mohor`
72			`// Trace disabled by default.`
73			`//`
74	23	mohor	`// Revision 1.5 2001/10/15 09:55:47 mohor`
75			`// Wishbone interface added, few fixes for better performance,`
76			`// hooks for boundary scan testing added.`
77			`//`
78	12	mohor	`// Revision 1.4 2001/09/24 14:06:42 mohor`
79			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
80			`//`
81	11	mohor	`// Revision 1.3 2001/09/20 10:11:25 mohor`
82			`// Working version. Few bugs fixed, comments added.`
83			`//`
84	9	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
85			`// Trace fixed. Some registers changed, trace simplified.`
86			`//`
87	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
88			`// Initial official release.`
89			`//`
90	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
91			`// This is a backup. It is not a fully working version. Not for use, yet.`
92			`//`
93			`// Revision 1.2 2001/05/18 13:10:00 mohor`
94			`// Headers changed. All additional information is now avaliable in the README.txt file.`
95			`//`
96			`// Revision 1.1.1.1 2001/05/18 06:35:08 mohor`
97			`// Initial release`
98			`//`
99			`//`
100
101
102	81	mohor	`// Length of the CHAIN ID register`
103			`define CHAIN_ID_LENGTH 3
104	2	mohor
105	81	mohor	`// Length of data`
106			`define CHAIN_DATA_LEN `CHAIN_ID_LENGTH + 1
107			`define DATA_CNT 3
108	2	mohor
109	81	mohor	`// Length of status`
110			`define STATUS_LEN 4
111			`define STATUS_CNT 3
112	2	mohor
113			`// Length of the CRC`
114	81	mohor	`define CRC_LEN 32
115			`define CRC_CNT 6
116	2	mohor
117			`// Chains`
118	81	mohor	`define CPU_DEBUG_CHAIN 3'b000
119			`define WISHBONE_SCAN_CHAIN 3'b001
120	2	mohor

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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 158