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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_top.v ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000,2001, 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.32 2003/09/18 14:00:47 simons
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// Lower two address lines must be always zero.
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//
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// Revision 1.31 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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//
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// Revision 1.30 2003/08/28 13:55:22 simons
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// Three more chains added for cpu debug access.
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//
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// Revision 1.29 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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//
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// Revision 1.28 2002/11/06 14:22:41 mohor
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// Trst signal is not inverted here any more. Inverted on higher layer !!!.
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//
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// Revision 1.27 2002/10/10 02:42:55 mohor
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// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).
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// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,
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// wb_cyc_o is negated.
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//
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// Revision 1.26 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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//
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Intentional error removed.
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//
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// Revision 1.23 2002/04/17 11:16:33 mohor
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// A block for checking possible simulation/synthesis missmatch added.
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//
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// Revision 1.22 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// contains only tap state machine and related logic. dbg_top contains all
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// logic necessery for debugging.
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//
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// Revision 1.21 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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// Revision 1.20 2002/02/06 12:23:09 mohor
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// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
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//
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// Revision 1.19 2002/02/05 13:34:51 mohor
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// Stupid bug that was entered by previous update fixed.
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//
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// Revision 1.18 2002/02/05 12:41:01 mohor
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// trst synchronization is not needed and was removed.
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//
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// Revision 1.17 2002/01/25 07:58:35 mohor
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
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// not filled-in. Tested in hw.
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//
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// Revision 1.16 2001/12/20 11:17:26 mohor
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// TDO and TDO Enable signal are separated into two signals.
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//
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// Revision 1.15 2001/12/05 13:28:21 mohor
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// trst signal is synchronized to wb_clk_i.
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//
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Register length fixed.
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//
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// CRC is returned when chain selection data is transmitted.
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//
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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//
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Reset signals are not combined any more.
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//
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// Revision 1.9 2001/10/19 11:40:01 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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//
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// Revision 1.8 2001/10/17 10:39:03 mohor
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// bs_chain_o added.
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//
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// Revision 1.7 2001/10/16 10:09:56 mohor
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// Signal names changed to lowercase.
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//
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//
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// Revision 1.6 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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//
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// Revision 1.5 2001/09/24 14:06:42 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.3 2001/09/19 11:55:13 mohor
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// Asynchronous set/reset not used in trace any more.
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
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// Initial release
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "dbg_defines.v"
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// Top module
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module dbg_top(
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// CPU signals
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cpu_clk_i, cpu_addr_o, cpu_data_i, cpu_data_o, wp_i,
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bp_i, opselect_o, lsstatus_i, istatus_i,
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cpu_stall_o, cpu_stall_all_o, cpu_sel_o, reset_o,
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// WISHBONE common signals
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wb_rst_i, wb_clk_i,
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// WISHBONE master interface
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wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
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wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
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// TAP states
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ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, SelectDRScan,
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// Instructions
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
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// TAP signals
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trst_in, tck, tdi, TDOData,
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BypassRegister,
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// Monitor mux control
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mon_cntl_o,
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// Selected chains
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RegisterScanChain,
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CpuDebugScanChain0,
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CpuDebugScanChain1,
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CpuDebugScanChain2,
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CpuDebugScanChain3,
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WishboneScanChain
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);
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parameter Tp = 1;
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// CPU signals
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input cpu_clk_i; // Master clock (CPU clock)
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input [31:0] cpu_data_i; // CPU data inputs (data that is written to the CPU registers)
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input [10:0] wp_i; // Watchpoint inputs
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input bp_i; // Breakpoint input
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input [3:0] lsstatus_i; // Load/store status inputs
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input [1:0] istatus_i; // Instruction status inputs
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output [31:0] cpu_addr_o; // CPU address output (for adressing registers within CPU)
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output [31:0] cpu_data_o; // CPU data output (data read from cpu registers)
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output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
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output cpu_stall_o; // Stalls the selected CPU
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output cpu_stall_all_o; // Stalls all the rest CPUs
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output [`CPU_NUM-1:0] cpu_sel_o; // Stalls all the rest CPUs
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output reset_o; // Resets the CPU
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// WISHBONE common signals
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input wb_rst_i; // WISHBONE reset
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input wb_clk_i; // WISHBONE clock
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// WISHBONE master interface
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_stb_o;
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output [3:0] wb_sel_o;
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output wb_we_o;
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input wb_ack_i;
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output wb_cab_o;
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input wb_err_i;
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// TAP states
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input ShiftDR;
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input Exit1DR;
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input UpdateDR;
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input UpdateDR_q;
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input SelectDRScan;
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input trst_in;
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input tck;
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input tdi;
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input BypassRegister;
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output TDOData;
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output [3:0] mon_cntl_o;
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// Defining which instruction is selected
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input IDCODESelected;
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input CHAIN_SELECTSelected;
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input DEBUGSelected;
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mohor |
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// Selected chains
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output RegisterScanChain;
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output CpuDebugScanChain0;
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output CpuDebugScanChain1;
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output CpuDebugScanChain2;
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output CpuDebugScanChain3;
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output WishboneScanChain;
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mohor |
reg wb_cyc_o;
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reg [31:0] ADDR;
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reg [31:0] DataOut;
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reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the cpu_data_i)
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mohor |
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mohor |
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
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reg [31:0] DataReadLatch; // Data when reading register or CPU is latched one cpu_clk_i clock after the data is read.
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mohor |
reg RegAccessTck; // Indicates access to the registers (read or write)
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reg CPUAccessTck0; // Indicates access to the CPU (read or write)
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reg CPUAccessTck1; // Indicates access to the CPU (read or write)
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reg CPUAccessTck2; // Indicates access to the CPU (read or write)
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reg CPUAccessTck3; // Indicates access to the CPU (read or write)
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mohor |
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
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reg RW; // Read/Write bit
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reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
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mohor |
reg CrcMatch_q;
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mohor |
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mohor |
reg RegAccess_q; // Delayed signals used for accessing the registers
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reg RegAccess_q2; // Delayed signals used for accessing the registers
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mohor |
reg CPUAccess_q; // Delayed signals used for accessing the CPU
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reg CPUAccess_q2; // Delayed signals used for accessing the CPU
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reg CPUAccess_q3; // Delayed signals used for accessing the CPU
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mohor |
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mohor |
reg wb_AccessTck; // Indicates access to the WISHBONE
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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mohor |
reg WBInProgress; // WISHBONE access is in progress
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reg [7:0] WBAccessCounter; // Counting access cycles. WBInProgress is cleared to 0 after counter exceeds 0xff
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wire WBAccessCounterExceed; // Marks when the WBAccessCounter exceeds max value (oxff)
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reg WBInProgress_sync1; // Synchronizing WBInProgress
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reg WBInProgress_tck; // Synchronizing WBInProgress to tck clock signal
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306 |
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mohor |
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307 |
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mohor |
wire trst;
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308 |
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309 |
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mohor |
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310 |
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mohor |
wire [31:0] RegDataIn; // Data from registers (read data)
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wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
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312 |
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mohor |
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mohor |
wire CpuStall_reg; // CPU is stalled by setting the register bit
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314 |
|
|
wire CpuReset_reg; // CPU is reset by setting the register bit
|
315 |
|
|
wire CpuStall_trace; // CPU is stalled by trace module
|
316 |
9 |
mohor |
|
317 |
|
|
|
318 |
73 |
mohor |
wire CpuStall_read_access_0; // Stalling Cpu because of the read access (SPR read)
|
319 |
|
|
wire CpuStall_read_access_1; // Stalling Cpu because of the read access (SPR read)
|
320 |
|
|
wire CpuStall_read_access_2; // Stalling Cpu because of the read access (SPR read)
|
321 |
|
|
wire CpuStall_read_access_3; // Stalling Cpu because of the read access (SPR read)
|
322 |
|
|
wire CpuStall_write_access_0; // Stalling Cpu because of the write access (SPR write)
|
323 |
|
|
wire CpuStall_write_access_1; // Stalling Cpu because of the write access (SPR write)
|
324 |
|
|
wire CpuStall_write_access_2; // Stalling Cpu because of the write access (SPR write)
|
325 |
|
|
wire CpuStall_write_access_3; // Stalling Cpu because of the write access (SPR write)
|
326 |
|
|
wire CpuStall_access; // Stalling Cpu because of the read or write access
|
327 |
11 |
mohor |
|
328 |
30 |
mohor |
wire BitCounter_Lt4;
|
329 |
|
|
wire BitCounter_Eq5;
|
330 |
|
|
wire BitCounter_Eq32;
|
331 |
|
|
wire BitCounter_Lt38;
|
332 |
|
|
wire BitCounter_Lt65;
|
333 |
|
|
|
334 |
15 |
mohor |
|
335 |
|
|
|
336 |
9 |
mohor |
// This signals are used only when TRACE is used in the design
|
337 |
2 |
mohor |
`ifdef TRACE_ENABLED
|
338 |
9 |
mohor |
wire [39:0] TraceChain; // Chain that comes from trace module
|
339 |
36 |
mohor |
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with tck)
|
340 |
9 |
mohor |
wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
|
341 |
|
|
reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
|
342 |
|
|
wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
|
343 |
2 |
mohor |
|
344 |
|
|
// Outputs from registers
|
345 |
9 |
mohor |
wire ContinMode; // Trace working in continous mode
|
346 |
|
|
wire TraceEnable; // Trace enabled
|
347 |
2 |
mohor |
|
348 |
9 |
mohor |
wire [10:0] WpTrigger; // Watchpoint starts trigger
|
349 |
|
|
wire BpTrigger; // Breakpoint starts trigger
|
350 |
|
|
wire [3:0] LSSTrigger; // Load/store status starts trigger
|
351 |
|
|
wire [1:0] ITrigger; // Instruction status starts trigger
|
352 |
|
|
wire [1:0] TriggerOper; // Trigger operation
|
353 |
2 |
mohor |
|
354 |
9 |
mohor |
wire WpTriggerValid; // Watchpoint trigger is valid
|
355 |
|
|
wire BpTriggerValid; // Breakpoint trigger is valid
|
356 |
|
|
wire LSSTriggerValid; // Load/store status trigger is valid
|
357 |
|
|
wire ITriggerValid; // Instruction status trigger is valid
|
358 |
2 |
mohor |
|
359 |
9 |
mohor |
wire [10:0] WpQualif; // Watchpoint starts qualifier
|
360 |
|
|
wire BpQualif; // Breakpoint starts qualifier
|
361 |
|
|
wire [3:0] LSSQualif; // Load/store status starts qualifier
|
362 |
|
|
wire [1:0] IQualif; // Instruction status starts qualifier
|
363 |
|
|
wire [1:0] QualifOper; // Qualifier operation
|
364 |
2 |
mohor |
|
365 |
9 |
mohor |
wire WpQualifValid; // Watchpoint qualifier is valid
|
366 |
|
|
wire BpQualifValid; // Breakpoint qualifier is valid
|
367 |
|
|
wire LSSQualifValid; // Load/store status qualifier is valid
|
368 |
|
|
wire IQualifValid; // Instruction status qualifier is valid
|
369 |
2 |
mohor |
|
370 |
9 |
mohor |
wire [10:0] WpStop; // Watchpoint stops recording of the trace
|
371 |
|
|
wire BpStop; // Breakpoint stops recording of the trace
|
372 |
|
|
wire [3:0] LSSStop; // Load/store status stops recording of the trace
|
373 |
|
|
wire [1:0] IStop; // Instruction status stops recording of the trace
|
374 |
|
|
wire [1:0] StopOper; // Stop operation
|
375 |
2 |
mohor |
|
376 |
9 |
mohor |
wire WpStopValid; // Watchpoint stop is valid
|
377 |
|
|
wire BpStopValid; // Breakpoint stop is valid
|
378 |
|
|
wire LSSStopValid; // Load/store status stop is valid
|
379 |
|
|
wire IStopValid; // Instruction status stop is valid
|
380 |
2 |
mohor |
|
381 |
9 |
mohor |
wire RecordPC; // Recording program counter
|
382 |
|
|
wire RecordLSEA; // Recording load/store effective address
|
383 |
|
|
wire RecordLDATA; // Recording load data
|
384 |
|
|
wire RecordSDATA; // Recording store data
|
385 |
|
|
wire RecordReadSPR; // Recording read SPR
|
386 |
|
|
wire RecordWriteSPR; // Recording write SPR
|
387 |
|
|
wire RecordINSTR; // Recording instruction
|
388 |
2 |
mohor |
|
389 |
|
|
// End: Outputs from registers
|
390 |
|
|
|
391 |
9 |
mohor |
wire TraceTestScanChain; // Trace Test Scan chain selected
|
392 |
|
|
wire [47:0] Trace_Data; // Trace data
|
393 |
2 |
mohor |
|
394 |
11 |
mohor |
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
|
395 |
73 |
mohor |
// data is set to the cpu_data_i)
|
396 |
30 |
mohor |
wire BitCounter_Lt40;
|
397 |
11 |
mohor |
|
398 |
2 |
mohor |
`endif
|
399 |
|
|
|
400 |
|
|
|
401 |
52 |
mohor |
assign trst = trst_in; // trst_pad_i is active high !!! Inverted on higher layer.
|
402 |
25 |
mohor |
|
403 |
|
|
|
404 |
2 |
mohor |
/**********************************************************************************
|
405 |
|
|
* *
|
406 |
|
|
* JTAG_DR: JTAG Data Register *
|
407 |
|
|
* *
|
408 |
|
|
**********************************************************************************/
|
409 |
|
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
410 |
|
|
reg TDOData;
|
411 |
|
|
|
412 |
|
|
|
413 |
36 |
mohor |
always @ (posedge tck or posedge trst)
|
414 |
2 |
mohor |
begin
|
415 |
18 |
mohor |
if(trst)
|
416 |
2 |
mohor |
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
417 |
|
|
else
|
418 |
30 |
mohor |
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
419 |
|
|
begin
|
420 |
|
|
if(ShiftDR)
|
421 |
36 |
mohor |
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
|
422 |
30 |
mohor |
else
|
423 |
|
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
424 |
|
|
end
|
425 |
|
|
else
|
426 |
|
|
if(CHAIN_SELECTSelected & ShiftDR)
|
427 |
36 |
mohor |
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
428 |
30 |
mohor |
else
|
429 |
|
|
if(DEBUGSelected & ShiftDR)
|
430 |
|
|
begin
|
431 |
73 |
mohor |
if(CpuDebugScanChain0 | CpuDebugScanChain1 |
|
432 |
|
|
CpuDebugScanChain2 | CpuDebugScanChain3 | WishboneScanChain)
|
433 |
36 |
mohor |
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
434 |
30 |
mohor |
else
|
435 |
|
|
if(RegisterScanChain)
|
436 |
36 |
mohor |
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
437 |
30 |
mohor |
end
|
438 |
2 |
mohor |
end
|
439 |
30 |
mohor |
|
440 |
73 |
mohor |
wire [73:0] CPU_Data;
|
441 |
22 |
mohor |
wire [46:0] Register_Data;
|
442 |
|
|
wire [73:0] WISHBONE_Data;
|
443 |
21 |
mohor |
wire [12:0] chain_sel_data;
|
444 |
12 |
mohor |
wire wb_Access_wbClk;
|
445 |
65 |
simons |
wire [1:0] wb_cntl_o;
|
446 |
2 |
mohor |
|
447 |
|
|
|
448 |
73 |
mohor |
reg crc_bypassed;
|
449 |
36 |
mohor |
always @ (posedge tck or posedge trst)
|
450 |
30 |
mohor |
begin
|
451 |
|
|
if(trst)
|
452 |
73 |
mohor |
crc_bypassed <= 0;
|
453 |
|
|
else if (CHAIN_SELECTSelected)
|
454 |
|
|
crc_bypassed <=#Tp 1;
|
455 |
|
|
else if(
|
456 |
|
|
RegisterScanChain & BitCounter_Eq5 |
|
457 |
|
|
CpuDebugScanChain0 & BitCounter_Eq32 |
|
458 |
|
|
CpuDebugScanChain1 & BitCounter_Eq32 |
|
459 |
|
|
CpuDebugScanChain2 & BitCounter_Eq32 |
|
460 |
|
|
CpuDebugScanChain3 & BitCounter_Eq32 |
|
461 |
|
|
WishboneScanChain & BitCounter_Eq32 )
|
462 |
|
|
crc_bypassed <=#Tp tdi; // when write is performed.
|
463 |
30 |
mohor |
end
|
464 |
12 |
mohor |
|
465 |
73 |
mohor |
reg [7:0] send_crc;
|
466 |
|
|
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
467 |
20 |
mohor |
|
468 |
73 |
mohor |
// Calculated CRC is returned when read operation is performed, else received crc is returned (loopback).
|
469 |
|
|
always @ (crc_bypassed or CrcMatch or CrcMatch_q or BypassRegister or CalculatedCrcOut)
|
470 |
|
|
begin
|
471 |
|
|
if (crc_bypassed)
|
472 |
|
|
begin
|
473 |
|
|
if (CrcMatch | CrcMatch_q) // When crc is looped back, first bit is not inverted
|
474 |
|
|
send_crc = {8{BypassRegister}}; // since it caused the error. By inverting it we would
|
475 |
|
|
else // get ok crc.
|
476 |
|
|
send_crc = {8{~BypassRegister}};
|
477 |
|
|
end
|
478 |
|
|
else
|
479 |
|
|
begin
|
480 |
|
|
if (CrcMatch)
|
481 |
|
|
send_crc = {8{CalculatedCrcOut}};
|
482 |
|
|
else
|
483 |
|
|
send_crc = {8{~CalculatedCrcOut}};
|
484 |
|
|
end
|
485 |
|
|
end
|
486 |
20 |
mohor |
|
487 |
73 |
mohor |
assign CPU_Data = {send_crc, DataReadLatch, 33'h0, 1'b0};
|
488 |
|
|
assign Register_Data = {send_crc, DataReadLatch, 6'h0, 1'b0};
|
489 |
|
|
assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch, 1'b0};
|
490 |
|
|
assign chain_sel_data = {send_crc, 4'h0, 1'b0};
|
491 |
20 |
mohor |
|
492 |
|
|
|
493 |
|
|
`ifdef TRACE_ENABLED
|
494 |
2 |
mohor |
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
495 |
|
|
`endif
|
496 |
|
|
|
497 |
36 |
mohor |
//TDO is changing on the falling edge of tck
|
498 |
|
|
always @ (negedge tck or posedge trst)
|
499 |
2 |
mohor |
begin
|
500 |
18 |
mohor |
if(trst)
|
501 |
2 |
mohor |
begin
|
502 |
|
|
TDOData <= #Tp 0;
|
503 |
|
|
`ifdef TRACE_ENABLED
|
504 |
|
|
ReadBuffer_Tck<=#Tp 0;
|
505 |
|
|
`endif
|
506 |
|
|
end
|
507 |
|
|
else
|
508 |
|
|
if(UpdateDR)
|
509 |
|
|
begin
|
510 |
|
|
TDOData <= #Tp CrcMatch;
|
511 |
|
|
`ifdef TRACE_ENABLED
|
512 |
9 |
mohor |
if(DEBUGSelected & TraceTestScanChain & TraceChain[0]) // Sample in the trace buffer is valid
|
513 |
|
|
ReadBuffer_Tck<=#Tp 1; // Increment read pointer
|
514 |
2 |
mohor |
`endif
|
515 |
|
|
end
|
516 |
|
|
else
|
517 |
|
|
begin
|
518 |
|
|
if(ShiftDR)
|
519 |
|
|
begin
|
520 |
|
|
if(IDCODESelected)
|
521 |
36 |
mohor |
TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
|
522 |
2 |
mohor |
else
|
523 |
|
|
if(CHAIN_SELECTSelected)
|
524 |
21 |
mohor |
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
525 |
2 |
mohor |
else
|
526 |
|
|
if(DEBUGSelected)
|
527 |
|
|
begin
|
528 |
73 |
mohor |
if(CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3)
|
529 |
|
|
TDOData <= #Tp CPU_Data[BitCounter]; // Data read from CPU in the previous cycle is shifted out
|
530 |
2 |
mohor |
else
|
531 |
|
|
if(RegisterScanChain)
|
532 |
9 |
mohor |
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
|
533 |
12 |
mohor |
else
|
534 |
|
|
if(WishboneScanChain)
|
535 |
|
|
TDOData <= #Tp WISHBONE_Data[BitCounter]; // Data read from the WISHBONE slave
|
536 |
2 |
mohor |
`ifdef TRACE_ENABLED
|
537 |
|
|
else
|
538 |
|
|
if(TraceTestScanChain)
|
539 |
9 |
mohor |
TDOData <= #Tp Trace_Data[BitCounter]; // Data from the trace buffer is shifted out
|
540 |
2 |
mohor |
`endif
|
541 |
|
|
end
|
542 |
|
|
end
|
543 |
|
|
else
|
544 |
|
|
begin
|
545 |
|
|
TDOData <= #Tp 0;
|
546 |
|
|
`ifdef TRACE_ENABLED
|
547 |
|
|
ReadBuffer_Tck<=#Tp 0;
|
548 |
|
|
`endif
|
549 |
|
|
end
|
550 |
|
|
end
|
551 |
|
|
end
|
552 |
|
|
|
553 |
42 |
mohor |
|
554 |
|
|
//synopsys translate_off
|
555 |
|
|
always @ (posedge tck)
|
556 |
|
|
begin
|
557 |
|
|
if(ShiftDR & CHAIN_SELECTSelected & BitCounter > 12)
|
558 |
|
|
begin
|
559 |
|
|
$display("\n%m Error: BitCounter is bigger then chain_sel_data bits width[12:0]. BitCounter=%d\n",BitCounter);
|
560 |
|
|
$stop;
|
561 |
|
|
end
|
562 |
|
|
else
|
563 |
|
|
if(ShiftDR & DEBUGSelected)
|
564 |
|
|
begin
|
565 |
73 |
mohor |
if((CpuDebugScanChain0 | CpuDebugScanChain1 | CpuDebugScanChain2 | CpuDebugScanChain3) & BitCounter > 73)
|
566 |
42 |
mohor |
begin
|
567 |
73 |
mohor |
$display("\n%m Error: BitCounter is bigger then CPU_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
568 |
42 |
mohor |
$stop;
|
569 |
|
|
end
|
570 |
|
|
else
|
571 |
43 |
mohor |
if(RegisterScanChain & BitCounter > 46)
|
572 |
42 |
mohor |
begin
|
573 |
73 |
mohor |
$display("\n%m Error: BitCounter is bigger then Register_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
|
574 |
42 |
mohor |
$stop;
|
575 |
|
|
end
|
576 |
|
|
else
|
577 |
|
|
if(WishboneScanChain & BitCounter > 73)
|
578 |
|
|
begin
|
579 |
|
|
$display("\n%m Error: BitCounter is bigger then WISHBONE_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
|
580 |
|
|
$stop;
|
581 |
|
|
end
|
582 |
|
|
`ifdef TRACE_ENABLED
|
583 |
|
|
else
|
584 |
|
|
if(TraceTestScanChain & BitCounter > 47)
|
585 |
|
|
begin
|
586 |
|
|
$display("\n%m Error: BitCounter is bigger then Trace_Data bits width[47:0]. BitCounter=%d\n",BitCounter);
|
587 |
|
|
$stop;
|
588 |
|
|
end
|
589 |
|
|
`endif
|
590 |
|
|
end
|
591 |
|
|
end
|
592 |
|
|
// synopsys translate_on
|
593 |
|
|
|
594 |
|
|
|
595 |
|
|
|
596 |
|
|
|
597 |
|
|
|
598 |
|
|
|
599 |
|
|
|
600 |
|
|
|
601 |
2 |
mohor |
/**********************************************************************************
|
602 |
|
|
* *
|
603 |
|
|
* End: JTAG_DR *
|
604 |
|
|
* *
|
605 |
|
|
**********************************************************************************/
|
606 |
|
|
|
607 |
|
|
|
608 |
|
|
|
609 |
|
|
/**********************************************************************************
|
610 |
|
|
* *
|
611 |
|
|
* CHAIN_SELECT logic *
|
612 |
|
|
* *
|
613 |
|
|
**********************************************************************************/
|
614 |
36 |
mohor |
always @ (posedge tck or posedge trst)
|
615 |
2 |
mohor |
begin
|
616 |
18 |
mohor |
if(trst)
|
617 |
9 |
mohor |
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
618 |
2 |
mohor |
else
|
619 |
|
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
620 |
9 |
mohor |
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
|
621 |
2 |
mohor |
end
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
|
625 |
|
|
/**********************************************************************************
|
626 |
|
|
* *
|
627 |
|
|
* Register read/write logic *
|
628 |
73 |
mohor |
* CPU registers read/write logic *
|
629 |
2 |
mohor |
* *
|
630 |
|
|
**********************************************************************************/
|
631 |
36 |
mohor |
always @ (posedge tck or posedge trst)
|
632 |
2 |
mohor |
begin
|
633 |
18 |
mohor |
if(trst)
|
634 |
2 |
mohor |
begin
|
635 |
|
|
ADDR[31:0] <=#Tp 32'h0;
|
636 |
|
|
DataOut[31:0] <=#Tp 32'h0;
|
637 |
|
|
RW <=#Tp 1'b0;
|
638 |
|
|
RegAccessTck <=#Tp 1'b0;
|
639 |
73 |
mohor |
CPUAccessTck0 <=#Tp 1'b0;
|
640 |
|
|
CPUAccessTck1 <=#Tp 1'b0;
|
641 |
|
|
CPUAccessTck2 <=#Tp 1'b0;
|
642 |
|
|
CPUAccessTck3 <=#Tp 1'b0;
|
643 |
12 |
mohor |
wb_AccessTck <=#Tp 1'h0;
|
644 |
2 |
mohor |
end
|
645 |
|
|
else
|
646 |
|
|
if(UpdateDR & DEBUGSelected & CrcMatch)
|
647 |
|
|
begin
|
648 |
|
|
if(RegisterScanChain)
|
649 |
|
|
begin
|
650 |
|
|
ADDR[4:0] <=#Tp JTAG_DR_IN[4:0]; // Latching address for register access
|
651 |
|
|
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
|
652 |
|
|
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
|
653 |
|
|
RegAccessTck <=#Tp 1'b1;
|
654 |
|
|
end
|
655 |
|
|
else
|
656 |
63 |
simons |
if(WishboneScanChain & (!WBInProgress_tck))
|
657 |
2 |
mohor |
begin
|
658 |
63 |
simons |
ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
|
659 |
|
|
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
660 |
|
|
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
661 |
|
|
wb_AccessTck <=#Tp 1'b1; //
|
662 |
|
|
end
|
663 |
|
|
else
|
664 |
73 |
mohor |
if(CpuDebugScanChain0)
|
665 |
63 |
simons |
begin
|
666 |
73 |
mohor |
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
667 |
2 |
mohor |
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
668 |
|
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
669 |
73 |
mohor |
CPUAccessTck0 <=#Tp 1'b1;
|
670 |
2 |
mohor |
end
|
671 |
12 |
mohor |
else
|
672 |
73 |
mohor |
if(CpuDebugScanChain1)
|
673 |
12 |
mohor |
begin
|
674 |
73 |
mohor |
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
675 |
20 |
mohor |
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
676 |
63 |
simons |
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
677 |
73 |
mohor |
CPUAccessTck1 <=#Tp 1'b1;
|
678 |
12 |
mohor |
end
|
679 |
63 |
simons |
else
|
680 |
73 |
mohor |
if(CpuDebugScanChain2)
|
681 |
63 |
simons |
begin
|
682 |
73 |
mohor |
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
683 |
63 |
simons |
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
684 |
|
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
685 |
73 |
mohor |
CPUAccessTck2 <=#Tp 1'b1;
|
686 |
63 |
simons |
end
|
687 |
|
|
else
|
688 |
73 |
mohor |
if(CpuDebugScanChain3)
|
689 |
63 |
simons |
begin
|
690 |
73 |
mohor |
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for CPU register access
|
691 |
63 |
simons |
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
|
692 |
|
|
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
|
693 |
73 |
mohor |
CPUAccessTck3 <=#Tp 1'b1;
|
694 |
63 |
simons |
end
|
695 |
2 |
mohor |
end
|
696 |
|
|
else
|
697 |
|
|
begin
|
698 |
36 |
mohor |
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
699 |
12 |
mohor |
wb_AccessTck <=#Tp 1'b0;
|
700 |
73 |
mohor |
CPUAccessTck0 <=#Tp 1'b0;
|
701 |
|
|
CPUAccessTck1 <=#Tp 1'b0;
|
702 |
|
|
CPUAccessTck2 <=#Tp 1'b0;
|
703 |
|
|
CPUAccessTck3 <=#Tp 1'b0;
|
704 |
2 |
mohor |
end
|
705 |
|
|
end
|
706 |
|
|
|
707 |
20 |
mohor |
|
708 |
67 |
simons |
assign wb_adr_o = {ADDR[31:2] & {30{wb_cyc_o}}, 2'b0};
|
709 |
65 |
simons |
assign wb_we_o = RW & wb_cyc_o;
|
710 |
12 |
mohor |
assign wb_cab_o = 1'b0;
|
711 |
65 |
simons |
|
712 |
67 |
simons |
reg [31:0] wb_dat_o;
|
713 |
|
|
always @(wb_sel_o or wb_cyc_o or DataOut)
|
714 |
|
|
begin
|
715 |
|
|
if(wb_cyc_o)
|
716 |
|
|
case (wb_sel_o)
|
717 |
|
|
4'b0001: wb_dat_o = {24'hx, DataOut[7:0]};
|
718 |
|
|
4'b0010: wb_dat_o = {16'hx, DataOut[7:0], 8'hx};
|
719 |
|
|
4'b0100: wb_dat_o = {8'hx, DataOut[7:0], 16'hx};
|
720 |
|
|
4'b1000: wb_dat_o = {DataOut[7:0], 24'hx};
|
721 |
|
|
4'b0011: wb_dat_o = {16'hx, DataOut[15:0]};
|
722 |
|
|
4'b1100: wb_dat_o = {DataOut[15:0], 16'hx};
|
723 |
|
|
default: wb_dat_o = DataOut;
|
724 |
|
|
endcase
|
725 |
|
|
else
|
726 |
|
|
wb_dat_o = 32'hx;
|
727 |
|
|
end
|
728 |
|
|
|
729 |
65 |
simons |
reg [3:0] wb_sel_o;
|
730 |
|
|
always @(ADDR[1:0] or wb_cntl_o or wb_cyc_o)
|
731 |
|
|
begin
|
732 |
|
|
if(wb_cyc_o)
|
733 |
|
|
case (wb_cntl_o)
|
734 |
|
|
2'b00: wb_sel_o = 4'hf;
|
735 |
|
|
2'b01: wb_sel_o = ADDR[1] ? 4'h3 : 4'hc;
|
736 |
|
|
2'b10: wb_sel_o = ADDR[1] ? (ADDR[0] ? 4'h1 : 4'h2) : (ADDR[0] ? 4'h4 : 4'h8);
|
737 |
67 |
simons |
default: wb_sel_o = 4'hx;
|
738 |
65 |
simons |
endcase
|
739 |
|
|
else
|
740 |
67 |
simons |
wb_sel_o = 4'hx;
|
741 |
65 |
simons |
end
|
742 |
20 |
mohor |
|
743 |
73 |
mohor |
// Synchronizing the RegAccess signal to cpu_clk_i clock
|
744 |
|
|
dbg_sync_clk1_clk2 syn1 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
745 |
2 |
mohor |
.set2(RegAccessTck), .sync_out(RegAccess)
|
746 |
|
|
);
|
747 |
|
|
|
748 |
63 |
simons |
// Synchronizing the wb_Access signal to wishbone clock
|
749 |
|
|
dbg_sync_clk1_clk2 syn2 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
750 |
|
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
751 |
2 |
mohor |
);
|
752 |
|
|
|
753 |
73 |
mohor |
// Synchronizing the CPUAccess0 signal to cpu_clk_i clock
|
754 |
|
|
dbg_sync_clk1_clk2 syn3 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
755 |
|
|
.set2(CPUAccessTck0), .sync_out(CPUAccess0)
|
756 |
63 |
simons |
);
|
757 |
2 |
mohor |
|
758 |
73 |
mohor |
// Synchronizing the CPUAccess1 signal to cpu_clk_i clock
|
759 |
|
|
dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
760 |
|
|
.set2(CPUAccessTck1), .sync_out(CPUAccess1)
|
761 |
12 |
mohor |
);
|
762 |
|
|
|
763 |
73 |
mohor |
// Synchronizing the CPUAccess2 signal to cpu_clk_i clock
|
764 |
|
|
dbg_sync_clk1_clk2 syn5 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
765 |
|
|
.set2(CPUAccessTck2), .sync_out(CPUAccess2)
|
766 |
63 |
simons |
);
|
767 |
12 |
mohor |
|
768 |
73 |
mohor |
// Synchronizing the CPUAccess3 signal to cpu_clk_i clock
|
769 |
|
|
dbg_sync_clk1_clk2 syn6 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
770 |
|
|
.set2(CPUAccessTck3), .sync_out(CPUAccess3)
|
771 |
63 |
simons |
);
|
772 |
12 |
mohor |
|
773 |
|
|
|
774 |
|
|
|
775 |
63 |
simons |
|
776 |
|
|
|
777 |
73 |
mohor |
// Delayed signals used for accessing registers and CPU
|
778 |
|
|
always @ (posedge cpu_clk_i or posedge wb_rst_i)
|
779 |
2 |
mohor |
begin
|
780 |
18 |
mohor |
if(wb_rst_i)
|
781 |
2 |
mohor |
begin
|
782 |
|
|
RegAccess_q <=#Tp 1'b0;
|
783 |
|
|
RegAccess_q2 <=#Tp 1'b0;
|
784 |
73 |
mohor |
CPUAccess_q <=#Tp 1'b0;
|
785 |
|
|
CPUAccess_q2 <=#Tp 1'b0;
|
786 |
|
|
CPUAccess_q3 <=#Tp 1'b0;
|
787 |
2 |
mohor |
end
|
788 |
|
|
else
|
789 |
|
|
begin
|
790 |
|
|
RegAccess_q <=#Tp RegAccess;
|
791 |
|
|
RegAccess_q2 <=#Tp RegAccess_q;
|
792 |
73 |
mohor |
CPUAccess_q <=#Tp CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3;
|
793 |
|
|
CPUAccess_q2 <=#Tp CPUAccess_q;
|
794 |
|
|
CPUAccess_q3 <=#Tp CPUAccess_q2;
|
795 |
2 |
mohor |
end
|
796 |
|
|
end
|
797 |
|
|
|
798 |
73 |
mohor |
// Chip select and read/write signals for accessing CPU
|
799 |
|
|
assign CpuStall_write_access_0 = CPUAccess0 & ~CPUAccess_q2 & RW;
|
800 |
|
|
assign CpuStall_read_access_0 = CPUAccess0 & ~CPUAccess_q2 & ~RW;
|
801 |
|
|
assign CpuStall_write_access_1 = CPUAccess1 & ~CPUAccess_q2 & RW;
|
802 |
|
|
assign CpuStall_read_access_1 = CPUAccess1 & ~CPUAccess_q2 & ~RW;
|
803 |
|
|
assign CpuStall_write_access_2 = CPUAccess2 & ~CPUAccess_q2 & RW;
|
804 |
|
|
assign CpuStall_read_access_2 = CPUAccess2 & ~CPUAccess_q2 & ~RW;
|
805 |
|
|
assign CpuStall_write_access_3 = CPUAccess3 & ~CPUAccess_q2 & RW;
|
806 |
|
|
assign CpuStall_read_access_3 = CPUAccess3 & ~CPUAccess_q2 & ~RW;
|
807 |
|
|
assign CpuStall_access = (CPUAccess0 | CPUAccess1 | CPUAccess2 | CPUAccess3) & ~CPUAccess_q3;
|
808 |
2 |
mohor |
|
809 |
|
|
|
810 |
12 |
mohor |
reg wb_Access_wbClk_q;
|
811 |
|
|
// Delayed signals used for accessing WISHBONE
|
812 |
18 |
mohor |
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
813 |
12 |
mohor |
begin
|
814 |
18 |
mohor |
if(wb_rst_i)
|
815 |
12 |
mohor |
wb_Access_wbClk_q <=#Tp 1'b0;
|
816 |
|
|
else
|
817 |
|
|
wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
|
818 |
|
|
end
|
819 |
|
|
|
820 |
18 |
mohor |
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
821 |
12 |
mohor |
begin
|
822 |
18 |
mohor |
if(wb_rst_i)
|
823 |
12 |
mohor |
wb_cyc_o <=#Tp 1'b0;
|
824 |
|
|
else
|
825 |
51 |
mohor |
if(wb_Access_wbClk & ~wb_Access_wbClk_q)
|
826 |
12 |
mohor |
wb_cyc_o <=#Tp 1'b1;
|
827 |
|
|
else
|
828 |
51 |
mohor |
if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
|
829 |
12 |
mohor |
wb_cyc_o <=#Tp 1'b0;
|
830 |
|
|
end
|
831 |
|
|
|
832 |
|
|
assign wb_stb_o = wb_cyc_o;
|
833 |
|
|
|
834 |
|
|
|
835 |
|
|
// Latching data read from registers
|
836 |
19 |
mohor |
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
837 |
12 |
mohor |
begin
|
838 |
18 |
mohor |
if(wb_rst_i)
|
839 |
12 |
mohor |
WBReadLatch[31:0]<=#Tp 32'h0;
|
840 |
|
|
else
|
841 |
|
|
if(wb_ack_i)
|
842 |
67 |
simons |
case (wb_sel_o)
|
843 |
|
|
4'b0001: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[7:0]};
|
844 |
|
|
4'b0010: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[15:8]};
|
845 |
|
|
4'b0100: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[23:16]};
|
846 |
|
|
4'b1000: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[31:24]};
|
847 |
|
|
4'b0011: WBReadLatch[31:0]<=#Tp {16'h0, wb_dat_i[15:0]};
|
848 |
|
|
4'b1100: WBReadLatch[31:0]<=#Tp {16'h0, wb_dat_i[31:16]};
|
849 |
|
|
default: WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
|
850 |
|
|
endcase
|
851 |
12 |
mohor |
end
|
852 |
|
|
|
853 |
|
|
// Latching WISHBONE error cycle
|
854 |
18 |
mohor |
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
855 |
12 |
mohor |
begin
|
856 |
18 |
mohor |
if(wb_rst_i)
|
857 |
12 |
mohor |
WBErrorLatch<=#Tp 1'b0;
|
858 |
|
|
else
|
859 |
|
|
if(wb_err_i)
|
860 |
|
|
WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
|
861 |
20 |
mohor |
else
|
862 |
12 |
mohor |
if(wb_ack_i)
|
863 |
|
|
WBErrorLatch<=#Tp 1'b0; // Clearing status
|
864 |
|
|
end
|
865 |
|
|
|
866 |
|
|
|
867 |
51 |
mohor |
// WBInProgress is set at the beginning of the access and cleared when wb_ack_i or wb_err_i is set
|
868 |
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
869 |
|
|
begin
|
870 |
|
|
if(wb_rst_i)
|
871 |
|
|
WBInProgress<=#Tp 1'b0;
|
872 |
|
|
else
|
873 |
|
|
if(wb_Access_wbClk & ~wb_Access_wbClk_q)
|
874 |
|
|
WBInProgress<=#Tp 1'b1;
|
875 |
|
|
else
|
876 |
|
|
if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
|
877 |
|
|
WBInProgress<=#Tp 1'b0;
|
878 |
|
|
end
|
879 |
|
|
|
880 |
|
|
|
881 |
|
|
// Synchronizing WBInProgress
|
882 |
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
883 |
|
|
begin
|
884 |
|
|
if(wb_rst_i)
|
885 |
|
|
WBAccessCounter<=#Tp 8'h0;
|
886 |
|
|
else
|
887 |
|
|
if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
|
888 |
|
|
WBAccessCounter<=#Tp 8'h0;
|
889 |
|
|
else
|
890 |
|
|
if(wb_cyc_o)
|
891 |
|
|
WBAccessCounter<=#Tp WBAccessCounter + 1'b1;
|
892 |
|
|
end
|
893 |
|
|
|
894 |
|
|
assign WBAccessCounterExceed = WBAccessCounter==8'hff;
|
895 |
|
|
|
896 |
|
|
|
897 |
|
|
// Synchronizing WBInProgress
|
898 |
|
|
always @ (posedge tck)
|
899 |
|
|
begin
|
900 |
|
|
WBInProgress_sync1<=#Tp WBInProgress;
|
901 |
|
|
WBInProgress_tck<=#Tp WBInProgress_sync1;
|
902 |
|
|
end
|
903 |
|
|
|
904 |
|
|
|
905 |
73 |
mohor |
// Whan enabled, TRACE stalls CPU while saving data to the trace buffer.
|
906 |
5 |
mohor |
`ifdef TRACE_ENABLED
|
907 |
73 |
mohor |
assign cpu_stall_o = CpuStall_access | CpuStall_reg | CpuStall_trace ;
|
908 |
5 |
mohor |
`else
|
909 |
73 |
mohor |
assign cpu_stall_o = CpuStall_access | CpuStall_reg;
|
910 |
5 |
mohor |
`endif
|
911 |
|
|
|
912 |
73 |
mohor |
assign reset_o = CpuReset_reg;
|
913 |
5 |
mohor |
|
914 |
|
|
|
915 |
12 |
mohor |
`ifdef TRACE_ENABLED
|
916 |
73 |
mohor |
always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
|
917 |
|
|
CpuStall_write_access_2 or CpuStall_write_access_2 or
|
918 |
|
|
CpuStall_read_access_0 or CpuStall_read_access_1 or
|
919 |
|
|
CpuStall_read_access_2 or CpuStall_read_access_3 or opselect_trace)
|
920 |
12 |
mohor |
`else
|
921 |
73 |
mohor |
always @ (CpuStall_write_access_0 or CpuStall_write_access_1 or
|
922 |
|
|
CpuStall_write_access_2 or CpuStall_write_access_3 or
|
923 |
|
|
CpuStall_read_access_0 or CpuStall_read_access_1 or
|
924 |
|
|
CpuStall_read_access_2 or CpuStall_read_access_3)
|
925 |
12 |
mohor |
`endif
|
926 |
11 |
mohor |
begin
|
927 |
73 |
mohor |
if(CpuStall_write_access_0)
|
928 |
63 |
simons |
opselect_o = `DEBUG_WRITE_0;
|
929 |
11 |
mohor |
else
|
930 |
73 |
mohor |
if(CpuStall_read_access_0)
|
931 |
63 |
simons |
opselect_o = `DEBUG_READ_0;
|
932 |
11 |
mohor |
else
|
933 |
73 |
mohor |
if(CpuStall_write_access_1)
|
934 |
63 |
simons |
opselect_o = `DEBUG_WRITE_1;
|
935 |
|
|
else
|
936 |
73 |
mohor |
if(CpuStall_read_access_1)
|
937 |
63 |
simons |
opselect_o = `DEBUG_READ_1;
|
938 |
|
|
else
|
939 |
73 |
mohor |
if(CpuStall_write_access_2)
|
940 |
63 |
simons |
opselect_o = `DEBUG_WRITE_2;
|
941 |
|
|
else
|
942 |
73 |
mohor |
if(CpuStall_read_access_2)
|
943 |
63 |
simons |
opselect_o = `DEBUG_READ_2;
|
944 |
|
|
else
|
945 |
73 |
mohor |
if(CpuStall_write_access_3)
|
946 |
63 |
simons |
opselect_o = `DEBUG_WRITE_3;
|
947 |
|
|
else
|
948 |
73 |
mohor |
if(CpuStall_read_access_3)
|
949 |
63 |
simons |
opselect_o = `DEBUG_READ_3;
|
950 |
|
|
else
|
951 |
12 |
mohor |
`ifdef TRACE_ENABLED
|
952 |
11 |
mohor |
opselect_o = opselect_trace;
|
953 |
12 |
mohor |
`else
|
954 |
|
|
opselect_o = 3'h0;
|
955 |
|
|
`endif
|
956 |
11 |
mohor |
end
|
957 |
9 |
mohor |
|
958 |
11 |
mohor |
|
959 |
73 |
mohor |
// Latching data read from CPU or registers
|
960 |
|
|
always @ (posedge cpu_clk_i or posedge wb_rst_i)
|
961 |
2 |
mohor |
begin
|
962 |
18 |
mohor |
if(wb_rst_i)
|
963 |
30 |
mohor |
DataReadLatch[31:0]<=#Tp 0;
|
964 |
2 |
mohor |
else
|
965 |
73 |
mohor |
if(CPUAccess_q & ~CPUAccess_q2)
|
966 |
|
|
DataReadLatch[31:0]<=#Tp cpu_data_i[31:0];
|
967 |
30 |
mohor |
else
|
968 |
|
|
if(RegAccess_q & ~RegAccess_q2)
|
969 |
|
|
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
970 |
2 |
mohor |
end
|
971 |
|
|
|
972 |
73 |
mohor |
assign cpu_addr_o = ADDR;
|
973 |
|
|
assign cpu_data_o = DataOut;
|
974 |
2 |
mohor |
|
975 |
|
|
|
976 |
|
|
|
977 |
|
|
/**********************************************************************************
|
978 |
|
|
* *
|
979 |
|
|
* Read Trace buffer logic *
|
980 |
|
|
* *
|
981 |
|
|
**********************************************************************************/
|
982 |
|
|
`ifdef TRACE_ENABLED
|
983 |
|
|
|
984 |
9 |
mohor |
|
985 |
73 |
mohor |
// Synchronizing the trace read buffer signal to cpu_clk_i clock
|
986 |
|
|
dbg_sync_clk1_clk2 syn4 (.clk1(cpu_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
987 |
9 |
mohor |
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
988 |
|
|
);
|
989 |
|
|
|
990 |
|
|
|
991 |
|
|
|
992 |
73 |
mohor |
always @(posedge cpu_clk_i or posedge wb_rst_i)
|
993 |
2 |
mohor |
begin
|
994 |
18 |
mohor |
if(wb_rst_i)
|
995 |
9 |
mohor |
ReadTraceBuffer_q <=#Tp 0;
|
996 |
2 |
mohor |
else
|
997 |
9 |
mohor |
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
998 |
2 |
mohor |
end
|
999 |
9 |
mohor |
|
1000 |
|
|
assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
|
1001 |
|
|
|
1002 |
2 |
mohor |
`endif
|
1003 |
|
|
|
1004 |
|
|
/**********************************************************************************
|
1005 |
|
|
* *
|
1006 |
|
|
* End: Read Trace buffer logic *
|
1007 |
|
|
* *
|
1008 |
|
|
**********************************************************************************/
|
1009 |
|
|
|
1010 |
|
|
|
1011 |
|
|
|
1012 |
|
|
|
1013 |
|
|
|
1014 |
|
|
/**********************************************************************************
|
1015 |
|
|
* *
|
1016 |
|
|
* Bit counter *
|
1017 |
|
|
* *
|
1018 |
|
|
**********************************************************************************/
|
1019 |
|
|
|
1020 |
|
|
|
1021 |
36 |
mohor |
always @ (posedge tck or posedge trst)
|
1022 |
2 |
mohor |
begin
|
1023 |
18 |
mohor |
if(trst)
|
1024 |
2 |
mohor |
BitCounter[7:0]<=#Tp 0;
|
1025 |
|
|
else
|
1026 |
|
|
if(ShiftDR)
|
1027 |
|
|
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
|
1028 |
|
|
else
|
1029 |
|
|
if(UpdateDR)
|
1030 |
|
|
BitCounter[7:0]<=#Tp 0;
|
1031 |
|
|
end
|
1032 |
|
|
|
1033 |
|
|
|
1034 |
|
|
|
1035 |
|
|
/**********************************************************************************
|
1036 |
|
|
* *
|
1037 |
|
|
* End: Bit counter *
|
1038 |
|
|
* *
|
1039 |
|
|
**********************************************************************************/
|
1040 |
|
|
|
1041 |
|
|
|
1042 |
|
|
|
1043 |
|
|
/**********************************************************************************
|
1044 |
|
|
* *
|
1045 |
|
|
* Connecting Registers *
|
1046 |
|
|
* *
|
1047 |
|
|
**********************************************************************************/
|
1048 |
44 |
mohor |
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
|
1049 |
73 |
mohor |
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(cpu_clk_i),
|
1050 |
44 |
mohor |
.bp(bp_i), .reset(wb_rst_i),
|
1051 |
2 |
mohor |
`ifdef TRACE_ENABLED
|
1052 |
5 |
mohor |
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
1053 |
2 |
mohor |
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
|
1054 |
|
|
.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
|
1055 |
|
|
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
|
1056 |
5 |
mohor |
.QualifOper(QualifOper), .RecordPC(RecordPC),
|
1057 |
|
|
.RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
|
1058 |
|
|
.RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
|
1059 |
|
|
.RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
|
1060 |
|
|
.WpTriggerValid(WpTriggerValid),
|
1061 |
2 |
mohor |
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
|
1062 |
|
|
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
|
1063 |
|
|
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
|
1064 |
|
|
.IQualifValid(IQualifValid),
|
1065 |
|
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
1066 |
5 |
mohor |
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
1067 |
|
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
1068 |
2 |
mohor |
`endif
|
1069 |
73 |
mohor |
.cpu_stall(CpuStall_reg), .cpu_stall_all(cpu_stall_all_o), .cpu_sel(cpu_sel_o),
|
1070 |
|
|
.cpu_reset(CpuReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
|
1071 |
5 |
mohor |
|
1072 |
2 |
mohor |
);
|
1073 |
|
|
|
1074 |
|
|
/**********************************************************************************
|
1075 |
|
|
* *
|
1076 |
|
|
* End: Connecting Registers *
|
1077 |
|
|
* *
|
1078 |
|
|
**********************************************************************************/
|
1079 |
|
|
|
1080 |
|
|
|
1081 |
|
|
/**********************************************************************************
|
1082 |
|
|
* *
|
1083 |
|
|
* Connecting CRC module *
|
1084 |
|
|
* *
|
1085 |
|
|
**********************************************************************************/
|
1086 |
18 |
mohor |
wire AsyncResetCrc = trst;
|
1087 |
9 |
mohor |
wire SyncResetCrc = UpdateDR_q;
|
1088 |
2 |
mohor |
|
1089 |
30 |
mohor |
assign BitCounter_Lt4 = BitCounter<4;
|
1090 |
|
|
assign BitCounter_Eq5 = BitCounter==5;
|
1091 |
|
|
assign BitCounter_Eq32 = BitCounter==32;
|
1092 |
|
|
assign BitCounter_Lt38 = BitCounter<38;
|
1093 |
|
|
assign BitCounter_Lt65 = BitCounter<65;
|
1094 |
|
|
|
1095 |
|
|
`ifdef TRACE_ENABLED
|
1096 |
|
|
assign BitCounter_Lt40 = BitCounter<40;
|
1097 |
|
|
`endif
|
1098 |
|
|
|
1099 |
|
|
|
1100 |
73 |
mohor |
// wire EnableCrcIn = ShiftDR &
|
1101 |
|
|
// ( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
1102 |
|
|
// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
1103 |
|
|
// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
|
1104 |
|
|
// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
|
1105 |
|
|
// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
|
1106 |
|
|
// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
|
1107 |
|
|
// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
1108 |
|
|
// );
|
1109 |
|
|
|
1110 |
|
|
wire EnableCrc = ShiftDR &
|
1111 |
63 |
simons |
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
|
1112 |
|
|
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
1113 |
73 |
mohor |
((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
|
1114 |
|
|
((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
|
1115 |
|
|
((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
|
1116 |
|
|
((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
|
1117 |
63 |
simons |
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
1118 |
2 |
mohor |
`ifdef TRACE_ENABLED
|
1119 |
73 |
mohor |
|
|
1120 |
30 |
mohor |
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
1121 |
2 |
mohor |
`endif
|
1122 |
73 |
mohor |
);
|
1123 |
2 |
mohor |
|
1124 |
73 |
mohor |
// wire EnableCrcOut= ShiftDR &
|
1125 |
|
|
// (
|
1126 |
|
|
// ((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
|
1127 |
|
|
// ((DEBUGSelected & CpuDebugScanChain0) & BitCounter_Lt65)|
|
1128 |
|
|
// ((DEBUGSelected & CpuDebugScanChain1) & BitCounter_Lt65)|
|
1129 |
|
|
// ((DEBUGSelected & CpuDebugScanChain2) & BitCounter_Lt65)|
|
1130 |
|
|
// ((DEBUGSelected & CpuDebugScanChain3) & BitCounter_Lt65)|
|
1131 |
|
|
// ((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
1132 |
|
|
// `ifdef TRACE_ENABLED
|
1133 |
|
|
// |
|
1134 |
|
|
// ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
1135 |
|
|
// `endif
|
1136 |
|
|
// );
|
1137 |
|
|
|
1138 |
2 |
mohor |
// Calculating crc for input data
|
1139 |
73 |
mohor |
//dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
1140 |
|
|
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
1141 |
44 |
mohor |
.crc_out(CalculatedCrcIn), .clk(tck));
|
1142 |
2 |
mohor |
|
1143 |
|
|
// Calculating crc for output data
|
1144 |
73 |
mohor |
//dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
1145 |
|
|
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrc), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
|
1146 |
44 |
mohor |
.crc_out(CalculatedCrcOut), .clk(tck));
|
1147 |
2 |
mohor |
|
1148 |
|
|
|
1149 |
73 |
mohor |
reg [3:0] crc_cnt;
|
1150 |
36 |
mohor |
always @ (posedge tck or posedge trst)
|
1151 |
2 |
mohor |
begin
|
1152 |
73 |
mohor |
if (trst)
|
1153 |
|
|
crc_cnt <= 0;
|
1154 |
|
|
else if (Exit1DR)
|
1155 |
|
|
crc_cnt <=#Tp 0;
|
1156 |
|
|
// else if ((~EnableCrcIn) & ShiftDR)
|
1157 |
|
|
else if ((~EnableCrc) & ShiftDR)
|
1158 |
|
|
crc_cnt <=#Tp crc_cnt + 1'b1;
|
1159 |
|
|
end
|
1160 |
|
|
|
1161 |
|
|
|
1162 |
|
|
// Generating CrcMatch signal.
|
1163 |
|
|
always @ (posedge tck or posedge trst)
|
1164 |
|
|
begin
|
1165 |
18 |
mohor |
if(trst)
|
1166 |
73 |
mohor |
CrcMatch <=#Tp 1'b1;
|
1167 |
|
|
else if (SelectDRScan)
|
1168 |
|
|
CrcMatch <=#Tp 1'b1;
|
1169 |
|
|
// else if ((~EnableCrcIn) & ShiftDR)
|
1170 |
|
|
else if ((~EnableCrc) & ShiftDR)
|
1171 |
2 |
mohor |
begin
|
1172 |
73 |
mohor |
if (tdi != CalculatedCrcIn[crc_cnt])
|
1173 |
|
|
CrcMatch <=#Tp 1'b0;
|
1174 |
2 |
mohor |
end
|
1175 |
|
|
end
|
1176 |
|
|
|
1177 |
|
|
|
1178 |
73 |
mohor |
// Generating CrcMatch_q signal.
|
1179 |
|
|
always @ (posedge tck or posedge trst)
|
1180 |
|
|
begin
|
1181 |
|
|
CrcMatch_q <=#Tp CrcMatch;
|
1182 |
|
|
end
|
1183 |
|
|
|
1184 |
|
|
|
1185 |
2 |
mohor |
// Active chain
|
1186 |
73 |
mohor |
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
1187 |
|
|
assign CpuDebugScanChain0 = Chain == `CPU_DEBUG_CHAIN_0;
|
1188 |
|
|
assign CpuDebugScanChain1 = Chain == `CPU_DEBUG_CHAIN_1;
|
1189 |
|
|
assign CpuDebugScanChain2 = Chain == `CPU_DEBUG_CHAIN_2;
|
1190 |
|
|
assign CpuDebugScanChain3 = Chain == `CPU_DEBUG_CHAIN_3;
|
1191 |
|
|
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
|
1192 |
2 |
mohor |
|
1193 |
|
|
`ifdef TRACE_ENABLED
|
1194 |
|
|
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
|
1195 |
|
|
`endif
|
1196 |
|
|
|
1197 |
|
|
/**********************************************************************************
|
1198 |
|
|
* *
|
1199 |
|
|
* End: Connecting CRC module *
|
1200 |
|
|
* *
|
1201 |
|
|
**********************************************************************************/
|
1202 |
|
|
|
1203 |
|
|
/**********************************************************************************
|
1204 |
|
|
* *
|
1205 |
|
|
* Connecting trace module *
|
1206 |
|
|
* *
|
1207 |
|
|
**********************************************************************************/
|
1208 |
|
|
`ifdef TRACE_ENABLED
|
1209 |
73 |
mohor |
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(cpu_data_i), .OpSelect(opselect_trace),
|
1210 |
|
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .CpuStall_O(CpuStall_trace),
|
1211 |
|
|
.Mclk(cpu_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
|
1212 |
8 |
mohor |
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
1213 |
5 |
mohor |
.WpTrigger(WpTrigger),
|
1214 |
2 |
mohor |
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
1215 |
|
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
1216 |
|
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
1217 |
5 |
mohor |
.RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
|
1218 |
|
|
.RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
|
1219 |
|
|
.RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
|
1220 |
|
|
.RecordINSTR(RecordINSTR),
|
1221 |
2 |
mohor |
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
|
1222 |
|
|
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
|
1223 |
|
|
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
|
1224 |
|
|
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
|
1225 |
9 |
mohor |
.ReadBuffer(ReadTraceBufferPulse),
|
1226 |
2 |
mohor |
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
1227 |
|
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
1228 |
|
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
|
1229 |
|
|
);
|
1230 |
|
|
`endif
|
1231 |
|
|
/**********************************************************************************
|
1232 |
|
|
* *
|
1233 |
|
|
* End: Connecting trace module *
|
1234 |
|
|
* *
|
1235 |
|
|
**********************************************************************************/
|
1236 |
|
|
|
1237 |
|
|
|
1238 |
|
|
|
1239 |
9 |
mohor |
endmodule
|