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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2004/01/06 17:15:19  mohor
// temp3 version.
//
// Revision 1.4  2004/01/05 12:16:00  mohor
// tmp2 version.
//
// Revision 1.3  2003/12/23 16:22:46  mohor
// Tmp version.
//
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg    [31:0] wb_dat_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg    [50:0] dr;
wire          enable;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
reg     [5:0] addr_len_cnt;
reg     [5:0] addr_len_cnt_limit;
wire          addr_len_cnt_end;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
reg    [18:0] data_cnt;
reg    [18:0] data_cnt_limit;
wire          data_cnt_end;
reg           status_reset_en;
 
 
reg [`STATUS_CNT -1:0]      status_cnt;
// reg [31:0] data_tck;
 
 
reg [2:0]  cmd, cmd_old;
reg [31:0] adr;
reg [15:0] len;
reg start_rd_tck;
reg start_rd_sync1;
reg start_wb_rd;
reg start_wb_rd_q;
reg start_wr_tck;
reg start_wr_sync1;
reg start_wb_wr;
reg start_wb_wr_q;
 
reg cmd_write;
reg cmd_read;
reg cmd_go;
 
wire status_cnt_end;
 
wire byte, half, long;
reg  byte_q, half_q, long_q;
//wire previous_cmd_read;
wire previous_cmd_write;
 
assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);   // igor !!! Add something so CRC is calculated when data is read from WB
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
always @ (posedge tck_i)
begin
  if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
    dr <= #1 {dr[49:0], tdi_i};
end
 
 
//always @ (posedge tck_i)
//begin
//  if (enable & (data_cnt_end))  // Igor !!! perhaps not needed data_cnt_end
//    data_tck <= #1 {data_tck[30:0], tdi_i};
//end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (enable & (~cmd_cnt_end))
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    addr_len_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_len_cnt <= #1 'h0;
  else if (enable & cmd_cnt_end & (~addr_len_cnt_end))
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
//  else if (enable & cmd_cnt_end & (~data_cnt_end))  // igor !!! add something that will count output data
  else if (enable & (~data_cnt_end) & cmd_go & ((cmd_cnt_end & previous_cmd_write | crc_cnt_end & cmd_read)))
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
 
assign byte = data_cnt[2:0] == 3'h0;
assign half = data_cnt[3:0] == 4'h0;
assign long = data_cnt[4:0] == 5'h0;
 
 
always @ (posedge tck_i)
begin
  byte_q <= #1 byte;
  half_q <= #1 half;
  long_q <= #1 long;
end
 
 
 
//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
 
wire dr_read;
wire dr_write;
wire dr_go;
wire dr_status;
 
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
assign dr_go = dr[2:0] == `WB_GO;
assign dr_status = dr[2:0] == `WB_STATUS;
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cmd_read  <= #1 1'b0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_read <= #1 dr_read;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cmd_write  <= #1 1'b0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_write <= #1 dr_write;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cmd_go  <= #1 1'b0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_go <= #1 dr_go;
end
 
 
 
 
 
always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
begin
  if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      // (current command is WB_STATUS or WB_GO)
      if (dr_status | dr_go)
        addr_len_cnt_limit = 6'd0;
      // (current command is WB_WRITEx or WB_READx)
      else
        addr_len_cnt_limit = 6'd48;
    end
end
 
 
 
always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
begin
  if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      // (current command is WB_GO and previous command is WB_WRITEx)
      if (dr_go & previous_cmd_write)
        data_cnt_limit = (len<<3);
      else
        data_cnt_limit = 19'h0;
    end
end
 
 
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
//  else if(enable & addr_len_cnt_end & (~crc_cnt_end))
  else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q <= #1 crc_cnt_end;
  cmd_cnt_end_q <= #1 cmd_cnt_end;
end
 
// status counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt <= #1 'h0;
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
    status_cnt <= #1 'h0;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
reg [`STATUS_LEN -1:0] status;
//reg address_unaligned;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
 
reg busy_wb;
reg busy_tck;
reg wb_end;
reg wb_end_rst;
reg wb_end_rst_sync;
reg wb_end_sync;
reg wb_end_tck;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status <= #1 'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if overrun occured during write (data couldn't be written fast enough)
// 4. bit:          1 if WB error occured, else 0
 
 
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
    end
  else if (crc_cnt_end & (~crc_cnt_end_q))
    begin
      tdo_o = crc_match_i;
      TDO_WISHBONE = "crc_match_i";
    end
  else if (crc_cnt_end)
    begin
      tdo_o = status[0];
      TDO_WISHBONE = "status";
    end
  else
    begin
      tdo_o = 1'b0;
      TDO_WISHBONE = "zero while CRC is shifted in";
    end
end
 
 
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (cmd_write | cmd_read)
        begin
          cmd <= #1 dr[50:48];
          adr <= #1 dr[47:16];
          len <= #1 dr[15:0];
          set_addr <= #1 1'b1;
        end
      else
        begin
          cmd <= #1 dr[2:0];
        end
 
      cmd_old <= #1 cmd;
    end
  else
    set_addr <= #1 1'b0;
end
 
 
// Start wishbone read cycle
always @ (posedge tck_i)
begin
  if (set_addr & cmd_read)
    start_rd_tck <= #1 1'b1;
  else
    start_rd_tck <= #1 1'b0;
end
 
 
 
// Start wishbone write cycle
always @ (posedge tck_i)
begin
  if (cmd_go & previous_cmd_write)
    begin
      case (cmd)  // synthesis parallel_case full_case
        `WB_WRITE8  : begin
                        if (byte & (~byte_q))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE16 : begin
                        if (half & (~half_q))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE32 : begin
                        if (long & (~long_q))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 dr[31:0];
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
      endcase
    end
  else
    start_wr_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_rd_sync1  <= #1 start_rd_tck;
  start_wb_rd     <= #1 start_rd_sync1;
  start_wb_rd_q   <= #1 start_wb_rd;
 
  start_wr_sync1  <= #1 start_wr_tck;
  start_wb_wr     <= #1 start_wr_sync1;
  start_wb_wr_q   <= #1 start_wb_wr;
 
  set_addr_sync   <= #1 set_addr;
  set_addr_wb     <= #1 set_addr_sync;
  set_addr_wb_q   <= #1 set_addr_wb;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_cyc_o <= #1 1'b0;
  else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
  if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((cmd == `WB_WRITE8) | (cmd_old == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((cmd == `WB_WRITE16) | (cmd_old == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
`define WB_STATUS     3'h0  // igor !!! Delete this lines 
`define WB_WRITE8     3'h1  // igor !!! Delete this lines
`define WB_WRITE16    3'h2  // igor !!! Delete this lines
`define WB_WRITE32    3'h3  // igor !!! Delete this lines
`define WB_GO         3'h4  // igor !!! Delete this lines
`define WB_READ8      3'h5  // igor !!! Delete this lines
`define WB_READ16     3'h6  // igor !!! Delete this lines
`define WB_READ32     3'h7  // igor !!! Delete this lines
 
 
 
 
 
 
 
//    adr   byte  |  short  |  long
//     0    1000     1100      1111
//     1    0100     err       err
//     2    0010     0011      err
//     3    0001     err       err
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    begin
      wb_sel_o[3:0] <= #1 4'h0;
    end
  else
    begin
      wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                        (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
      wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
    end
end
 
 
 
 
/*
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_dat_o[31:0] <= #1 32'h0;
  else if (start_wb_wr & (~start_wb_wr_q))
    begin
      if (cmd[1:0] == 2'd1)                       // 8-bit access
        wb_dat_o[31:0] <= #1 {4{8'h0}};
      else if (cmd[1:0] == 2'd2)                  // 16-bit access
        wb_dat_o[31:0] <= #1 {2{16'h0}};
      else
        wb_dat_o[31:0] <= #1 32'h0;               //32-bit access
    end
end
*/
 
//always @ (wb_adr_o or cmd)
//begin
//  wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) | 
//                (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
//  wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
//  wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
//  wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
//end
 
 
 
// always @ (dr)
// begin
//   address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
// end
 
 
 
assign wb_we_o = ~cmd[2];   // Status or write (for simpler logic status is allowed)
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
reg [31:0] input_data;
 
always @ (posedge wb_clk_i)
begin
  if(wb_ack_i)
    input_data <= #1 wb_dat_i;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
    end
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_overrun <= #1 1'b0;
  else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
    wb_overrun <= #1 1'b1;
  else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
    wb_overrun <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_overrun_sync <= #1 wb_overrun;
  wb_overrun_tck  <= #1 wb_overrun_sync;
end
 
 
 
 
 
 
// wb_error is locked until WB_STATUS is performed
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_reset_en <= 1'b0;
  else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
    status_reset_en <= #1 1'b1;
  else
    status_reset_en <= #1 1'b0;
end
 
 
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	89	mohor	`// Revision 1.5 2004/01/06 17:15:19 mohor`
47			`// temp3 version.`
48			`//`
49	88	mohor	`// Revision 1.4 2004/01/05 12:16:00 mohor`
50			`// tmp2 version.`
51			`//`
52	87	mohor	`// Revision 1.3 2003/12/23 16:22:46 mohor`
53			`// Tmp version.`
54			`//`
55	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
56			`// Small fix.`
57			`//`
58	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
59			`// New directory structure. New version of the debug interface.`
60	82	mohor	`//`
61			`//`
62	83	mohor	`//`
63	82	mohor
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "dbg_wb_defines.v"
68
69			`// Top module`
70			`module dbg_wb(`
71			`// JTAG signals`
72			`trst_i, // trst_i is active high (inverted on higher layers)`
73			`tck_i,`
74			`tdi_i,`
75			`tdo_o,`
76
77			`// TAP states`
78			`shift_dr_i,`
79			`pause_dr_i,`
80			`update_dr_i,`
81
82			`wishbone_ce_i,`
83			`crc_match_i,`
84			`crc_en_o,`
85			`shift_crc_o,`
86
87			`// WISHBONE common signals`
88			`wb_rst_i, wb_clk_i,`
89
90			`// WISHBONE master interface`
91			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
92			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
93
94			`);`
95
96			`// JTAG signals`
97			`input trst_i;`
98			`input tck_i;`
99			`input tdi_i;`
100			`output tdo_o;`
101
102			`// TAP states`
103			`input shift_dr_i;`
104			`input pause_dr_i;`
105			`input update_dr_i;`
106
107			`input wishbone_ce_i;`
108			`input crc_match_i;`
109			`output crc_en_o;`
110			`output shift_crc_o;`
111
112			`// WISHBONE common signals`
113			`input wb_rst_i; // WISHBONE reset`
114			`input wb_clk_i; // WISHBONE clock`
115
116			`// WISHBONE master interface`
117			`output [31:0] wb_adr_o;`
118			`output [31:0] wb_dat_o;`
119			`input [31:0] wb_dat_i;`
120			`output wb_cyc_o;`
121			`output wb_stb_o;`
122			`output [3:0] wb_sel_o;`
123			`output wb_we_o;`
124			`input wb_ack_i;`
125			`output wb_cab_o;`
126			`input wb_err_i;`
127			`output [2:0] wb_cti_o;`
128			`output [1:0] wb_bte_o;`
129
130			`reg wb_cyc_o;`
131			`reg [31:0] wb_adr_o;`
132	88	mohor	`reg [31:0] wb_dat_o;`
133	82	mohor	`reg [3:0] wb_sel_o;`
134
135			`reg tdo_o;`
136
137	88	mohor	`reg [50:0] dr;`
138			`wire enable;`
139			`reg [1:0] cmd_cnt;`
140			`wire cmd_cnt_end;`
141			`reg cmd_cnt_end_q;`
142			`reg [5:0] addr_len_cnt;`
143			`reg [5:0] addr_len_cnt_limit;`
144			`wire addr_len_cnt_end;`
145			`reg [5:0] crc_cnt;`
146			`wire crc_cnt_end;`
147			`reg crc_cnt_end_q;`
148			`reg [18:0] data_cnt;`
149			`reg [18:0] data_cnt_limit;`
150			`wire data_cnt_end;`
151			`reg status_reset_en;`
152	82	mohor
153
154			reg [`STATUS_CNT -1:0] status_cnt;
155	88	mohor	`// reg [31:0] data_tck;`
156
157
158			`reg [2:0] cmd, cmd_old;`
159			`reg [31:0] adr;`
160			`reg [15:0] len;`
161	89	mohor	`reg start_rd_tck;`
162			`reg start_rd_sync1;`
163			`reg start_wb_rd;`
164			`reg start_wb_rd_q;`
165			`reg start_wr_tck;`
166			`reg start_wr_sync1;`
167			`reg start_wb_wr;`
168			`reg start_wb_wr_q;`
169	88	mohor
170	89	mohor	`reg cmd_write;`
171			`reg cmd_read;`
172			`reg cmd_go;`
173	88	mohor
174	82	mohor	`wire status_cnt_end;`
175
176	89	mohor	`wire byte, half, long;`
177			`reg byte_q, half_q, long_q;`
178			`//wire previous_cmd_read;`
179			`wire previous_cmd_write;`
180
181	82	mohor	`assign enable = wishbone_ce_i & shift_dr_i;`
182	89	mohor	`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); // igor !!! Add something so CRC is calculated when data is read from WB`
183			`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
184	82	mohor
185
186			`always @ (posedge tck_i)`
187			`begin`
188	88	mohor	`if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end) \| (~data_cnt_end)))`
189			`dr <= #1 {dr[49:0], tdi_i};`
190	82	mohor	`end`
191
192
193	88	mohor	`//always @ (posedge tck_i)`
194			`//begin`
195			`// if (enable & (data_cnt_end)) // Igor !!! perhaps not needed data_cnt_end`
196			`// data_tck <= #1 {data_tck[30:0], tdi_i};`
197			`//end`
198
199
200	82	mohor	`always @ (posedge tck_i or posedge trst_i)`
201			`begin`
202			`if (trst_i)`
203	87	mohor	`cmd_cnt <= #1 'h0;`
204	82	mohor	`else if (update_dr_i)`
205	87	mohor	`cmd_cnt <= #1 'h0;`
206			`else if (enable & (~cmd_cnt_end))`
207			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
208	82	mohor	`end`
209
210
211	87	mohor	`always @ (posedge tck_i or posedge trst_i)`
212			`begin`
213			`if (trst_i)`
214	88	mohor	`addr_len_cnt <= #1 'h0;`
215			`else if (update_dr_i)`
216			`addr_len_cnt <= #1 'h0;`
217			`else if (enable & cmd_cnt_end & (~addr_len_cnt_end))`
218			`addr_len_cnt <= #1 addr_len_cnt + 1'b1;`
219			`end`
220
221
222			`always @ (posedge tck_i or posedge trst_i)`
223			`begin`
224			`if (trst_i)`
225	87	mohor	`data_cnt <= #1 'h0;`
226			`else if (update_dr_i)`
227			`data_cnt <= #1 'h0;`
228	89	mohor	`// else if (enable & cmd_cnt_end & (~data_cnt_end)) // igor !!! add something that will count output data`
229			`else if (enable & (~data_cnt_end) & cmd_go & ((cmd_cnt_end & previous_cmd_write \| crc_cnt_end & cmd_read)))`
230	87	mohor	`data_cnt <= #1 data_cnt + 1'b1;`
231			`end`
232	82	mohor
233	87	mohor
234	88	mohor
235			`assign byte = data_cnt[2:0] == 3'h0;`
236			`assign half = data_cnt[3:0] == 4'h0;`
237			`assign long = data_cnt[4:0] == 5'h0;`
238
239
240			`always @ (posedge tck_i)`
241			`begin`
242			`byte_q <= #1 byte;`
243			`half_q <= #1 half;`
244			`long_q <= #1 long;`
245			`end`
246
247
248
249			//assign previous_cmd_read = (cmd == `WB_READ8) \| (cmd == `WB_READ16) \| (cmd == `WB_READ32);
250			assign previous_cmd_write = (cmd == `WB_WRITE8) \| (cmd == `WB_WRITE16) \| (cmd == `WB_WRITE32);
251
252	89	mohor	`wire dr_read;`
253			`wire dr_write;`
254			`wire dr_go;`
255			`wire dr_status;`
256	88	mohor
257	89	mohor	assign dr_read = (dr[2:0] == `WB_READ8) \| (dr[2:0] == `WB_READ16) \| (dr[2:0] == `WB_READ32);
258			assign dr_write = (dr[2:0] == `WB_WRITE8) \| (dr[2:0] == `WB_WRITE16) \| (dr[2:0] == `WB_WRITE32);
259			assign dr_go = dr[2:0] == `WB_GO;
260			assign dr_status = dr[2:0] == `WB_STATUS;
261	88	mohor
262
263			`always @ (posedge tck_i)`
264			`begin`
265			`if (update_dr_i)`
266			`cmd_read <= #1 1'b0;`
267			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
268	89	mohor	`cmd_read <= #1 dr_read;`
269	88	mohor	`end`
270
271
272			`always @ (posedge tck_i)`
273			`begin`
274			`if (update_dr_i)`
275			`cmd_write <= #1 1'b0;`
276			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
277	89	mohor	`cmd_write <= #1 dr_write;`
278	88	mohor	`end`
279
280
281			`always @ (posedge tck_i)`
282			`begin`
283			`if (update_dr_i)`
284			`cmd_go <= #1 1'b0;`
285			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
286	89	mohor	`cmd_go <= #1 dr_go;`
287	88	mohor	`end`
288
289
290
291
292
293			`always @ (cmd_cnt_end or cmd_cnt_end_q or dr)`
294			`begin`
295			`if (cmd_cnt_end & (~cmd_cnt_end_q))`
296			`begin`
297			`// (current command is WB_STATUS or WB_GO)`
298	89	mohor	`if (dr_status \| dr_go)`
299	88	mohor	`addr_len_cnt_limit = 6'd0;`
300			`// (current command is WB_WRITEx or WB_READx)`
301			`else`
302			`addr_len_cnt_limit = 6'd48;`
303			`end`
304			`end`
305
306
307
308			`always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)`
309			`begin`
310			`if (cmd_cnt_end & (~cmd_cnt_end_q))`
311			`begin`
312			`// (current command is WB_GO and previous command is WB_WRITEx)`
313	89	mohor	`if (dr_go & previous_cmd_write)`
314	88	mohor	`data_cnt_limit = (len<<3);`
315			`else`
316			`data_cnt_limit = 19'h0;`
317			`end`
318			`end`
319
320
321
322	82	mohor	`// crc counter`
323			`always @ (posedge tck_i or posedge trst_i)`
324			`begin`
325			`if (trst_i)`
326			`crc_cnt <= #1 'h0;`
327	88	mohor	`// else if(enable & addr_len_cnt_end & (~crc_cnt_end))`
328			`else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))`
329	82	mohor	`crc_cnt <= #1 crc_cnt + 1'b1;`
330			`else if (update_dr_i)`
331			`crc_cnt <= #1 'h0;`
332			`end`
333
334	87	mohor	`assign cmd_cnt_end = cmd_cnt == 2'h3;`
335	88	mohor	`//assign addr_len_cnt_end = addr_len_cnt == 6'd48;`
336			`assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;`
337	87	mohor	`assign crc_cnt_end = crc_cnt == 6'd32;`
338	89	mohor	`assign data_cnt_end = (data_cnt == data_cnt_limit);`
339	82	mohor
340			`always @ (posedge tck_i)`
341			`begin`
342			`crc_cnt_end_q <= #1 crc_cnt_end;`
343	88	mohor	`cmd_cnt_end_q <= #1 cmd_cnt_end;`
344	82	mohor	`end`
345
346			`// status counter`
347			`always @ (posedge tck_i or posedge trst_i)`
348			`begin`
349			`if (trst_i)`
350			`status_cnt <= #1 'h0;`
351			`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
352			`status_cnt <= #1 status_cnt + 1'b1;`
353			`else if (update_dr_i)`
354			`status_cnt <= #1 'h0;`
355			`end`
356
357			assign status_cnt_end = status_cnt == `STATUS_LEN;
358			reg [`STATUS_LEN -1:0] status;
359	88	mohor	`//reg address_unaligned;`
360	82	mohor
361			`reg wb_error, wb_error_sync, wb_error_tck;`
362	88	mohor	`reg wb_overrun, wb_overrun_sync, wb_overrun_tck;`
363	82	mohor
364	86	mohor	`reg busy_wb;`
365			`reg busy_tck;`
366			`reg wb_end;`
367			`reg wb_end_rst;`
368			`reg wb_end_rst_sync;`
369			`reg wb_end_sync;`
370			`reg wb_end_tck;`
371			`reg busy_sync;`
372			`reg [799:0] TDO_WISHBONE;`
373	82	mohor
374			`always @ (posedge tck_i or posedge trst_i)`
375			`begin`
376			`if (trst_i)`
377			`status <= #1 'h0;`
378			`else if(crc_cnt_end & (~crc_cnt_end_q))`
379	88	mohor	`status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,`
380	82	mohor	`else if (shift_dr_i & (~status_cnt_end))`
381			status <= #1 {status[0], status[`STATUS_LEN -1:1]};
382			`end`
383	88	mohor	`// Following status is shifted out:`
384	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
385	86	mohor	`// 2. bit: 1 while WB access is in progress (busy_tck), else 0`
386	88	mohor	`// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)`
387	82	mohor	`// 4. bit: 1 if WB error occured, else 0`
388
389
390	88	mohor
391	82	mohor	`always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)`
392			`begin`
393			`if (pause_dr_i)`
394	87	mohor	`begin`
395	82	mohor	`tdo_o = busy_tck;`
396			`TDO_WISHBONE = "busy_tck";`
397	87	mohor	`end`
398	82	mohor	`else if (crc_cnt_end & (~crc_cnt_end_q))`
399	87	mohor	`begin`
400			`tdo_o = crc_match_i;`
401			`TDO_WISHBONE = "crc_match_i";`
402			`end`
403			`else if (crc_cnt_end)`
404			`begin`
405			`tdo_o = status[0];`
406			`TDO_WISHBONE = "status";`
407			`end`
408	82	mohor	`else`
409	87	mohor	`begin`
410			`tdo_o = 1'b0;`
411			`TDO_WISHBONE = "zero while CRC is shifted in";`
412			`end`
413	82	mohor	`end`
414
415
416	88	mohor	`reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;`
417	82	mohor
418			`always @ (posedge tck_i)`
419			`begin`
420			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
421			`begin`
422	88	mohor	`if (cmd_write \| cmd_read)`
423			`begin`
424			`cmd <= #1 dr[50:48];`
425			`adr <= #1 dr[47:16];`
426			`len <= #1 dr[15:0];`
427			`set_addr <= #1 1'b1;`
428			`end`
429			`else`
430			`begin`
431			`cmd <= #1 dr[2:0];`
432			`end`
433
434	87	mohor	`cmd_old <= #1 cmd;`
435	82	mohor	`end`
436			`else`
437	88	mohor	`set_addr <= #1 1'b0;`
438			`end`
439
440
441	89	mohor	`// Start wishbone read cycle`
442	88	mohor	`always @ (posedge tck_i)`
443			`begin`
444	89	mohor	`if (set_addr & cmd_read)`
445			`start_rd_tck <= #1 1'b1;`
446			`else`
447			`start_rd_tck <= #1 1'b0;`
448			`end`
449
450
451
452			`// Start wishbone write cycle`
453			`always @ (posedge tck_i)`
454			`begin`
455	88	mohor	`if (cmd_go & previous_cmd_write)`
456			`begin`
457			`case (cmd) // synthesis parallel_case full_case`
458			`WB_WRITE8 : begin
459			`if (byte & (~byte_q))`
460			`begin`
461	89	mohor	`start_wr_tck <= #1 1'b1;`
462	88	mohor	`wb_dat_o <= #1 {4{dr[7:0]}};`
463			`end`
464			`else`
465			`begin`
466	89	mohor	`start_wr_tck <= #1 1'b0;`
467	88	mohor	`end`
468			`end`
469			`WB_WRITE16 : begin
470			`if (half & (~half_q))`
471			`begin`
472	89	mohor	`start_wr_tck <= #1 1'b1;`
473	88	mohor	`wb_dat_o <= #1 {2{dr[15:0]}};`
474			`end`
475			`else`
476			`begin`
477	89	mohor	`start_wr_tck <= #1 1'b0;`
478	88	mohor	`end`
479			`end`
480			`WB_WRITE32 : begin
481			`if (long & (~long_q))`
482			`begin`
483	89	mohor	`start_wr_tck <= #1 1'b1;`
484	88	mohor	`wb_dat_o <= #1 dr[31:0];`
485			`end`
486			`else`
487			`begin`
488	89	mohor	`start_wr_tck <= #1 1'b0;`
489	88	mohor	`end`
490			`end`
491			`endcase`
492			`end`
493			`else`
494	89	mohor	`start_wr_tck <= #1 1'b0;`
495	82	mohor	`end`
496
497
498			`always @ (posedge wb_clk_i)`
499			`begin`
500	89	mohor	`start_rd_sync1 <= #1 start_rd_tck;`

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