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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] [dbg_cpu_registers.v] - Blame information for rev 158

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu_registers.v                                         ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2004/01/22 10:16:08  mohor
// cpu_stall_o activated as soon as bp occurs.
//
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:33  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
module dbg_cpu_registers  (
                            data_i,
                            data_o,
                            addr_i,
                            we_i,
                            en_i,
                            clk_i,
                            bp_i,
                            rst_i,
                            cpu_clk_i,
                            cpu_stall_o,
                            cpu_stall_all_o,
                            cpu_sel_o,
                            cpu_rst_o
                          );
 
 
input            [7:0]  data_i;
input            [1:0]  addr_i;
 
input                   we_i;
input                   en_i;
input                   clk_i;
input                   bp_i;
input                   rst_i;
input                   cpu_clk_i;
 
output           [7:0]  data_o;
reg              [7:0]  data_o;
 
output                  cpu_stall_o;
output                  cpu_stall_all_o;
output [`CPU_NUM -1:0]  cpu_sel_o;
output                  cpu_rst_o;
 
wire                    cpu_stall_all;
wire                    cpu_reset;
wire             [2:1]  cpu_op_out;
wire   [`CPU_NUM -1:0]  cpu_sel_out;
 
wire                    cpuop_wr;
wire                    cpusel_wr;
 
reg                     cpusel_wr_sync, cpusel_wr_cpu;
reg                     stall_bp, stall_bp_sync, stall_bp_tck;
reg                     stall_reg, stall_reg_sync, stall_reg_cpu;
reg                     cpu_stall_all_sync;
reg                     cpu_stall_all_o;
reg                     cpu_reset_sync;
reg                     cpu_rst_o;
 
 
 
assign cpuop_wr      = en_i & we_i & (addr_i == `CPU_OP_ADR);
assign cpusel_wr     = en_i & we_i & (addr_i == `CPU_SEL_ADR);
 
 
// Synchronising we for cpu_sel register that works in cpu_clk clock domain
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpusel_wr_sync <= #1 1'b0;
      cpusel_wr_cpu  <= #1 1'b0;
    end
  else
    begin
      cpusel_wr_sync <= #1 cpusel_wr;
      cpusel_wr_cpu  <= #1 cpusel_wr_sync;
    end
end
 
 
// Breakpoint is latched and synchronized. Stall is set and latched.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if(rst_i)
    stall_bp <= #1 1'b0;
  else if(bp_i)
    stall_bp <= #1 1'b1;
  else if(stall_reg_cpu)
    stall_bp <= #1 1'b0;
end
 
 
// Synchronizing
always @ (posedge clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_bp_sync <= #1 1'b0;
      stall_bp_tck  <= #1 1'b0;
    end
  else
    begin
      stall_bp_sync <= #1 stall_bp;
      stall_bp_tck  <= #1 stall_bp_sync;
    end
end
 
 
always @ (posedge clk_i or posedge rst_i)
begin
  if (rst_i)
    stall_reg <= #1 1'b0;
  else if (stall_bp_tck)
    stall_reg <= #1 1'b1;
  else if (cpuop_wr)
    stall_reg <= #1 data_i[0];
end
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_reg_sync <= #1 1'b0;
      stall_reg_cpu  <= #1 1'b0;
    end
  else
    begin
      stall_reg_sync <= #1 stall_reg;
      stall_reg_cpu  <= #1 stall_reg_sync;
    end
end
 
 
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
 
 
 
dbg_register #(2, 0)          CPUOP  (.data_in(data_i[2:1]),           .data_out(cpu_op_out[2:1]), .write(cpuop_wr),       .clk(clk_i),     .reset(rst_i));
dbg_register #(`CPU_NUM, 0)   CPUSEL (.data_in(data_i[`CPU_NUM-1:0]),  .data_out(cpu_sel_out),     .write(cpusel_wr_cpu),  .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
 
 
always @ (posedge clk_i or posedge rst_i)
begin
  if (rst_i)
    data_o <= #1 8'h0;
  else
    begin
      case (addr_i)         // Synthesis parallel_case
        `CPU_OP_ADR  : data_o <= #1 {5'h0, cpu_op_out[2:1], stall_reg};
        `CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
        default      : data_o <= #1 8'h0;
      endcase
    end
end
 
 
assign cpu_stall_all      = cpu_op_out[2];       // this signal is used to stall all the cpus except the one that is selected in cpusel register
assign cpu_sel_o          = cpu_sel_out;
assign cpu_reset          = cpu_op_out[1];
 
 
 
 
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_stall_all_sync  <= #1 1'b0;
      cpu_stall_all_o     <= #1 1'b0;
      cpu_reset_sync      <= #1 1'b0;
      cpu_rst_o           <= #1 1'b0;
    end
  else
    begin
      cpu_stall_all_sync  <= #1 cpu_stall_all;
      cpu_stall_all_o     <= #1 cpu_stall_all_sync;
      cpu_reset_sync      <= #1 cpu_reset;
      cpu_rst_o           <= #1 cpu_reset_sync;
    end
end
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu_registers.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	123	mohor	`// Revision 1.3 2004/01/22 10:16:08 mohor`
47			`// cpu_stall_o activated as soon as bp occurs.`
48			`//`
49	119	mohor	`// Revision 1.2 2004/01/17 17:01:14 mohor`
50			`// Almost finished.`
51			`//`
52	101	mohor	`// Revision 1.1 2004/01/16 14:53:33 mohor`
53			`// * empty log message *`
54	100	mohor	`//`
55			`//`
56	101	mohor	`//`
57	100	mohor
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "dbg_cpu_defines.v"
62
63			`module dbg_cpu_registers (`
64	101	mohor	`data_i,`
65			`data_o,`
66			`addr_i,`
67			`we_i,`
68			`en_i,`
69			`clk_i,`
70			`bp_i,`
71			`rst_i,`
72			`cpu_clk_i,`
73			`cpu_stall_o,`
74			`cpu_stall_all_o,`
75			`cpu_sel_o,`
76			`cpu_rst_o`
77	100	mohor	`);`
78
79
80	101	mohor	`input [7:0] data_i;`
81			`input [1:0] addr_i;`
82	100	mohor
83	101	mohor	`input we_i;`
84			`input en_i;`
85			`input clk_i;`
86			`input bp_i;`
87			`input rst_i;`
88			`input cpu_clk_i;`
89	100	mohor
90	101	mohor	`output [7:0] data_o;`
91			`reg [7:0] data_o;`
92	100	mohor
93	101	mohor	`output cpu_stall_o;`
94			`output cpu_stall_all_o;`
95			output [`CPU_NUM -1:0] cpu_sel_o;
96			`output cpu_rst_o;`
97	100	mohor
98	101	mohor	`wire cpu_stall_all;`
99			`wire cpu_reset;`
100	100	mohor	`wire [2:1] cpu_op_out;`
101			wire [`CPU_NUM -1:0] cpu_sel_out;
102
103			`wire cpuop_wr;`
104			`wire cpusel_wr;`
105
106	119	mohor	`reg cpusel_wr_sync, cpusel_wr_cpu;`
107			`reg stall_bp, stall_bp_sync, stall_bp_tck;`
108			`reg stall_reg, stall_reg_sync, stall_reg_cpu;`
109	101	mohor	`reg cpu_stall_all_sync;`
110			`reg cpu_stall_all_o;`
111			`reg cpu_reset_sync;`
112			`reg cpu_rst_o;`
113	100	mohor
114
115
116	101	mohor	assign cpuop_wr = en_i & we_i & (addr_i == `CPU_OP_ADR);
117			assign cpusel_wr = en_i & we_i & (addr_i == `CPU_SEL_ADR);
118	100	mohor
119
120	101	mohor	`// Synchronising we for cpu_sel register that works in cpu_clk clock domain`
121	119	mohor	`always @ (posedge cpu_clk_i or posedge rst_i)`
122	100	mohor	`begin`
123	119	mohor	`if (rst_i)`
124			`begin`
125			`cpusel_wr_sync <= #1 1'b0;`
126			`cpusel_wr_cpu <= #1 1'b0;`
127			`end`
128			`else`
129			`begin`
130			`cpusel_wr_sync <= #1 cpusel_wr;`
131			`cpusel_wr_cpu <= #1 cpusel_wr_sync;`
132			`end`
133	101	mohor	`end`
134
135
136	119	mohor	`// Breakpoint is latched and synchronized. Stall is set and latched.`
137			`always @ (posedge cpu_clk_i or posedge rst_i)`
138	101	mohor	`begin`
139			`if(rst_i)`
140	119	mohor	`stall_bp <= #1 1'b0;`
141			`else if(bp_i)`
142			`stall_bp <= #1 1'b1;`
143			`else if(stall_reg_cpu)`
144			`stall_bp <= #1 1'b0;`
145	100	mohor	`end`
146
147
148	119	mohor	`// Synchronizing`
149			`always @ (posedge clk_i or posedge rst_i)`
150			`begin`
151			`if (rst_i)`
152			`begin`
153			`stall_bp_sync <= #1 1'b0;`
154			`stall_bp_tck <= #1 1'b0;`
155			`end`
156			`else`
157			`begin`
158			`stall_bp_sync <= #1 stall_bp;`
159			`stall_bp_tck <= #1 stall_bp_sync;`
160			`end`
161			`end`
162
163
164			`always @ (posedge clk_i or posedge rst_i)`
165			`begin`
166			`if (rst_i)`
167			`stall_reg <= #1 1'b0;`
168			`else if (stall_bp_tck)`
169			`stall_reg <= #1 1'b1;`
170			`else if (cpuop_wr)`
171			`stall_reg <= #1 data_i[0];`
172			`end`
173
174
175			`always @ (posedge cpu_clk_i or posedge rst_i)`
176			`begin`
177			`if (rst_i)`
178			`begin`
179			`stall_reg_sync <= #1 1'b0;`
180			`stall_reg_cpu <= #1 1'b0;`
181			`end`
182			`else`
183			`begin`
184			`stall_reg_sync <= #1 stall_reg;`
185			`stall_reg_cpu <= #1 stall_reg_sync;`
186			`end`
187			`end`
188
189
190			`assign cpu_stall_o = bp_i \| stall_bp \| stall_reg_cpu;`
191
192
193
194			`dbg_register #(2, 0) CPUOP (.data_in(data_i[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk_i), .reset(rst_i));`
195	101	mohor	dbg_register #(`CPU_NUM, 0) CPUSEL (.data_in(data_i[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr_cpu), .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
196	100	mohor
197
198	123	mohor	`always @ (posedge clk_i or posedge rst_i)`
199	100	mohor	`begin`
200	123	mohor	`if (rst_i)`
201			`data_o <= #1 8'h0;`
202			`else`
203			`begin`
204			`case (addr_i) // Synthesis parallel_case`
205			`CPU_OP_ADR : data_o <= #1 {5'h0, cpu_op_out[2:1], stall_reg};
206			`CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
207			`default : data_o <= #1 8'h0;`
208			`endcase`
209			`end`
210	100	mohor	`end`
211
212
213			`assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register`
214	101	mohor	`assign cpu_sel_o = cpu_sel_out;`
215	100	mohor	`assign cpu_reset = cpu_op_out[1];`
216
217	101	mohor
218
219
220			`// Synchronizing signals from registers`
221	119	mohor	`always @ (posedge cpu_clk_i or posedge rst_i)`
222	101	mohor	`begin`
223	119	mohor	`if (rst_i)`
224			`begin`
225			`cpu_stall_all_sync <= #1 1'b0;`
226			`cpu_stall_all_o <= #1 1'b0;`
227			`cpu_reset_sync <= #1 1'b0;`
228			`cpu_rst_o <= #1 1'b0;`
229			`end`
230			`else`
231			`begin`
232			`cpu_stall_all_sync <= #1 cpu_stall_all;`
233			`cpu_stall_all_o <= #1 cpu_stall_all_sync;`
234			`cpu_reset_sync <= #1 cpu_reset;`
235			`cpu_rst_o <= #1 cpu_reset_sync;`
236			`end`
237	101	mohor	`end`
238
239
240
241	100	mohor	`endmodule`
242

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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] [dbg_cpu_registers.v] - Blame information for rev 158