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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 83

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg [`WB_DR_LEN -1:0] dr;
wire enable;
reg [5:0] cnt;
reg [5:0] crc_cnt;
wire      cnt_end;
wire      crc_cnt_end;
reg       crc_cnt_end_q;
 
 
reg [`STATUS_CNT -1:0]      status_cnt;
wire status_cnt_end;
 
assign enable = wishbone_ce_i & shift_dr_i;
assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i;  // Signals dbg module to shift out the CRC
 
 
always @ (posedge tck_i)
begin
  if (enable & (~cnt_end))
    dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cnt <= #1 'h0;
  else if (update_dr_i)
    cnt <= #1 'h0;
  else if (enable & (~cnt_end))
    cnt <= #1 cnt + 1'b1;
end
 
assign cnt_end = cnt == `WB_DR_LEN;
 
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
  else if(enable & cnt_end & (~crc_cnt_end))
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign crc_cnt_end = crc_cnt == 6'd32;
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q <= #1 crc_cnt_end;
end
 
// status counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt <= #1 'h0;
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
    status_cnt <= #1 'h0;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
reg [`STATUS_LEN -1:0] status;
reg address_unaligned;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_timeout, wb_timeout_sync, wb_timeout_tck;
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status <= #1 'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    begin
      if (dr[2:0] == `WB_STATUS)
        status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, address_unaligned};
      else                          // Status is not updated when status read is requested
        status <= #1 {crc_match_i, 2'b10, address_unaligned};
    end
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
// Following status is shifted out: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 if address is unaligned, else 0
// 3. bit:          always 0
// 4. bit:          always 1
 
// Following status is shifted out: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 if address is unaligned, else 0
// 3. bit:          1 if WB timeout occured, else 0
// 4. bit:          1 if WB error occured, else 0
 
reg busy_wb;
reg busy_tck;
reg wb_ack_latched;
reg wb_ack_latched_rst;
reg wb_ack_latched_rst_sync;
reg tck_ack_sync;
reg tck_ack;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
begin
  if (pause_dr_i)
  begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
  end
  else if (crc_cnt_end & (~crc_cnt_end_q))
  begin
    tdo_o = crc_match_i;
    TDO_WISHBONE = "crc_match_i";
  end
  else
  begin
    tdo_o = status[0];
    TDO_WISHBONE = "status";
  end
end
 
assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
 
reg [2:0]  cmd;
reg [31:0] adr;
reg [15:0] len;
reg start_tck;
reg start_sync1;
reg start_wb;
reg start_wb_q;
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd <= #1 dr[2:0];
      adr <= #1 dr[34:3];
      len <= #1 dr[50:35];
      start_tck <= #1 1'b1;
    end
  else
    start_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_sync1 <= #1 start_tck;
  start_wb <= #1 start_sync1;
  start_wb_q <= #1 start_wb;
end
 
reg [7:0] acc_cnt;
wire acc_cnt_limit;
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_cyc_o <= #1 1'b0;
  else if (start_wb & (~start_wb_q) & cmd[2])     // "read" or "go" command   igor !!! tu pride se nekaj, ki starta vse naslednje accesse
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i | acc_cnt_limit)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
//  if (start_wb & (~start_wb_q) & (cmd > `WB_STATUS) & (cmd < `WB_GO)) // Setting starting address
  if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((cmd == `WB_WRITE8) | (cmd == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((cmd == `WB_WRITE16) | (cmd == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
always @ (wb_adr_o or cmd)
begin
  wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
  wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
  wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
  wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
end
//      byte  |  short  |  long
//  0   1000     1100      1111
//  1   0100     err       err
//  2   0010     0011      err
//  3   0001     err       err
 
 
always @ (dr)
begin
  address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
end
 
`define WB_STATUS     3'h0  // 000
`define WB_WRITE8     3'h1  // 001
`define WB_WRITE16    3'h2  // 010
`define WB_WRITE32    3'h3  // 011
`define WB_GO         3'h4  // 100
`define WB_READ8      3'h5  // 101
`define WB_READ16     3'h6  // 110
`define WB_READ32     3'h7  // 111
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    acc_cnt<= #1 8'h0;
  else
  if(wb_ack_i | wb_err_i | acc_cnt_limit)
    acc_cnt<= #1 8'h0;
  else
  if(wb_cyc_o)
    acc_cnt<= #1 acc_cnt + 1'b1;
end
 
assign acc_cnt_limit = acc_cnt==8'hff;
 
 
assign wb_we_o = ~cmd[2];   // Status or write (for simpler logic status is allowed)
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
reg [31:0] input_storage;
 
always @ (posedge wb_clk_i)
begin
  if(wb_ack_i)
    input_storage <= #1 wb_dat_i;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_ack_latched <= #1 1'b0;
  else if (wb_ack_i)
    wb_ack_latched <= #1 1'b1;
  else if (wb_ack_latched_rst)
    wb_ack_latched <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      tck_ack_sync <= #1 1'b0;
      tck_ack  <= #1 1'b0;
    end
  else
    begin
      tck_ack_sync <= #1 wb_ack_latched;
      tck_ack  <= #1 tck_ack_sync;
    end
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_ack_latched_rst | wb_err_i | acc_cnt_limit)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_ack_latched_rst_sync <= #1 tck_ack;
  wb_ack_latched_rst  <= #1 wb_ack_latched_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i | acc_cnt_limit)
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_timeout <= #1 1'b0;
  else if(acc_cnt_limit)
    wb_timeout <= #1 1'b1;
  else if(wb_ack_i | wb_err_i)
    wb_timeout <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_timeout_sync <= #1 wb_timeout;
  wb_timeout_tck  <= #1 wb_timeout_sync;
end
 
 
endmodule
 

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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 83

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
47			`// New directory structure. New version of the debug interface.`
48	82	mohor	`//`
49			`//`
50	83	mohor	`//`
51	82	mohor
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "dbg_wb_defines.v"
56
57			`// Top module`
58			`module dbg_wb(`
59			`// JTAG signals`
60			`trst_i, // trst_i is active high (inverted on higher layers)`
61			`tck_i,`
62			`tdi_i,`
63			`tdo_o,`
64
65			`// TAP states`
66			`shift_dr_i,`
67			`pause_dr_i,`
68			`update_dr_i,`
69
70			`wishbone_ce_i,`
71			`crc_match_i,`
72			`crc_en_o,`
73			`shift_crc_o,`
74
75			`// WISHBONE common signals`
76			`wb_rst_i, wb_clk_i,`
77
78			`// WISHBONE master interface`
79			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
80			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
81
82			`);`
83
84			`// JTAG signals`
85			`input trst_i;`
86			`input tck_i;`
87			`input tdi_i;`
88			`output tdo_o;`
89
90			`// TAP states`
91			`input shift_dr_i;`
92			`input pause_dr_i;`
93			`input update_dr_i;`
94
95			`input wishbone_ce_i;`
96			`input crc_match_i;`
97			`output crc_en_o;`
98			`output shift_crc_o;`
99
100			`// WISHBONE common signals`
101			`input wb_rst_i; // WISHBONE reset`
102			`input wb_clk_i; // WISHBONE clock`
103
104			`// WISHBONE master interface`
105			`output [31:0] wb_adr_o;`
106			`output [31:0] wb_dat_o;`
107			`input [31:0] wb_dat_i;`
108			`output wb_cyc_o;`
109			`output wb_stb_o;`
110			`output [3:0] wb_sel_o;`
111			`output wb_we_o;`
112			`input wb_ack_i;`
113			`output wb_cab_o;`
114			`input wb_err_i;`
115			`output [2:0] wb_cti_o;`
116			`output [1:0] wb_bte_o;`
117
118			`reg wb_cyc_o;`
119			`reg [31:0] wb_adr_o;`
120			`reg [3:0] wb_sel_o;`
121
122			`reg tdo_o;`
123
124			reg [`WB_DR_LEN -1:0] dr;
125			`wire enable;`
126			`reg [5:0] cnt;`
127			`reg [5:0] crc_cnt;`
128			`wire cnt_end;`
129			`wire crc_cnt_end;`
130			`reg crc_cnt_end_q;`
131
132
133			reg [`STATUS_CNT -1:0] status_cnt;
134			`wire status_cnt_end;`
135
136			`assign enable = wishbone_ce_i & shift_dr_i;`
137			`assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC`
138
139
140			`always @ (posedge tck_i)`
141			`begin`
142			`if (enable & (~cnt_end))`
143			dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
144			`end`
145
146
147			`always @ (posedge tck_i or posedge trst_i)`
148			`begin`
149			`if (trst_i)`
150			`cnt <= #1 'h0;`
151			`else if (update_dr_i)`
152			`cnt <= #1 'h0;`
153			`else if (enable & (~cnt_end))`
154			`cnt <= #1 cnt + 1'b1;`
155			`end`
156
157			assign cnt_end = cnt == `WB_DR_LEN;
158
159
160			`// crc counter`
161			`always @ (posedge tck_i or posedge trst_i)`
162			`begin`
163			`if (trst_i)`
164			`crc_cnt <= #1 'h0;`
165			`else if(enable & cnt_end & (~crc_cnt_end))`
166			`crc_cnt <= #1 crc_cnt + 1'b1;`
167			`else if (update_dr_i)`
168			`crc_cnt <= #1 'h0;`
169			`end`
170
171			`assign crc_cnt_end = crc_cnt == 6'd32;`
172
173			`always @ (posedge tck_i)`
174			`begin`
175			`crc_cnt_end_q <= #1 crc_cnt_end;`
176			`end`
177
178			`// status counter`
179			`always @ (posedge tck_i or posedge trst_i)`
180			`begin`
181			`if (trst_i)`
182			`status_cnt <= #1 'h0;`
183			`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
184			`status_cnt <= #1 status_cnt + 1'b1;`
185			`else if (update_dr_i)`
186			`status_cnt <= #1 'h0;`
187			`end`
188
189			assign status_cnt_end = status_cnt == `STATUS_LEN;
190			reg [`STATUS_LEN -1:0] status;
191			`reg address_unaligned;`
192
193			`reg wb_error, wb_error_sync, wb_error_tck;`
194			`reg wb_timeout, wb_timeout_sync, wb_timeout_tck;`
195
196
197			`always @ (posedge tck_i or posedge trst_i)`
198			`begin`
199			`if (trst_i)`
200			`status <= #1 'h0;`
201			`else if(crc_cnt_end & (~crc_cnt_end_q))`
202			`begin`
203			if (dr[2:0] == `WB_STATUS)
204			`status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, address_unaligned};`
205			`else // Status is not updated when status read is requested`
206			`status <= #1 {crc_match_i, 2'b10, address_unaligned};`
207			`end`
208			`else if (shift_dr_i & (~status_cnt_end))`
209			status <= #1 {status[0], status[`STATUS_LEN -1:1]};
210			`end`
211			`// Following status is shifted out:`
212			`// 1. bit: 1 if crc is OK, else 0`
213			`// 2. bit: 1 if address is unaligned, else 0`
214			`// 3. bit: always 0`
215			`// 4. bit: always 1`
216
217			`// Following status is shifted out:`
218			`// 1. bit: 1 if crc is OK, else 0`
219			`// 2. bit: 1 if address is unaligned, else 0`
220			`// 3. bit: 1 if WB timeout occured, else 0`
221			`// 4. bit: 1 if WB error occured, else 0`
222
223			`reg busy_wb;`
224			`reg busy_tck;`
225			`reg wb_ack_latched;`
226			`reg wb_ack_latched_rst;`
227			`reg wb_ack_latched_rst_sync;`
228			`reg tck_ack_sync;`
229			`reg tck_ack;`
230			`reg busy_sync;`
231			`reg [799:0] TDO_WISHBONE;`
232
233			`always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)`
234			`begin`
235			`if (pause_dr_i)`
236			`begin`
237			`tdo_o = busy_tck;`
238			`TDO_WISHBONE = "busy_tck";`
239			`end`
240			`else if (crc_cnt_end & (~crc_cnt_end_q))`
241			`begin`
242			`tdo_o = crc_match_i;`
243			`TDO_WISHBONE = "crc_match_i";`
244			`end`
245			`else`
246			`begin`
247			`tdo_o = status[0];`
248			`TDO_WISHBONE = "status";`
249			`end`
250			`end`
251
252			`assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;`
253
254			`reg [2:0] cmd;`
255			`reg [31:0] adr;`
256			`reg [15:0] len;`
257			`reg start_tck;`
258			`reg start_sync1;`
259			`reg start_wb;`
260			`reg start_wb_q;`
261
262			`always @ (posedge tck_i)`
263			`begin`
264			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
265			`begin`
266			`cmd <= #1 dr[2:0];`
267			`adr <= #1 dr[34:3];`
268			`len <= #1 dr[50:35];`
269			`start_tck <= #1 1'b1;`
270			`end`
271			`else`
272			`start_tck <= #1 1'b0;`
273			`end`
274
275
276			`always @ (posedge wb_clk_i)`
277			`begin`
278			`start_sync1 <= #1 start_tck;`
279			`start_wb <= #1 start_sync1;`
280			`start_wb_q <= #1 start_wb;`
281			`end`
282
283			`reg [7:0] acc_cnt;`
284			`wire acc_cnt_limit;`
285
286			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
287			`begin`
288			`if (wb_rst_i)`
289			`wb_cyc_o <= #1 1'b0;`
290			`else if (start_wb & (~start_wb_q) & cmd[2]) // "read" or "go" command igor !!! tu pride se nekaj, ki starta vse naslednje accesse`
291			`wb_cyc_o <= #1 1'b1;`
292			`else if (wb_ack_i \| wb_err_i \| acc_cnt_limit)`
293			`wb_cyc_o <= #1 1'b0;`
294			`end`
295
296
297
298			`always @ (posedge wb_clk_i)`
299			`begin`
300			// if (start_wb & (~start_wb_q) & (cmd > `WB_STATUS) & (cmd < `WB_GO)) // Setting starting address
301			if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
302			`wb_adr_o <= #1 adr;`
303			`else if (wb_ack_i)`
304			`begin`
305			if ((cmd == `WB_WRITE8) \| (cmd == `WB_READ8))
306			`wb_adr_o <= #1 wb_adr_o + 1'd1;`
307			else if ((cmd == `WB_WRITE16) \| (cmd == `WB_READ16))
308			`wb_adr_o <= #1 wb_adr_o + 2'd2;`
309			`else`
310			`wb_adr_o <= #1 wb_adr_o + 3'd4;`
311			`end`
312			`end`
313
314
315			`always @ (wb_adr_o or cmd)`
316			`begin`
317			`wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) \|`
318			`(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);`
319			`wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);`
320			`wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);`
321			`wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);`
322			`end`
323			`// byte \| short \| long`
324			`// 0 1000 1100 1111`
325			`// 1 0100 err err`
326			`// 2 0010 0011 err`
327			`// 3 0001 err err`
328
329
330			`always @ (dr)`
331			`begin`
332			`address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) \| (dr[1:0] == 2'b10) & (dr[3]);`
333			`end`
334
335			`define WB_STATUS 3'h0 // 000
336			`define WB_WRITE8 3'h1 // 001
337			`define WB_WRITE16 3'h2 // 010
338			`define WB_WRITE32 3'h3 // 011
339			`define WB_GO 3'h4 // 100
340			`define WB_READ8 3'h5 // 101
341			`define WB_READ16 3'h6 // 110
342			`define WB_READ32 3'h7 // 111
343
344			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
345			`begin`
346			`if(wb_rst_i)`
347			`acc_cnt<= #1 8'h0;`
348			`else`
349			`if(wb_ack_i \| wb_err_i \| acc_cnt_limit)`
350			`acc_cnt<= #1 8'h0;`
351			`else`
352			`if(wb_cyc_o)`
353			`acc_cnt<= #1 acc_cnt + 1'b1;`
354			`end`
355
356			`assign acc_cnt_limit = acc_cnt==8'hff;`
357
358
359			`assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)`
360			`assign wb_cab_o = 1'b0;`
361			`assign wb_stb_o = wb_cyc_o;`
362			`assign wb_cti_o = 3'h0; // always performing single access`
363			`assign wb_bte_o = 2'h0; // always performing single access`
364
365			`reg [31:0] input_storage;`
366
367			`always @ (posedge wb_clk_i)`
368			`begin`
369			`if(wb_ack_i)`
370			`input_storage <= #1 wb_dat_i;`
371			`end`
372
373
374
375			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
376			`begin`
377			`if (wb_rst_i)`
378			`wb_ack_latched <= #1 1'b0;`
379			`else if (wb_ack_i)`
380			`wb_ack_latched <= #1 1'b1;`
381			`else if (wb_ack_latched_rst)`
382			`wb_ack_latched <= #1 1'b0;`
383			`end`
384
385
386			`always @ (posedge tck_i or posedge trst_i)`
387			`begin`
388			`if (trst_i)`
389			`begin`
390			`tck_ack_sync <= #1 1'b0;`
391			`tck_ack <= #1 1'b0;`
392			`end`
393			`else`
394			`begin`
395			`tck_ack_sync <= #1 wb_ack_latched;`
396			`tck_ack <= #1 tck_ack_sync;`
397			`end`
398			`end`
399
400
401			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
402			`begin`
403			`if (wb_rst_i)`
404			`busy_wb <= #1 1'b0;`
405			`else if (wb_ack_latched_rst \| wb_err_i \| acc_cnt_limit)`
406			`busy_wb <= #1 1'b0;`
407			`else if (wb_cyc_o)`
408			`busy_wb <= #1 1'b1;`
409			`end`
410
411
412			`always @ (posedge tck_i or posedge trst_i)`
413			`begin`
414			`if (trst_i)`
415			`begin`
416			`busy_sync <= #1 1'b0;`
417			`busy_tck <= #1 1'b0;`
418			`end`
419			`else`
420			`begin`
421			`busy_sync <= #1 busy_wb;`
422			`busy_tck <= #1 busy_sync;`
423			`end`
424			`end`
425
426
427			`always @ (posedge wb_clk_i)`
428			`begin`
429			`wb_ack_latched_rst_sync <= #1 tck_ack;`
430			`wb_ack_latched_rst <= #1 wb_ack_latched_rst_sync;`
431			`end`
432
433
434			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
435			`begin`
436			`if (wb_rst_i)`
437			`wb_error <= #1 1'b0;`
438			`else if(wb_err_i)`
439			`wb_error <= #1 1'b1;`
440			`else if(wb_ack_i \| acc_cnt_limit)`
441			`wb_error <= #1 1'b0;`
442			`end`
443
444			`always @ (posedge tck_i)`
445			`begin`
446			`wb_error_sync <= #1 wb_error;`
447			`wb_error_tck <= #1 wb_error_sync;`
448			`end`
449
450
451			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
452			`begin`
453			`if (wb_rst_i)`
454			`wb_timeout <= #1 1'b0;`
455			`else if(acc_cnt_limit)`
456			`wb_timeout <= #1 1'b1;`
457			`else if(wb_ack_i \| wb_err_i)`
458			`wb_timeout <= #1 1'b0;`
459			`end`
460
461			`always @ (posedge tck_i)`
462			`begin`
463			`wb_timeout_sync <= #1 wb_timeout;`
464			`wb_timeout_tck <= #1 wb_timeout_sync;`
465			`end`
466
467
468			`endmodule`
469