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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [cpu_behavioral.v] - Blame information for rev 102

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// cpu_behavioral.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2004/01/17 17:01:25  mohor
// Almost finished.
//
//
//
//
//
`include "timescale.v"
`include "dbg_cpu_defines.v"
 
 
 
module cpu_behavioral
                   (
                    // CPU signals
                    cpu_rst_i,
                    cpu_clk_o,
                    cpu_addr_i,
                    cpu_data_o,
                    cpu_data_i,
                    cpu_bp_o,
                    cpu_stall_i,
                    cpu_stall_all_i,
                    cpu_stb_i,
                    cpu_sel_i,
                    cpu_we_i,
                    cpu_ack_o,
                    cpu_rst_o
                   );
 
 
// CPU signals
input         cpu_rst_i;
output        cpu_clk_o;
input  [31:0] cpu_addr_i;
output [31:0] cpu_data_o;
input  [31:0] cpu_data_i;
output        cpu_bp_o;
input         cpu_stall_i;
input         cpu_stall_all_i;
input         cpu_stb_i;
input [`CPU_NUM -1:0]  cpu_sel_i;
input         cpu_we_i;
output        cpu_ack_o;
output        cpu_rst_o;
 
reg           cpu_clk_o;
reg    [31:0] cpu_data_o;
 
initial
begin
  cpu_clk_o = 1'b0;
  forever #5 cpu_clk_o = ~cpu_clk_o;
end
 
 
assign cpu_bp_o = 1'b0;
 
assign #200 cpu_ack_o = cpu_stall_i & cpu_stb_i;
 
 
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
  if (cpu_rst_i)
    cpu_data_o <= #1 32'h11111111;
  else if ((cpu_addr_i == 32'h32323232) & cpu_we_i & cpu_ack_o)
    cpu_data_o <= #1 cpu_data_i + 1'd1;
  else if ((cpu_addr_i == 32'h08080808) & cpu_we_i & cpu_ack_o)
    cpu_data_o <= #1 cpu_data_i + 2'd2;
end
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	101	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// cpu_behavioral.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	102	mohor	`// Revision 1.1 2004/01/17 17:01:25 mohor`
47			`// Almost finished.`
48	101	mohor	`//`
49			`//`
50			`//`
51			`//`
52	102	mohor	`//`
53	101	mohor	`include "timescale.v"
54			`include "dbg_cpu_defines.v"
55
56
57
58			`module cpu_behavioral`
59			`(`
60			`// CPU signals`
61			`cpu_rst_i,`
62			`cpu_clk_o,`
63			`cpu_addr_i,`
64			`cpu_data_o,`
65			`cpu_data_i,`
66			`cpu_bp_o,`
67			`cpu_stall_i,`
68			`cpu_stall_all_i,`
69			`cpu_stb_i,`
70			`cpu_sel_i,`
71			`cpu_we_i,`
72			`cpu_ack_o,`
73			`cpu_rst_o`
74			`);`
75
76
77			`// CPU signals`
78			`input cpu_rst_i;`
79			`output cpu_clk_o;`
80			`input [31:0] cpu_addr_i;`
81			`output [31:0] cpu_data_o;`
82			`input [31:0] cpu_data_i;`
83			`output cpu_bp_o;`
84			`input cpu_stall_i;`
85			`input cpu_stall_all_i;`
86			`input cpu_stb_i;`
87			input [`CPU_NUM -1:0] cpu_sel_i;
88			`input cpu_we_i;`
89			`output cpu_ack_o;`
90			`output cpu_rst_o;`
91
92			`reg cpu_clk_o;`
93	102	mohor	`reg [31:0] cpu_data_o;`
94	101	mohor
95			`initial`
96			`begin`
97			`cpu_clk_o = 1'b0;`
98			`forever #5 cpu_clk_o = ~cpu_clk_o;`
99			`end`
100
101
102			`assign cpu_bp_o = 1'b0;`
103
104			`assign #200 cpu_ack_o = cpu_stall_i & cpu_stb_i;`
105
106
107
108			`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`
109			`begin`
110			`if (cpu_rst_i)`
111	102	mohor	`cpu_data_o <= #1 32'h11111111;`
112	101	mohor	`else if ((cpu_addr_i == 32'h32323232) & cpu_we_i & cpu_ack_o)`
113	102	mohor	`cpu_data_o <= #1 cpu_data_i + 1'd1;`
114	101	mohor	`else if ((cpu_addr_i == 32'h08080808) & cpu_we_i & cpu_ack_o)`
115	102	mohor	`cpu_data_o <= #1 cpu_data_i + 2'd2;`
116	101	mohor	`end`
117
118
119
120
121			`endmodule`
122

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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [cpu_behavioral.v] - Blame information for rev 102