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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_tb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/10/23 16:16:30  mohor
// CRC logic changed.
//
// Revision 1.13  2003/08/28 13:54:33  simons
// Three more chains added for cpu debug access.
//
// Revision 1.12  2002/05/07 14:44:52  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.11  2002/03/12 14:32:26  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.10  2002/03/08 15:27:08  mohor
// Structure changed. Hooks for jtag chain added.
//
// Revision 1.9  2001/10/19 11:39:20  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8  2001/10/17 10:39:17  mohor
// bs_chain_o added.
//
// Revision 1.7  2001/10/16 10:10:18  mohor
// Signal names changed to lowercase.
//
// Revision 1.6  2001/10/15 09:52:50  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5  2001/09/24 14:06:12  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4  2001/09/20 10:10:29  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:54:03  mohor
// Minor changes for simulation.
//
// Revision 1.2  2001/09/18 14:12:43  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:23:40  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:05  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:15  mohor
// Initial release
//
//
 
 
`include "timescale.v"
`include "dbg_defines.v"
`include "dbg_wb_defines.v"
//`include "dbg_tb_defines.v"
 
// Test bench
module dbg_tb;
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
reg   tms_pad_i;
reg   tck_pad_i;
reg   trst_pad_i;
reg   tdi_pad_i;
wire  tdo_pad_o;
wire  tdo_padoe_o;
 
wire  shift_dr_o;
wire  pause_dr_o;
wire  update_dr_o;
 
wire  extest_select_o;
wire  sample_preload_select_o;
wire  mbist_select_o;
wire  debug_select_o;
 
// WISHBONE common signals
reg   wb_rst_i;
reg   wb_clk_i;
 
// WISHBONE master interface
wire [31:0] wb_adr_o;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
wire        wb_cyc_o;
wire        wb_stb_o;
wire  [3:0] wb_sel_o;
wire        wb_we_o;
wire        wb_ack_i;
wire        wb_cab_o;
wire        wb_err_i;
wire  [2:0] wb_cti_o;
wire  [1:0] wb_bte_o;
 
 
 
 
 
 
wire  tdo_o;
 
wire  debug_tdi_i;
wire  bs_chain_tdi_i;
wire  mbist_tdi_i;
 
reg   test_enabled;
 
reg [31:0] result;
 
wire tdo;
 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
 
// Connecting TAP module
tap_top i_tap_top (
                    .tms_pad_i(tms_pad_i),
                    .tck_pad_i(tck_pad_i),
                    .trst_pad_i(!trst_pad_i),
                    .tdi_pad_i(tdi_pad_i),
                    .tdo_pad_o(tdo_pad_o),
                    .tdo_padoe_o(tdo_padoe_o),
 
                    // TAP states
                    .shift_dr_o(shift_dr_o),
                    .pause_dr_o(pause_dr_o),
                    .update_dr_o(update_dr_o),
 
                    // Select signals for boundary scan or mbist
                    .extest_select_o(extest_select_o),
                    .sample_preload_select_o(sample_preload_select_o),
                    .mbist_select_o(mbist_select_o),
                    .debug_select_o(debug_select_o),
 
                    // TDO signal that is connected to TDI of sub-modules.
                    .tdo_o(tdo_o),
 
                    // TDI signals from sub-modules
                    .debug_tdi_i(debug_tdi_i),        // from debug module
                    .bs_chain_tdi_i(bs_chain_tdi_i),  // from Boundary Scan Chain
                    .mbist_tdi_i(mbist_tdi_i)         // from Mbist Chain
 
               );
 
 
dbg_top i_dbg_top  (
 
                    .trst_i(!trst_pad_i),
                    .tck_i(tck_pad_i),
                    .tdi_i(tdo_o),
                    .tdo_o(debug_tdi_i),
 
                    // TAP states
                    .shift_dr_i   (shift_dr_o),
                    .pause_dr_i   (pause_dr_o),
                    .update_dr_i  (update_dr_o),
 
                    // Instructions
                    .debug_select_i(debug_select_o),
 
                    // WISHBONE common signals
                    .wb_rst_i      (wb_rst_i),
                    .wb_clk_i      (wb_clk_i),
 
                    // WISHBONE master interface
                    .wb_adr_o      (wb_adr_o),
                    .wb_dat_o      (wb_dat_o),
                    .wb_dat_i      (wb_dat_i),
                    .wb_cyc_o      (wb_cyc_o),
                    .wb_stb_o      (wb_stb_o),
                    .wb_sel_o      (wb_sel_o),
                    .wb_we_o       (wb_we_o),
                    .wb_ack_i      (wb_ack_i),
                    .wb_cab_o      (wb_cab_o),
                    .wb_err_i      (wb_err_i),
                    .wb_cti_o      (wb_cti_o),
                    .wb_bte_o      (wb_bte_o)
                   );
 
 
wb_slave_behavioral wb_slave
                   (
                    .CLK_I(wb_clk_i),
                    .RST_I(wb_rst_i),
                    .ACK_O(wb_ack_i),
                    .ADR_I(wb_adr_o),
                    .CYC_I(wb_cyc_o),
                    .DAT_O(wb_dat_i),
                    .DAT_I(wb_dat_o),
                    .ERR_O(wb_err_i),
                    .RTY_O(),      // NOT USED for now!
                    .SEL_I(wb_sel_o),
                    .STB_I(wb_stb_o),
                    .WE_I (wb_we_o),
                    .CAB_I(1'b0)
                   );
 
 
// Initial values
initial
begin
  test_enabled = 1'b0;
  trst_pad_i = 1'b1;
  tms_pad_i = 1'hz;
  tck_pad_i = 1'hz;
  tdi_pad_i = 1'hz;
 
  #100;
  trst_pad_i = 1'b0;
  #100;
  trst_pad_i = 1'b1;
  #1 test_enabled<=#1 1'b1;
end
 
initial
begin
  wb_rst_i = 1'b0;
  #1000;
  wb_rst_i = 1'b1;
  #1000;
  wb_rst_i = 1'b0;
 
  // Initial values for wishbone slave model
  wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
end
 
initial
begin
  wb_clk_i = 1'b0;
  forever #5 wb_clk_i = ~wb_clk_i;
end
 
always @ (posedge test_enabled)
begin
 
  $display("//////////////////////////////////////////////////////////////////");
  $display("//                                                              //");
  $display("//  (%0t) dbg_tb starting                                     //", $time);
  $display("//                                                              //");
  $display("//////////////////////////////////////////////////////////////////");
 
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
 
  reset_tap;
  goto_run_test_idle;
 
  // Testing read and write to internal registers
  #10000;
  set_instruction(`IDCODE);
  read_id_code;
 
  set_instruction(`DEBUG);
  #10000;
 
  chain_select(`WISHBONE_SCAN_CHAIN, 32'hf2bcd929);
 
//  #10000;
//  xxx(4'b1001, 32'he579b242);
 
  #10000;
 
//  debug_wishbone(`WB_READ8, 32'h12345678, 32'h0, 16'h4, 32'h08359131, result); // {command, addr, data, length, crc, result}
//  debug_wishbone(`WB_READ8, 32'h12345679, 32'h0, 16'h4, 32'hadfeabe2, result); // {command, addr, data, length, crc, result}
//  debug_wishbone(`WB_READ8, 32'h1234567a, 32'h0, 16'h4, 32'hd8b08283, result); // {command, addr, data, length, crc, result}
 
//  debug_wishbone(`WB_READ16, 32'h12345678, 32'h0, 16'h4, 32'haf07fce0, result); // {command, addr, data, length, crc, result}
//  debug_wishbone(`WB_READ16, 32'h1234567a, 32'h0, 16'h4, 32'h7f82ef52, result); // {command, addr, data, length, crc, result}
 
  debug_wishbone(`WB_READ32, 32'h12345678, 32'h0, 16'h4, 32'h969b4113, result); // {command, addr, data, length, crc, result}
 
//  debug_wishbone(`WB_READ16, 32'h12345679, 32'h0, 16'h4, 32'h0accc633, result); // {command, addr, data, length, crc, result}
 
  #10000;
//  xxx(4'b1001, 32'he579b242);
 
  wb_slave.cycle_response(`NO_RESPONSE, 8'h03, 8'h2);   // (`NO_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone_shift_dr(`WB_READ32, 32'h12345678, 32'h0, 16'h4, 32'h969b4113, result); // {command, addr, data, length, crc, result}
  wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
  #10000;
  debug_wishbone_shift_dr(`WB_READ32, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result); // {command, addr, data, length, crc, result}
 
  #10000;
  debug_wishbone_shift_dr(`WB_READ32, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result); // {command, addr, data, length, crc, result}
 
 
 
/*
  // Testing read and write to CPU0 registers
  #10000;
  set_instruction(`CHAIN_SELECT);
  chain_select(`CPU_DEBUG_CHAIN_0, 8'h12);  // {chain, crc}
  set_instruction(`DEBUG);
  WriteCPURegister(32'h11001100, 32'h00110011, 8'h86);  // {data, addr, crc}
 
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
*/
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
  #1000 $stop;
 
end
 
 
task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin
    for (i=0; i<length; i=i+4)
      begin
        addr = start_addr + i;
        wb_slave.wr_mem(addr, {addr[7:0], addr[15:8], addr[23:16], addr[31:24]}, 4'hf);    // adr, data, sel
      end
  end
endtask
 
 
 
// Generation of the TCLK signal
task gen_clk;
  input [7:0] num;
  integer i;
  begin
    for(i=0; i<num; i=i+1)
      begin
        #TCLK tck_pad_i<=1;
        #TCLK tck_pad_i<=0;
      end
  end
endtask
 
 
// TAP reset
task reset_tap;
  begin
    $display("(%0t) Task reset_tap", $time);
    tms_pad_i<=#1 1'b1;
    gen_clk(7);
  end
endtask
 
 
// Goes to RunTestIdle state
task goto_run_test_idle;
  begin
    $display("(%0t) Task goto_run_test_idle", $time);
    tms_pad_i<=#1 1'b0;
    gen_clk(1);
  end
endtask
 
 
// sets the instruction to the IR register and goes to the RunTestIdle state
task set_instruction;
  input [3:0] instr;
  integer i;
 
  begin
    $display("(%0t) Task set_instruction", $time);
    tms_pad_i<=#1 1;
    gen_clk(2);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftIR
 
    for(i=0; i<`IR_LENGTH-1; i=i+1)
    begin
      tdi_pad_i<=#1 instr[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 instr[i]; // last shift
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
      tdi_pad_i<=#1 'hz;    // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Reads the ID code
task read_id_code;
  begin
    $display("(%0t) Task read_id_code", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 0;
    gen_clk(31);
 
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
 
    tdi_pad_i<=#1 'hz; // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task chain_select;
  input [3:0]  data;
  input [31:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task chain_select", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b1; // chain_select bit
    gen_clk(1);
 
    for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN -1-i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
// Performs 32-bit read to the selected chain
task debug_wishbone;
  input [2:0]   command;
  input [31:0]  addr;
  input [31:0]  data;
  input [15:0]  length;
  input [31:0]  crc;
  output [31:0] result;
  integer i;
 
  begin
   $write("(%0t) Task debug_wishbone: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    case (command)
      `WB_STATUS   :
        begin
          $display("wb_status");
        end
      `WB_READ8    :
        begin
          $display("wb_read8 (adr=0x%0x, length=0x%0x, crc=0x%0x)", addr, length, crc);
        end
      `WB_READ16   :
        begin
          $display("wb_read16 (adr=0x%0x, length=0x%0x, crc=0x%0x)", addr, length, crc);
        end
      `WB_READ32   :
        begin
          $display("wb_read32 (adr=0x%0x, length=0x%0x, crc=0x%0x)", addr, length, crc);
        end
      `WB_WRITE8   :
        begin
          $display("wb_write8 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x)", addr, data, length, crc);
        end
      `WB_WRITE16  :
        begin
          $display("wb_write16 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x)", addr, data, length, crc);
        end
      `WB_WRITE32  :
        begin
          $display("wb_write32 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x)", addr, data, length, crc);
        end
      `WB_GO       :
        begin
          $display("wb_go, crc=0x%0x)", crc);
        end
    endcase
 
 
 
 
    for(i=0; i<3; i=i+1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    for(i=0; i<32; i=i+1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      gen_clk(1);
    end
 
    for(i=0; i<16; i=i+1)       // length
    begin
      tdi_pad_i<=#1 length[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN -1-i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
 
 
 
 
// Performs 32-bit read to the selected chain waiting some time in shift_dr
task debug_wishbone_shift_dr;
  input [2:0]   command;
  input [31:0]  addr;
  input [31:0]  data;
  input [15:0]  length;
  input [31:0]  crc;
  output [31:0] result;
  integer i;
 
  begin
   $write("(%0t) Task debug_wishbone_shift_dr: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    case (command)
      `WB_STATUS   :
        begin
          $display("wb_status");
        end
      `WB_READ8    :
        begin
          $display("wb_read8 (adr=0x%0x, length=0x%0x, crc=0x%0x)", addr, length, crc);
        end
      `WB_READ16   :
        begin
          $display("wb_read16 (adr=0x%0x, length=0x%0x, crc=0x%0x)", addr, length, crc);
        end
      `WB_READ32   :
        begin
          $display("wb_read32 (adr=0x%0x, length=0x%0x, crc=0x%0x)", addr, length, crc);
        end
      `WB_WRITE8   :
        begin
          $display("wb_write8 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x)", addr, data, length, crc);
        end
      `WB_WRITE16  :
        begin
          $display("wb_write16 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x)", addr, data, length, crc);
        end
      `WB_WRITE32  :
        begin
          $display("wb_write32 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x)", addr, data, length, crc);
        end
      `WB_GO       :
        begin
          $display("wb_go, crc=0x%0x)", crc);
        end
    endcase
 
 
 
 
    for(i=0; i<3; i=i+1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    for(i=0; i<32; i=i+1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      gen_clk(1);
    end
 
    for(i=0; i<16; i=i+1)       // length
    begin
      tdi_pad_i<=#1 length[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN -1-i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN -1);   // Generating 4 clocks to read out status. Going to pause_dr at the end
 
    tdi_pad_i<=#1 'hz;
    tms_pad_i<=#1 1;
    gen_clk(1);       // to exit1_dr
    tms_pad_i<=#1 0;
    gen_clk(1);       // to pause_dr
 
    while (dbg_tb.tdo_pad_o)     // waiting for wb to send "ready" 
    begin
      gen_clk(1);       // staying in pause_dr
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);       // to exit2_dr
    tms_pad_i<=#1 0;
    gen_clk(1);       // to shift_dr
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
 
 
 
 
// Reads sample from the Trace Buffer
task ReadTraceBuffer;
  begin
    $display("(%0t) Task ReadTraceBuffer", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 0;
    gen_clk(47);
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
      tdi_pad_i<=#1 'hz; // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Reads the CPU register and latches the data so it is ready for reading
task ReadCPURegister;
  input [31:0] Address;
  input [7:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task ReadCPURegister", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<32; i=i+1)
    begin
      tdi_pad_i<=#1 Address[i];  // Shifting address
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 0;             // shifting RW bit = read
    gen_clk(1);
 
    for(i=0; i<32; i=i+1)
    begin
      tdi_pad_i<=#1 0;     // Shifting data. Data is not important in read cycle.
      gen_clk(1);
    end
 
//    for(i=0; i<`CRC_LEN -1; i=i+1)
    for(i=0; i<`CRC_LEN; i=i+1)      // crc is 9 bit long
    begin
      tdi_pad_i<=#1 crc[i];     // Shifting CRC.
      gen_clk(1);
    end
 
//    tdi_pad_i<=#1 crc[i];   // Shifting last bit of CRC.
    tdi_pad_i<=#1 1'b0;       // crc[i];   // Shifting last bit of CRC.
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
      tdi_pad_i<=#1 'hz;   // Tristate TDI.
    gen_clk(1);
 
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Write the CPU register
task WriteCPURegister;
  input [31:0] data;
  input [31:0] Address;
  input [`CRC_LEN -1:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task WriteCPURegister", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<32; i=i+1)
    begin
      tdi_pad_i<=#1 Address[i];  // Shifting address
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1;             // shifting RW bit = write
    gen_clk(1);
 
    for(i=0; i<32; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];     // Shifting data
      gen_clk(1);
    end
 
//    for(i=0; i<`CRC_LEN -1; i=i+1)
    for(i=0; i<`CRC_LEN; i=i+1)      // crc is 9 bit long
    begin
      tdi_pad_i<=#1 crc[i];     // Shifting CRC
      gen_clk(1);
    end
 
//    tdi_pad_i<=#1 crc[i];        // shifting last bit of CRC
    tdi_pad_i<=#1 1'b0;            // crc[i];        // shifting last bit of CRC
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
      tdi_pad_i<=#1 'hz;        // tristate TDI
    gen_clk(1);
 
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
 
    gen_clk(10);      // Generating few clock cycles needed for the write operation to accomplish
  end
endtask
 
 
// Reads the register and latches the data so it is ready for reading
task ReadRegister;
  input [4:0] Address;
  input [7:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task ReadRegister", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<5; i=i+1)
    begin
      tdi_pad_i<=#1 Address[i];  // Shifting address
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 0;             // shifting RW bit = read
    gen_clk(1);
 
    for(i=0; i<32; i=i+1)
    begin
      tdi_pad_i<=#1 0;     // Shifting data. Data is not important in read cycle.
      gen_clk(1);
    end
 
//    for(i=0; i<`CRC_LEN -1; i=i+1)
    for(i=0; i<`CRC_LEN; i=i+1)      // crc is 9 bit long
    begin
      tdi_pad_i<=#1 crc[i];     // Shifting CRC. CRC is not important in read cycle.
      gen_clk(1);
    end
 
//    tdi_pad_i<=#1 crc[i];     // Shifting last bit of CRC.
    tdi_pad_i<=#1 1'b0;         // crc[i];     // Shifting last bit of CRC.
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
      tdi_pad_i<=#1 'hz;     // Tri state TDI
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
 
    gen_clk(10);      // Generating few clock cycles needed for the read operation to accomplish
  end
endtask
 
 
// Write the register
task WriteRegister;
  input [31:0] data;
  input [4:0] Address;
  input [`CRC_LEN -1:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task WriteRegister", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<5; i=i+1)
    begin
      tdi_pad_i<=#1 Address[i];  // Shifting address
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1;             // shifting RW bit = write
    gen_clk(1);
 
    for(i=0; i<32; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];     // Shifting data
      gen_clk(1);
    end
 
//    for(i=0; i<`CRC_LEN -1; i=i+1)
    for(i=0; i<`CRC_LEN; i=i+1)      // crc is 9 bit long
    begin
      tdi_pad_i<=#1 crc[i];     // Shifting CRC
      gen_clk(1);
    end
 
//    tdi_pad_i<=#1 crc[i];   // Shifting last bit of CRC
    tdi_pad_i<=#1 1'b0;       // crc[i];   // Shifting last bit of CRC
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
      tdi_pad_i<=#1 'hz;   // Tri state TDI
    gen_clk(1);
 
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
 
    gen_clk(5);       // Extra clocks needed for operations to finish 
 
  end
endtask
 
/*
task EnableWishboneSlave;
begin
$display("(%0t) Task EnableWishboneSlave", $time);
while(1)
  begin
    @ (posedge Mclk);
    if(wb_stb_i & wb_cyc_i) // WB access
//    wait (wb_stb_i & wb_cyc_i) // WB access
      begin
        @ (posedge Mclk);
        @ (posedge Mclk);
        @ (posedge Mclk);
        #1 wb_ack_o = 1;
        if(~wb_we_i) // read
          wb_dat_o = 32'hbeefdead;
          wb_dat_o = {wb_adr_i[3:0],   wb_adr_i[7:4],   wb_adr_i[11:8],  wb_adr_i[15:12],
                      wb_adr_i[19:16], wb_adr_i[23:20], wb_adr_i[27:24], wb_adr_i[31:28]};
        if(wb_we_i & wb_stb_i & wb_cyc_i) // write
          $display("\nWISHBONE write data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
        if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
          $display("\nWISHBONE read data=%0h, Addr=%0h", wb_dat_o, wb_adr_i);
      end
    @ (posedge Mclk);
    #1 wb_ack_o = 0;
    wb_dat_o = 32'h0;
  end
 
end
endtask
*/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Printing the information to the screen                                        *
*                                                                                 *
**********************************************************************************/
 
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.update_ir)
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
      `EXTEST         : $display("\tInstruction EXTEST entered");
      `SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
      `IDCODE         : $display("\tInstruction IDCODE entered");
      `MBIST          : $display("\tInstruction MBIST entered");
      `DEBUG          : $display("\tInstruction DEBUG entered");
      `BYPASS         : $display("\tInstruction BYPASS entered");
                default           :     $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
    endcase
end
 
 
// Print selected chain
/*
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.chain_select & dbg_tb.i_dbg_top.update_dr_q)
    case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
      `GLOBAL_BS_CHAIN      : $write("\nChain GLOBAL_BS_CHAIN");
      `CPU_DEBUG_CHAIN_0    : $write("\nChain CPU_DEBUG_CHAIN_0");
      `CPU_DEBUG_CHAIN_1    : $write("\nChain CPU_DEBUG_CHAIN_1");
      `CPU_DEBUG_CHAIN_2    : $write("\nChain CPU_DEBUG_CHAIN_2");
      `CPU_DEBUG_CHAIN_3    : $write("\nChain CPU_DEBUG_CHAIN_3");
      `CPU_TEST_CHAIN       : $write("\nChain CPU_TEST_CHAIN");
      `TRACE_TEST_CHAIN     : $write("\nChain TRACE_TEST_CHAIN");
      `REGISTER_SCAN_CHAIN  : $write("\nChain REGISTER_SCAN_CHAIN");
      `WISHBONE_SCAN_CHAIN  : $write("\nChain WISHBONE_SCAN_CHAIN");
    endcase
end
*/
 
// print CPU registers read/write
/*
always @ (posedge Mclk)
begin
  if(dbg_tb.i_dbg_top.CPUAccess0 & ~dbg_tb.i_dbg_top.CPUAccess_q & dbg_tb.i_dbg_top.RW)
    $write("\n\t\tWrite to CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
  else
  if(dbg_tb.i_dbg_top.CPUAccess_q & ~dbg_tb.i_dbg_top.CPUAccess_q2 & ~dbg_tb.i_dbg_top.RW)
    $write("\n\t\tRead from CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.cpu_data_i[31:0]);
end
*/
 
// print registers read/write
/*
always @ (posedge Mclk)
begin
  if(dbg_tb.i_dbg_top.RegAccess_q & ~dbg_tb.i_dbg_top.RegAccess_q2)
    begin
      if(dbg_tb.i_dbg_top.RW)
        $write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.DataOut[31:0]);
      else
        $write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.RegDataIn[31:0]);
    end
end
*/
 
// print CRC error
/*
`ifdef TRACE_ENABLED
  wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.chain_select | dbg_tb.i_dbg_top.debug_select & register_scan_chain | dbg_tb.i_dbg_top.debug_select & (cpu_debug_scan_chain0 | cpu_debug_scan_chain1 | cpu_debug_scan_chain2 | cpu_debug_scan_chain3) | dbg_tb.i_dbg_top.debug_select & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.debug_select & wishbone_scan_chain));
`else  // TRACE_ENABLED not enabled
  wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.chain_select | dbg_tb.i_tap_top.debug_select & register_scan_chain | dbg_tb.i_tap_top.debug_select & (cpu_debug_scan_chain0 | cpu_debug_scan_chain1 | cpu_debug_scan_chain2 | cpu_debug_scan_chain3) | dbg_tb.i_tap_top.debug_select & wishbone_scan_chain));
`endif
*/
 
/*
// print crc
always @ (posedge P_TCK)
begin
  if(dbg_tb.i_tap_top.update_dr & ~dbg_tb.i_tap_top.idcode_select)
    begin
      if(dbg_tb.i_tap_top.chain_select)
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
      else
      if(register_scan_chain & ~dbg_tb.i_tap_top.chain_select)
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
      else
      if((cpu_debug_scan_chain0 | cpu_debug_scan_chain1 | cpu_debug_scan_chain2 | cpu_debug_scan_chain3) & ~dbg_tb.i_tap_top.chain_select)
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
      if(wishbone_scan_chain & ~dbg_tb.i_tap_top.chain_select)
        $write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
 
      if(CRCErrorReport)
        begin
          $write("\n\t\t\t\tCrc Error when receiving data (read or write) !!!  CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
          #1000 $stop;
        end
      $display("\n");
    end
end
*/
 
// Print shifted IDCode
reg [31:0] tmp_data;
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.idcode_select)
    begin
      if(dbg_tb.i_tap_top.shift_dr)
        tmp_data[31:0]<=#1 {dbg_tb.tdo, tmp_data[31:1]};
      else
      if(dbg_tb.i_tap_top.update_dr)
        if (tmp_data[31:0] != `IDCODE_VALUE)
          begin
            $display("(%0t) ERROR: IDCODE not correct", $time);
            $stop;
          end
        else
          $display("\t\tIDCode = 0x%h", tmp_data[31:0]);
    end
end
 
 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
    begin
      $display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
      $display("(%0t) Simulation stopped !!!", $time);
      $stop;
    end
end
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task xxx;
  input [3:0]  data;
  input [31:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task xxx", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<4; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN - 1 - i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
 
 
 
endmodule // dbg_tb
 
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_tb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7	36	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	80	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	80	mohor	`//// Copyright (C) 2000 - 2003 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	80	mohor	`// Revision 1.14 2003/10/23 16:16:30 mohor`
47			`// CRC logic changed.`
48			`//`
49	73	mohor	`// Revision 1.13 2003/08/28 13:54:33 simons`
50			`// Three more chains added for cpu debug access.`
51			`//`
52	63	simons	`// Revision 1.12 2002/05/07 14:44:52 mohor`
53			`// mon_cntl_o signals that controls monitor mux added.`
54			`//`
55	47	mohor	`// Revision 1.11 2002/03/12 14:32:26 mohor`
56			`// Few outputs for boundary scan chain added.`
57			`//`
58	38	mohor	`// Revision 1.10 2002/03/08 15:27:08 mohor`
59			`// Structure changed. Hooks for jtag chain added.`
60			`//`
61	36	mohor	`// Revision 1.9 2001/10/19 11:39:20 mohor`
62			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
63			`// few different cores in a single project.`
64			`//`
65	17	mohor	`// Revision 1.8 2001/10/17 10:39:17 mohor`
66			`// bs_chain_o added.`
67			`//`
68	15	mohor	`// Revision 1.7 2001/10/16 10:10:18 mohor`
69			`// Signal names changed to lowercase.`
70			`//`
71	13	mohor	`// Revision 1.6 2001/10/15 09:52:50 mohor`
72			`// Wishbone interface added, few fixes for better performance,`
73			`// hooks for boundary scan testing added.`
74			`//`
75	12	mohor	`// Revision 1.5 2001/09/24 14:06:12 mohor`
76			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
77			`//`
78	11	mohor	`// Revision 1.4 2001/09/20 10:10:29 mohor`
79			`// Working version. Few bugs fixed, comments added.`
80			`//`
81	9	mohor	`// Revision 1.3 2001/09/19 11:54:03 mohor`
82			`// Minor changes for simulation.`
83			`//`
84	6	mohor	`// Revision 1.2 2001/09/18 14:12:43 mohor`
85			`// Trace fixed. Some registers changed, trace simplified.`
86			`//`
87	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
88			`// Initial official release.`
89			`//`
90	2	mohor	`// Revision 1.3 2001/06/01 22:23:40 mohor`
91			`// This is a backup. It is not a fully working version. Not for use, yet.`
92			`//`
93			`// Revision 1.2 2001/05/18 13:10:05 mohor`
94			`// Headers changed. All additional information is now avaliable in the README.txt file.`
95			`//`
96			`// Revision 1.1.1.1 2001/05/18 06:35:15 mohor`
97			`// Initial release`
98			`//`
99			`//`
100
101
102	17	mohor	`include "timescale.v"
103	2	mohor	`include "dbg_defines.v"
104	80	mohor	`include "dbg_wb_defines.v"
105			//`include "dbg_tb_defines.v"
106	2	mohor
107			`// Test bench`
108			`module dbg_tb;`
109
110	80	mohor	`parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)`
111	2	mohor
112	80	mohor	`reg tms_pad_i;`
113			`reg tck_pad_i;`
114			`reg trst_pad_i;`
115			`reg tdi_pad_i;`
116			`wire tdo_pad_o;`
117			`wire tdo_padoe_o;`
118	2	mohor
119	80	mohor	`wire shift_dr_o;`
120			`wire pause_dr_o;`
121			`wire update_dr_o;`
122	2	mohor
123	80	mohor	`wire extest_select_o;`
124			`wire sample_preload_select_o;`
125			`wire mbist_select_o;`
126			`wire debug_select_o;`
127	2	mohor
128	80	mohor	`// WISHBONE common signals`
129			`reg wb_rst_i;`
130			`reg wb_clk_i;`
131
132			`// WISHBONE master interface`
133			`wire [31:0] wb_adr_o;`
134			`wire [31:0] wb_dat_o;`
135			`wire [31:0] wb_dat_i;`
136			`wire wb_cyc_o;`
137			`wire wb_stb_o;`
138			`wire [3:0] wb_sel_o;`
139			`wire wb_we_o;`
140			`wire wb_ack_i;`
141			`wire wb_cab_o;`
142			`wire wb_err_i;`
143			`wire [2:0] wb_cti_o;`
144			`wire [1:0] wb_bte_o;`
145	2	mohor
146
147
148	12	mohor
149
150	73	mohor
151	80	mohor	`wire tdo_o;`
152	12	mohor
153	80	mohor	`wire debug_tdi_i;`
154			`wire bs_chain_tdi_i;`
155			`wire mbist_tdi_i;`
156	73	mohor
157	80	mohor	`reg test_enabled;`
158	73	mohor
159	80	mohor	`reg [31:0] result;`
160	2	mohor
161	80	mohor	`wire tdo;`
162	73	mohor
163	80	mohor	`assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;`
164	73	mohor
165	80	mohor	`// Connecting TAP module`
166			`tap_top i_tap_top (`
167			`.tms_pad_i(tms_pad_i),`
168			`.tck_pad_i(tck_pad_i),`
169			`.trst_pad_i(!trst_pad_i),`
170			`.tdi_pad_i(tdi_pad_i),`
171			`.tdo_pad_o(tdo_pad_o),`
172			`.tdo_padoe_o(tdo_padoe_o),`
173	38	mohor
174	80	mohor	`// TAP states`
175			`.shift_dr_o(shift_dr_o),`
176			`.pause_dr_o(pause_dr_o),`
177			`.update_dr_o(update_dr_o),`
178	38	mohor
179	80	mohor	`// Select signals for boundary scan or mbist`
180			`.extest_select_o(extest_select_o),`
181			`.sample_preload_select_o(sample_preload_select_o),`
182			`.mbist_select_o(mbist_select_o),`
183			`.debug_select_o(debug_select_o),`
184	2	mohor
185	80	mohor	`// TDO signal that is connected to TDI of sub-modules.`
186			`.tdo_o(tdo_o),`
187	38	mohor
188	80	mohor	`// TDI signals from sub-modules`
189			`.debug_tdi_i(debug_tdi_i), // from debug module`
190			`.bs_chain_tdi_i(bs_chain_tdi_i), // from Boundary Scan Chain`
191			`.mbist_tdi_i(mbist_tdi_i) // from Mbist Chain`
192	73	mohor
193	38	mohor	`);`
194	2	mohor
195
196	80	mohor	`dbg_top i_dbg_top (`
197
198			`.trst_i(!trst_pad_i),`
199			`.tck_i(tck_pad_i),`
200			`.tdi_i(tdo_o),`
201			`.tdo_o(debug_tdi_i),`
202
203			`// TAP states`
204			`.shift_dr_i (shift_dr_o),`
205			`.pause_dr_i (pause_dr_o),`
206			`.update_dr_i (update_dr_o),`
207
208			`// Instructions`
209			`.debug_select_i(debug_select_o),`
210	12	mohor
211	80	mohor	`// WISHBONE common signals`
212			`.wb_rst_i (wb_rst_i),`
213			`.wb_clk_i (wb_clk_i),`
214
215			`// WISHBONE master interface`
216			`.wb_adr_o (wb_adr_o),`
217			`.wb_dat_o (wb_dat_o),`
218			`.wb_dat_i (wb_dat_i),`
219			`.wb_cyc_o (wb_cyc_o),`
220			`.wb_stb_o (wb_stb_o),`
221			`.wb_sel_o (wb_sel_o),`
222			`.wb_we_o (wb_we_o),`
223			`.wb_ack_i (wb_ack_i),`
224			`.wb_cab_o (wb_cab_o),`
225			`.wb_err_i (wb_err_i),`
226			`.wb_cti_o (wb_cti_o),`
227			`.wb_bte_o (wb_bte_o)`
228			`);`
229	12	mohor
230
231	80	mohor	`wb_slave_behavioral wb_slave`
232			`(`
233			`.CLK_I(wb_clk_i),`
234			`.RST_I(wb_rst_i),`
235			`.ACK_O(wb_ack_i),`
236			`.ADR_I(wb_adr_o),`
237			`.CYC_I(wb_cyc_o),`
238			`.DAT_O(wb_dat_i),`
239			`.DAT_I(wb_dat_o),`
240			`.ERR_O(wb_err_i),`
241			`.RTY_O(), // NOT USED for now!`
242			`.SEL_I(wb_sel_o),`
243			`.STB_I(wb_stb_o),`
244			`.WE_I (wb_we_o),`
245			`.CAB_I(1'b0)`
246			`);`
247	2	mohor
248
249	80	mohor	`// Initial values`
250	2	mohor	`initial`
251			`begin`
252	80	mohor	`test_enabled = 1'b0;`
253			`trst_pad_i = 1'b1;`
254			`tms_pad_i = 1'hz;`
255			`tck_pad_i = 1'hz;`
256			`tdi_pad_i = 1'hz;`
257
258			`#100;`
259			`trst_pad_i = 1'b0;`
260			`#100;`
261			`trst_pad_i = 1'b1;`
262			`#1 test_enabled<=#1 1'b1;`
263	2	mohor	`end`
264
265	80	mohor	`initial`
266			`begin`
267			`wb_rst_i = 1'b0;`
268			`#1000;`
269			`wb_rst_i = 1'b1;`
270			`#1000;`
271			`wb_rst_i = 1'b0;`
272	2	mohor
273	80	mohor	`// Initial values for wishbone slave model`
274			wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
275			`end`
276
277			`initial`
278	2	mohor	`begin`
279	80	mohor	`wb_clk_i = 1'b0;`
280			`forever #5 wb_clk_i = ~wb_clk_i;`
281	2	mohor	`end`
282
283	80	mohor	`always @ (posedge test_enabled)`
284			`begin`
285	2	mohor
286	80	mohor	`$display("//////////////////////////////////////////////////////////////////");`
287			`$display("// //");`
288			`$display("// (%0t) dbg_tb starting //", $time);`
289			`$display("// //");`
290			`$display("//////////////////////////////////////////////////////////////////");`
291	2	mohor
292	80	mohor	`initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000`
293	2	mohor
294	80	mohor	`reset_tap;`
295			`goto_run_test_idle;`
296	12	mohor
297	80	mohor	`// Testing read and write to internal registers`
298			`#10000;`
299			set_instruction(`IDCODE);
300			`read_id_code;`
301	12	mohor
302	80	mohor	set_instruction(`DEBUG);
303			`#10000;`
304	2	mohor
305	80	mohor	chain_select(`WISHBONE_SCAN_CHAIN, 32'hf2bcd929);
306	12	mohor
307	80	mohor	`// #10000;`
308			`// xxx(4'b1001, 32'he579b242);`
309	12	mohor
310	80	mohor	`#10000;`
311	2	mohor
312	80	mohor	// debug_wishbone(`WB_READ8, 32'h12345678, 32'h0, 16'h4, 32'h08359131, result); // {command, addr, data, length, crc, result}
313			// debug_wishbone(`WB_READ8, 32'h12345679, 32'h0, 16'h4, 32'hadfeabe2, result); // {command, addr, data, length, crc, result}
314			// debug_wishbone(`WB_READ8, 32'h1234567a, 32'h0, 16'h4, 32'hd8b08283, result); // {command, addr, data, length, crc, result}
315	2	mohor
316	80	mohor	// debug_wishbone(`WB_READ16, 32'h12345678, 32'h0, 16'h4, 32'haf07fce0, result); // {command, addr, data, length, crc, result}
317			// debug_wishbone(`WB_READ16, 32'h1234567a, 32'h0, 16'h4, 32'h7f82ef52, result); // {command, addr, data, length, crc, result}
318	2	mohor
319	80	mohor	debug_wishbone(`WB_READ32, 32'h12345678, 32'h0, 16'h4, 32'h969b4113, result); // {command, addr, data, length, crc, result}
320	2	mohor
321	80	mohor	// debug_wishbone(`WB_READ16, 32'h12345679, 32'h0, 16'h4, 32'h0accc633, result); // {command, addr, data, length, crc, result}
322	5	mohor
323	80	mohor	`#10000;`
324			`// xxx(4'b1001, 32'he579b242);`
325
326			wb_slave.cycle_response(`NO_RESPONSE, 8'h03, 8'h2); // (`NO_RESPONSE, wbs_waits, wbs_retries);
327			debug_wishbone_shift_dr(`WB_READ32, 32'h12345678, 32'h0, 16'h4, 32'h969b4113, result); // {command, addr, data, length, crc, result}
328			wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
329
330			`#10000;`
331			debug_wishbone_shift_dr(`WB_READ32, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result); // {command, addr, data, length, crc, result}
332
333			`#10000;`
334			debug_wishbone_shift_dr(`WB_READ32, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result); // {command, addr, data, length, crc, result}
335
336
337
338			`/*`
339			`// Testing read and write to CPU0 registers`
340			`#10000;`
341			set_instruction(`CHAIN_SELECT);
342			chain_select(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
343			set_instruction(`DEBUG);
344			`WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc}`
345
346			`ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}`
347			`ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}`
348			`*/`
349			`#5000 gen_clk(1); // One extra TCLK for debugging purposes`
350	5	mohor	`#1000 $stop;`
351	80	mohor
352	2	mohor	`end`
353
354	80	mohor
355			`task initialize_memory;`
356			`input [31:0] start_addr;`
357			`input [31:0] length;`
358			`integer i;`
359			`reg [31:0] addr;`
360			`begin`
361			`for (i=0; i<length; i=i+4)`
362			`begin`
363			`addr = start_addr + i;`
364			`wb_slave.wr_mem(addr, {addr[7:0], addr[15:8], addr[23:16], addr[31:24]}, 4'hf); // adr, data, sel`
365			`end`
366			`end`
367			`endtask`
368
369
370
371	2	mohor	`// Generation of the TCLK signal`
372	80	mohor	`task gen_clk;`
373			`input [7:0] num;`
374	2	mohor	`integer i;`
375			`begin`
376	80	mohor	`for(i=0; i<num; i=i+1)`
377	2	mohor	`begin`
378	80	mohor	`#TCLK tck_pad_i<=1;`
379			`#TCLK tck_pad_i<=0;`
380	2	mohor	`end`
381			`end`
382			`endtask`
383
384
385			`// TAP reset`
386	80	mohor	`task reset_tap;`
387	2	mohor	`begin`
388	80	mohor	`$display("(%0t) Task reset_tap", $time);`
389			`tms_pad_i<=#1 1'b1;`
390			`gen_clk(7);`
391	2	mohor	`end`
392			`endtask`
393
394
395			`// Goes to RunTestIdle state`
396	80	mohor	`task goto_run_test_idle;`
397	2	mohor	`begin`
398	80	mohor	`$display("(%0t) Task goto_run_test_idle", $time);`
399			`tms_pad_i<=#1 1'b0;`
400			`gen_clk(1);`
401	2	mohor	`end`
402			`endtask`
403
404
405			`// sets the instruction to the IR register and goes to the RunTestIdle state`
406	80	mohor	`task set_instruction;`
407			`input [3:0] instr;`
408	2	mohor	`integer i;`
409
410			`begin`
411	80	mohor	`$display("(%0t) Task set_instruction", $time);`
412			`tms_pad_i<=#1 1;`
413			`gen_clk(2);`
414			`tms_pad_i<=#1 0;`
415			`gen_clk(2); // we are in shiftIR`
416	2	mohor
417			for(i=0; i<`IR_LENGTH-1; i=i+1)
418			`begin`
419	80	mohor	`tdi_pad_i<=#1 instr[i];`
420			`gen_clk(1);`
421	2	mohor	`end`
422
423	80	mohor	`tdi_pad_i<=#1 instr[i]; // last shift`
424			`tms_pad_i<=#1 1; // going out of shiftIR`
425			`gen_clk(1);`
426			`tdi_pad_i<=#1 'hz; // tri-state`
427			`gen_clk(1);`
428			`tms_pad_i<=#1 0;`
429			`gen_clk(1); // we are in RunTestIdle`
430	2	mohor	`end`
431			`endtask`
432
433
434	80	mohor	`// Reads the ID code`
435			`task read_id_code;`
436			`begin`
437			`$display("(%0t) Task read_id_code", $time);`
438			`tms_pad_i<=#1 1;`
439			`gen_clk(1);`
440			`tms_pad_i<=#1 0;`
441			`gen_clk(2); // we are in shiftDR`
442
443			`tdi_pad_i<=#1 0;`
444			`gen_clk(31);`
445
446			`tms_pad_i<=#1 1; // going out of shiftIR`
447			`gen_clk(1);`
448
449			`tdi_pad_i<=#1 'hz; // tri-state`
450			`gen_clk(1);`
451			`tms_pad_i<=#1 0;`
452			`gen_clk(1); // we are in RunTestIdle`
453			`end`
454			`endtask`
455
456
457	2	mohor	`// sets the selected scan chain and goes to the RunTestIdle state`
458	80	mohor	`task chain_select;`
459			`input [3:0] data;`
460			`input [31:0] crc;`
461	2	mohor	`integer i;`
462
463			`begin`
464	80	mohor	`$display("(%0t) Task chain_select", $time);`
465			`tms_pad_i<=#1 1;`
466			`gen_clk(1);`
467			`tms_pad_i<=#1 0;`
468			`gen_clk(2); // we are in shiftDR`
469	2	mohor
470	80	mohor	`tdi_pad_i<=#1 1'b1; // chain_select bit`
471			`gen_clk(1);`
472
473	2	mohor	for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
474			`begin`
475	80	mohor	`tdi_pad_i<=#1 data[i];`
476			`gen_clk(1);`
477	2	mohor	`end`
478
479	80	mohor	for(i=0; i<`CRC_LEN; i=i+1)
480	2	mohor	`begin`
481	80	mohor	tdi_pad_i<=#1 crc[`CRC_LEN -1-i];
482			`gen_clk(1);`
483	2	mohor	`end`
484
485	80	mohor	gen_clk(`STATUS_LEN); // Generating 5 clocks to read out status.
486
487
488			for(i=0; i<`CRC_LEN -1; i=i+1)
489			`begin`
490			`tdi_pad_i<=#1 1'b0;`
491			`gen_clk(1);`
492			`end`
493
494			`tdi_pad_i<=#1 crc[i]; // last crc`
495			`tms_pad_i<=#1 1;`
496			`gen_clk(1); // to exit1_dr`
497
498			`tdi_pad_i<=#1 'hz; // tri-state`
499			`tms_pad_i<=#1 1;`
500			`gen_clk(1); // to update_dr`

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