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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_tb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.22  2004/01/13 11:28:30  mohor
// tmp version.
//
// Revision 1.21  2004/01/10 07:50:41  mohor
// temp version.
//
// Revision 1.20  2004/01/09 12:49:23  mohor
// tmp version.
//
// Revision 1.19  2004/01/08 17:53:12  mohor
// tmp version.
//
// Revision 1.18  2004/01/07 11:59:48  mohor
// temp4 version.
//
// Revision 1.17  2004/01/06 17:14:59  mohor
// temp3 version.
//
// Revision 1.16  2004/01/05 12:16:50  mohor
// tmp2 version.
//
// Revision 1.15  2003/12/23 14:26:01  mohor
// New version of the debug interface. Not finished, yet.
//
// Revision 1.14  2003/10/23 16:16:30  mohor
// CRC logic changed.
//
// Revision 1.13  2003/08/28 13:54:33  simons
// Three more chains added for cpu debug access.
//
// Revision 1.12  2002/05/07 14:44:52  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.11  2002/03/12 14:32:26  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.10  2002/03/08 15:27:08  mohor
// Structure changed. Hooks for jtag chain added.
//
// Revision 1.9  2001/10/19 11:39:20  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8  2001/10/17 10:39:17  mohor
// bs_chain_o added.
//
// Revision 1.7  2001/10/16 10:10:18  mohor
// Signal names changed to lowercase.
//
// Revision 1.6  2001/10/15 09:52:50  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5  2001/09/24 14:06:12  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4  2001/09/20 10:10:29  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:54:03  mohor
// Minor changes for simulation.
//
// Revision 1.2  2001/09/18 14:12:43  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:23:40  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:05  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:15  mohor
// Initial release
//
//
 
 
`include "timescale.v"
`include "dbg_defines.v"
`include "dbg_wb_defines.v"
//`include "dbg_tb_defines.v"
 
// Test bench
module dbg_tb;
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
reg   tms_pad_i;
reg   tck_pad_i;
reg   trst_pad_i;
reg   tdi_pad_i;
wire  tdo_pad_o;
wire  tdo_padoe_o;
 
wire  shift_dr_o;
wire  pause_dr_o;
wire  update_dr_o;
 
wire  extest_select_o;
wire  sample_preload_select_o;
wire  mbist_select_o;
wire  debug_select_o;
 
// WISHBONE common signals
reg   wb_rst_i;
reg   wb_clk_i;
 
// WISHBONE master interface
wire [31:0] wb_adr_o;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
wire        wb_cyc_o;
wire        wb_stb_o;
wire  [3:0] wb_sel_o;
wire        wb_we_o;
wire        wb_ack_i;
wire        wb_cab_o;
wire        wb_err_i;
wire  [2:0] wb_cti_o;
wire  [1:0] wb_bte_o;
 
// Text used for easier debugging
reg  [99:0] test_text;
reg   [2:0] last_wb_cmd;
reg  [99:0] last_wb_cmd_text;
reg  [31:0] wb_data;
 
 
 
wire  tdo_o;
 
wire  debug_tdi_i;
wire  bs_chain_tdi_i;
wire  mbist_tdi_i;
 
reg   test_enabled;
 
reg [31:0] result;
 
reg [31:0] tmp_crc;
reg [31:0] shifted_in_crc;
 
wire tdo;
 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
 
// Connecting TAP module
tap_top i_tap_top (
                    .tms_pad_i(tms_pad_i),
                    .tck_pad_i(tck_pad_i),
                    .trst_pad_i(!trst_pad_i),
                    .tdi_pad_i(tdi_pad_i),
                    .tdo_pad_o(tdo_pad_o),
                    .tdo_padoe_o(tdo_padoe_o),
 
                    // TAP states
                    .shift_dr_o(shift_dr_o),
                    .pause_dr_o(pause_dr_o),
                    .update_dr_o(update_dr_o),
 
                    // Select signals for boundary scan or mbist
                    .extest_select_o(extest_select_o),
                    .sample_preload_select_o(sample_preload_select_o),
                    .mbist_select_o(mbist_select_o),
                    .debug_select_o(debug_select_o),
 
                    // TDO signal that is connected to TDI of sub-modules.
                    .tdo_o(tdo_o),
 
                    // TDI signals from sub-modules
                    .debug_tdi_i(debug_tdi_i),        // from debug module
                    .bs_chain_tdi_i(bs_chain_tdi_i),  // from Boundary Scan Chain
                    .mbist_tdi_i(mbist_tdi_i)         // from Mbist Chain
 
               );
 
 
dbg_top i_dbg_top  (
                    .tck_i(tck_pad_i),
                    .tdi_i(tdo_o),
                    .tdo_o(debug_tdi_i),
 
                    // TAP states
                    .shift_dr_i   (shift_dr_o),
                    .pause_dr_i   (pause_dr_o),
                    .update_dr_i  (update_dr_o),
 
                    // Instructions
                    .debug_select_i(debug_select_o),
 
                    // WISHBONE common signals
                    .wb_rst_i      (wb_rst_i),
                    .wb_clk_i      (wb_clk_i),
 
                    // WISHBONE master interface
                    .wb_adr_o      (wb_adr_o),
                    .wb_dat_o      (wb_dat_o),
                    .wb_dat_i      (wb_dat_i),
                    .wb_cyc_o      (wb_cyc_o),
                    .wb_stb_o      (wb_stb_o),
                    .wb_sel_o      (wb_sel_o),
                    .wb_we_o       (wb_we_o),
                    .wb_ack_i      (wb_ack_i),
                    .wb_cab_o      (wb_cab_o),
                    .wb_err_i      (wb_err_i),
                    .wb_cti_o      (wb_cti_o),
                    .wb_bte_o      (wb_bte_o)
                   );
 
 
wb_slave_behavioral wb_slave
                   (
                    .CLK_I(wb_clk_i),
                    .RST_I(wb_rst_i),
                    .ACK_O(wb_ack_i),
                    .ADR_I(wb_adr_o),
                    .CYC_I(wb_cyc_o),
                    .DAT_O(wb_dat_i),
                    .DAT_I(wb_dat_o),
                    .ERR_O(wb_err_i),
                    .RTY_O(),      // NOT USED for now!
                    .SEL_I(wb_sel_o),
                    .STB_I(wb_stb_o),
                    .WE_I (wb_we_o),
                    .CAB_I(1'b0)
                   );
 
 
// Initial values
initial
begin
  test_enabled = 1'b0;
  wb_data = 32'h01234567;
  trst_pad_i = 1'b1;
  tms_pad_i = 1'hz;
  tck_pad_i = 1'hz;
  tdi_pad_i = 1'hz;
 
  #100;
  trst_pad_i = 1'b0;
  #100;
  trst_pad_i = 1'b1;
  #1 test_enabled<=#1 1'b1;
end
 
initial
begin
  wb_rst_i = 1'b0;
  #1000;
  wb_rst_i = 1'b1;
  #1000;
  wb_rst_i = 1'b0;
 
  // Initial values for wishbone slave model
  wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
end
 
initial
begin
  wb_clk_i = 1'b0;
  forever #5 wb_clk_i = ~wb_clk_i;
end
 
always @ (posedge test_enabled)
begin
 
  $display("//////////////////////////////////////////////////////////////////");
  $display("//                                                              //");
  $display("//  (%0t) dbg_tb starting                                     //", $time);
  $display("//                                                              //");
  $display("//////////////////////////////////////////////////////////////////");
 
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
 
  reset_tap;
 
  #500;
  goto_run_test_idle;
 
  // Testing read and write to internal registers
  #10000;
  set_instruction(`IDCODE);
  read_id_code;
 
  set_instruction(`DEBUG);
  #10000;
 
  chain_select(`WISHBONE_SCAN_CHAIN, 32'hf2bcd929);
 
//  #10000;
//  xxx(4'b1001, 32'he579b242);
 
  #10000;
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 32'h57ecda62, result, "abc 1"); // {command, ready, addr, length, crc, result, text}
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 32'h563476e5, result, "abc 2"); // {command, ready, addr, length, crc, result, text}
//  debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 32'h545d836c, result, "abc 3"); // {command, ready, addr, length, crc, result, text}
//
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 32'h86156251, result, "abc 4"); // {command, ready, addr, length, crc, result, text}
//  debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 32'h85a43b5f, result, "abc 5"); // {command, ready, addr, length, crc, result, text}
//
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 32'hc9420a40, result, "read32 1"); // {command, ready, addr, length, crc, result, text}
//
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 32'h87cdced6, result, "abc 6"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
//  xxx(4'b1001, 32'he579b242);
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 32'hc9420a40, result, "read32 2"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "read32 3"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  wb_slave.cycle_response(`ERR_RESPONSE, 8'h03, 8'h2);   // (`ERR_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "read32 4"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 1"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 2"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  wb_slave.cycle_response(`ACK_RESPONSE, 8'h0a, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "read32 5"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "wr32 len8"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 32'hed029606, result, "wr16 len8"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 32'h359e2d2a, result, "wr8 len8"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'h5e9dd377, result, "go 1"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 32'h8bbeb90d, result, "read32 6"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 32'hcedab37c, result, "read16 7"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 32'hbe993245, result, "read8 8"); // {command, ready, addr, length, crc, result, text}
 
  #10000;
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'hd4b43491, result, "go 2"); // {command, ready, addr, length, crc, result, text}
 
 
 
 
/*
  // Testing read and write to CPU0 registers
  #10000;
  set_instruction(`CHAIN_SELECT);
  chain_select(`CPU_DEBUG_CHAIN_0, 8'h12);  // {chain, crc}
  set_instruction(`DEBUG);
  WriteCPURegister(32'h11001100, 32'h00110011, 8'h86);  // {data, addr, crc}
 
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
*/
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
  $display("\n\nSimulation end.");
  #1000 $stop;
 
end
 
 
task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin
    for (i=0; i<length; i=i+4)
      begin
        addr = start_addr + i;
        wb_slave.wr_mem(addr, {addr[7:0], addr[15:8], addr[23:16], addr[31:24]}, 4'hf);    // adr, data, sel
      end
  end
endtask
 
 
 
// Generation of the TCLK signal
task gen_clk;
  input [7:0] num;
  integer i;
  begin
    for(i=0; i<num; i=i+1)
      begin
        #TCLK tck_pad_i<=1;
        #TCLK tck_pad_i<=0;
      end
  end
endtask
 
 
// TAP reset
task reset_tap;
  begin
    $display("(%0t) Task reset_tap", $time);
    tms_pad_i<=#1 1'b1;
    gen_clk(5);
  end
endtask
 
 
// Goes to RunTestIdle state
task goto_run_test_idle;
  begin
    $display("(%0t) Task goto_run_test_idle", $time);
    tms_pad_i<=#1 1'b0;
    gen_clk(1);
  end
endtask
 
 
// sets the instruction to the IR register and goes to the RunTestIdle state
task set_instruction;
  input [3:0] instr;
  integer i;
 
  begin
    $display("(%0t) Task set_instruction", $time);
    tms_pad_i<=#1 1;
    gen_clk(2);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftIR
 
    for(i=0; i<`IR_LENGTH-1; i=i+1)
    begin
      tdi_pad_i<=#1 instr[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 instr[i]; // last shift
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
    tdi_pad_i<=#1 'hz;    // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Reads the ID code
task read_id_code;
  begin
    $display("(%0t) Task read_id_code", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 0;
    gen_clk(31);
 
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
 
    tdi_pad_i<=#1 'hz; // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task chain_select;
  input [3:0]  data;
  input [31:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task chain_select", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b1; // chain_select bit
    gen_clk(1);
 
    for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN -1-i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
 
 
 
 
 
task debug_wishbone;
  input [2:0]   command;
  input         ready;
  input [31:0]  addr;
  input [15:0]  length;
  input [31:0]  crc;
  output [31:0] result;
  input [99:0]  text;
  integer i;
 
  begin
   $write("(%0t) Task debug_wishbone: ", $time);
 
    test_text = text;
    shifted_in_crc = crc;
 
    case (command)
      `WB_STATUS   :
        begin
          $display("wb_status (crc=0x%0x (%0s))", crc, text);
          debug_wishbone_status(command, crc);
          last_wb_cmd = `WB_STATUS;  last_wb_cmd_text = "WB_STATUS";
        end
      `WB_READ8    :
        begin
          $display("wb_read8 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
          debug_wishbone_set_addr(command, ready, addr, length, crc);
          last_wb_cmd = `WB_READ8;  last_wb_cmd_text = "WB_READ8";
        end
      `WB_READ16   :
        begin
          $display("wb_read16 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
          debug_wishbone_set_addr(command, ready, addr, length, crc);
          last_wb_cmd = `WB_READ16;  last_wb_cmd_text = "WB_READ16";
        end
      `WB_READ32   :
        begin
          $display("wb_read32 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
          debug_wishbone_set_addr(command, ready, addr, length, crc);
          last_wb_cmd = `WB_READ32;  last_wb_cmd_text = "WB_READ32";
        end
      `WB_WRITE8   :
        begin
          $display("wb_write8 (adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, length, crc, text);
          debug_wishbone_set_addr(command, ready, addr, length, crc);
          last_wb_cmd = `WB_WRITE8;  last_wb_cmd_text = "WB_WRITE8";
        end
      `WB_WRITE16  :
        begin
          $display("wb_write16 (adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, length, crc, text);
          debug_wishbone_set_addr(command, ready, addr, length, crc);
          last_wb_cmd = `WB_WRITE16;  last_wb_cmd_text = "WB_WRITE16";
        end
      `WB_WRITE32  :
        begin
          $display("wb_write32 (adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, length, crc, text);
          debug_wishbone_set_addr(command, ready, addr, length, crc);
          last_wb_cmd = `WB_WRITE32;  last_wb_cmd_text = "WB_WRITE32";
        end
      `WB_GO       :
        begin
          $display("wb_go, crc=0x%0x (%0s))", crc, text);
          debug_wishbone_go(command, crc);
//          $display("wb_go_tmp, crc=0x%0x (%0s))", crc, text);
//          debug_wishbone_go_tmp(command, crc);
          last_wb_cmd = `WB_GO;  last_wb_cmd_text = "WB_GO";
        end
    endcase
  end
endtask       // debug_wishbone
 
 
 
 
 
 
task debug_wishbone_set_addr;
  input [2:0]   command;
  input         wait_for_wb_ready;
  input [31:0]  addr;
  input [15:0]  length;
  input [31:0]  crc;
  integer i;
 
  begin
    $display("(%0t) Task debug_wishbone_set_addr: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      gen_clk(1);
    end
 
    for(i=15; i>=0; i=i-1)       // length
    begin
      tdi_pad_i<=#1 length[i];
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 crc[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 'hz;
    if (wait_for_wb_ready)
      begin
        gen_clk(`STATUS_LEN -1);   // Generating 4 clocks to read out status. Going to pause_dr at the end
        tms_pad_i<=#1 1;
        gen_clk(1);       // to exit1_dr
        tms_pad_i<=#1 0;
        gen_clk(1);       // to pause_dr
 
        while (dbg_tb.tdo_pad_o)     // waiting for wb to send "ready" 
        begin
          gen_clk(1);       // staying in pause_dr
        end
 
        tms_pad_i<=#1 1;
        gen_clk(1);       // to exit2_dr
        tms_pad_i<=#1 0;
        gen_clk(1);       // to shift_dr
      end
    else
      gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_set_addr
 
 
 
 
 
task debug_wishbone_status;
  input [2:0]   command;
  input [31:0]  crc;
  integer i;
 
  begin
    $display("(%0t) Task debug_wishbone_status: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)      // crc
    begin
      tdi_pad_i<=#1 crc[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_status
 
 
 
 
task debug_wishbone_go;
  input [2:0]   command;
  input [31:0]  crc;
  integer i;
  reg   [4:0]   pointer;
 
  begin
    $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
 
    if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
          begin
            if (!(i%32))
              begin
                wb_data = wb_data + 32'h11111111;
                $display("\t\twb_data = 0x%x", wb_data);
              end
            pointer = 31-i[4:0];
            tdi_pad_i<=#1 wb_data[pointer];
            gen_clk(1);
 
          end
      end
 
 
    for(i=31; i>=0; i=i-1)      // crc
    begin
      tdi_pad_i<=#1 crc[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
 
 
 
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
          gen_clk(1);
      end
 
 
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_go
 
 
 
 
 
task debug_wishbone_go_tmp;
  input [2:0]   command;
  input [31:0]  crc;
  integer i;
  reg   [4:0]   pointer;
 
  begin
    $display("(%0t) Task debug_wishbone_go_tmp (previous command was %0s): ", $time, last_wb_cmd_text);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
 
    if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
          begin
            if (!(i%32))
              begin
                wb_data = wb_data + 32'h11111111;
                $display("\t\twb_data = 0x%x", wb_data);
              end
            pointer = 31-i[4:0];
            tdi_pad_i<=#1 wb_data[pointer];
            gen_clk(1);
 
          end
      end
 
 
    for(i=31; i>=0; i=i-1)      // crc
    begin
      tdi_pad_i<=#1 crc[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
 
 
 
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.len << 3, dbg_tb.i_dbg_top.i_dbg_wb.len);
        $display("\t\tFirst half");
//        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
 
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3)/2; i=i+1)
          begin
          gen_clk(1);
          end
 
        tms_pad_i<=#1 1;
        gen_clk(1);         // to exit1_dr
        tms_pad_i<=#1 0;
        gen_clk(1);         // to pause_dr
        gen_clk(1000);      // wait in pause_dr
        tms_pad_i<=#1 1;
        gen_clk(1);         // to exit2_dr
        tms_pad_i<=#1 0;    // to shift_dr
        gen_clk(1);
 
        $display("\t\tSecond half");
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3)/2; i=i+1)
          begin
          gen_clk(1);
          end
 
      end
 
 
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_go_tmp
 
 
 
 
 
 
 
 
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Printing the information to the screen                                        *
*                                                                                 *
**********************************************************************************/
 
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.update_ir)
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
      `EXTEST         : $display("\tInstruction EXTEST entered");
      `SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
      `IDCODE         : $display("\tInstruction IDCODE entered");
      `MBIST          : $display("\tInstruction MBIST entered");
      `DEBUG          : $display("\tInstruction DEBUG entered");
      `BYPASS         : $display("\tInstruction BYPASS entered");
                default           :     $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
    endcase
end
 
 
 
// Print shifted IDCode
reg [31:0] tmp_data;
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.idcode_select)
    begin
      if(dbg_tb.i_tap_top.shift_dr)
        tmp_data[31:0]<=#1 {dbg_tb.tdo, tmp_data[31:1]};
      else
      if(dbg_tb.i_tap_top.update_dr)
        if (tmp_data[31:0] != `IDCODE_VALUE)
          begin
            $display("(%0t) ERROR: IDCODE not correct", $time);
            $stop;
          end
        else
          $display("\t\tIDCode = 0x%h", tmp_data[31:0]);
    end
end
 
 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
    begin
      $display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
      $display("(%0t) Simulation stopped !!!", $time);
      $stop;
    end
end
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task xxx;
  input [3:0]  data;
  input [31:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task xxx", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<4; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN - 1 - i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
// Printing CRC
//always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end)
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or posedge dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end)
begin
  #2;
  if (dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end & dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end)
    tmp_crc = dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc;
end
 
 
// Detecting CRC error
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end)
begin
  #2;
  if (~dbg_tb.i_dbg_top.crc_match)
    begin
      $display("\t\tCRC ERROR !!!");
      $display("\t\tCRC needed (%0s) = 0x%0x , shifted_in = 0x%0x", test_text, tmp_crc, shifted_in_crc);
      $stop;
    end
end
 
 
 
// Detecting errors in counters
always @ (dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt or
          dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end or
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt or
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end or
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt or
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or
          dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt2 or
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt3 or
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt4
          // dbg_tb.i_dbg_top.i_dbg_wb. or
         )
begin
  if ((~dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end) & (
                                                  dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en |
                                                  dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en     |
                                                  dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en      |
                                                  dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
                                                 )
     )
    begin
      $display("\n\n\t\t(%0t) ERROR in counters !!!", $time);
      #10000;
      $stop;
    end
 
 
 
end
 
 
 
 
 
 
endmodule // dbg_tb
 
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_tb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7	36	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	80	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	80	mohor	`//// Copyright (C) 2000 - 2003 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	95	mohor	`// Revision 1.22 2004/01/13 11:28:30 mohor`
47			`// tmp version.`
48			`//`
49	93	mohor	`// Revision 1.21 2004/01/10 07:50:41 mohor`
50			`// temp version.`
51			`//`
52	92	mohor	`// Revision 1.20 2004/01/09 12:49:23 mohor`
53			`// tmp version.`
54			`//`
55	91	mohor	`// Revision 1.19 2004/01/08 17:53:12 mohor`
56			`// tmp version.`
57			`//`
58	90	mohor	`// Revision 1.18 2004/01/07 11:59:48 mohor`
59			`// temp4 version.`
60			`//`
61	89	mohor	`// Revision 1.17 2004/01/06 17:14:59 mohor`
62			`// temp3 version.`
63			`//`
64	88	mohor	`// Revision 1.16 2004/01/05 12:16:50 mohor`
65			`// tmp2 version.`
66			`//`
67	87	mohor	`// Revision 1.15 2003/12/23 14:26:01 mohor`
68			`// New version of the debug interface. Not finished, yet.`
69			`//`
70	80	mohor	`// Revision 1.14 2003/10/23 16:16:30 mohor`
71			`// CRC logic changed.`
72			`//`
73	73	mohor	`// Revision 1.13 2003/08/28 13:54:33 simons`
74			`// Three more chains added for cpu debug access.`
75			`//`
76	63	simons	`// Revision 1.12 2002/05/07 14:44:52 mohor`
77			`// mon_cntl_o signals that controls monitor mux added.`
78			`//`
79	47	mohor	`// Revision 1.11 2002/03/12 14:32:26 mohor`
80			`// Few outputs for boundary scan chain added.`
81			`//`
82	38	mohor	`// Revision 1.10 2002/03/08 15:27:08 mohor`
83			`// Structure changed. Hooks for jtag chain added.`
84			`//`
85	36	mohor	`// Revision 1.9 2001/10/19 11:39:20 mohor`
86			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
87			`// few different cores in a single project.`
88			`//`
89	17	mohor	`// Revision 1.8 2001/10/17 10:39:17 mohor`
90			`// bs_chain_o added.`
91			`//`
92	15	mohor	`// Revision 1.7 2001/10/16 10:10:18 mohor`
93			`// Signal names changed to lowercase.`
94			`//`
95	13	mohor	`// Revision 1.6 2001/10/15 09:52:50 mohor`
96			`// Wishbone interface added, few fixes for better performance,`
97			`// hooks for boundary scan testing added.`
98			`//`
99	12	mohor	`// Revision 1.5 2001/09/24 14:06:12 mohor`
100			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
101			`//`
102	11	mohor	`// Revision 1.4 2001/09/20 10:10:29 mohor`
103			`// Working version. Few bugs fixed, comments added.`
104			`//`
105	9	mohor	`// Revision 1.3 2001/09/19 11:54:03 mohor`
106			`// Minor changes for simulation.`
107			`//`
108	6	mohor	`// Revision 1.2 2001/09/18 14:12:43 mohor`
109			`// Trace fixed. Some registers changed, trace simplified.`
110			`//`
111	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
112			`// Initial official release.`
113			`//`
114	2	mohor	`// Revision 1.3 2001/06/01 22:23:40 mohor`
115			`// This is a backup. It is not a fully working version. Not for use, yet.`
116			`//`
117			`// Revision 1.2 2001/05/18 13:10:05 mohor`
118			`// Headers changed. All additional information is now avaliable in the README.txt file.`
119			`//`
120			`// Revision 1.1.1.1 2001/05/18 06:35:15 mohor`
121			`// Initial release`
122			`//`
123			`//`
124
125
126	17	mohor	`include "timescale.v"
127	2	mohor	`include "dbg_defines.v"
128	80	mohor	`include "dbg_wb_defines.v"
129			//`include "dbg_tb_defines.v"
130	2	mohor
131			`// Test bench`
132			`module dbg_tb;`
133
134	80	mohor	`parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)`
135	2	mohor
136	80	mohor	`reg tms_pad_i;`
137			`reg tck_pad_i;`
138			`reg trst_pad_i;`
139			`reg tdi_pad_i;`
140			`wire tdo_pad_o;`
141			`wire tdo_padoe_o;`
142	2	mohor
143	80	mohor	`wire shift_dr_o;`
144			`wire pause_dr_o;`
145			`wire update_dr_o;`
146	2	mohor
147	80	mohor	`wire extest_select_o;`
148			`wire sample_preload_select_o;`
149			`wire mbist_select_o;`
150			`wire debug_select_o;`
151	2	mohor
152	80	mohor	`// WISHBONE common signals`
153			`reg wb_rst_i;`
154			`reg wb_clk_i;`
155
156			`// WISHBONE master interface`
157			`wire [31:0] wb_adr_o;`
158			`wire [31:0] wb_dat_o;`
159			`wire [31:0] wb_dat_i;`
160			`wire wb_cyc_o;`
161			`wire wb_stb_o;`
162			`wire [3:0] wb_sel_o;`
163			`wire wb_we_o;`
164			`wire wb_ack_i;`
165			`wire wb_cab_o;`
166			`wire wb_err_i;`
167			`wire [2:0] wb_cti_o;`
168			`wire [1:0] wb_bte_o;`
169	2	mohor
170	87	mohor	`// Text used for easier debugging`
171			`reg [99:0] test_text;`
172	88	mohor	`reg [2:0] last_wb_cmd;`
173			`reg [99:0] last_wb_cmd_text;`
174			`reg [31:0] wb_data;`
175	2	mohor
176
177	12	mohor
178	80	mohor	`wire tdo_o;`
179	12	mohor
180	80	mohor	`wire debug_tdi_i;`
181			`wire bs_chain_tdi_i;`
182			`wire mbist_tdi_i;`
183	73	mohor
184	80	mohor	`reg test_enabled;`
185	73	mohor
186	80	mohor	`reg [31:0] result;`
187	2	mohor
188	88	mohor	`reg [31:0] tmp_crc;`
189			`reg [31:0] shifted_in_crc;`
190
191	80	mohor	`wire tdo;`
192	73	mohor
193	80	mohor	`assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;`
194	73	mohor
195	80	mohor	`// Connecting TAP module`
196			`tap_top i_tap_top (`
197			`.tms_pad_i(tms_pad_i),`
198			`.tck_pad_i(tck_pad_i),`
199			`.trst_pad_i(!trst_pad_i),`
200			`.tdi_pad_i(tdi_pad_i),`
201			`.tdo_pad_o(tdo_pad_o),`
202			`.tdo_padoe_o(tdo_padoe_o),`
203	38	mohor
204	80	mohor	`// TAP states`
205			`.shift_dr_o(shift_dr_o),`
206			`.pause_dr_o(pause_dr_o),`
207			`.update_dr_o(update_dr_o),`
208	38	mohor
209	80	mohor	`// Select signals for boundary scan or mbist`
210			`.extest_select_o(extest_select_o),`
211			`.sample_preload_select_o(sample_preload_select_o),`
212			`.mbist_select_o(mbist_select_o),`
213			`.debug_select_o(debug_select_o),`
214	2	mohor
215	80	mohor	`// TDO signal that is connected to TDI of sub-modules.`
216			`.tdo_o(tdo_o),`
217	38	mohor
218	80	mohor	`// TDI signals from sub-modules`
219			`.debug_tdi_i(debug_tdi_i), // from debug module`
220			`.bs_chain_tdi_i(bs_chain_tdi_i), // from Boundary Scan Chain`
221			`.mbist_tdi_i(mbist_tdi_i) // from Mbist Chain`
222	73	mohor
223	38	mohor	`);`
224	2	mohor
225
226	80	mohor	`dbg_top i_dbg_top (`
227			`.tck_i(tck_pad_i),`
228			`.tdi_i(tdo_o),`
229			`.tdo_o(debug_tdi_i),`
230
231			`// TAP states`
232			`.shift_dr_i (shift_dr_o),`
233			`.pause_dr_i (pause_dr_o),`
234			`.update_dr_i (update_dr_o),`
235
236			`// Instructions`
237			`.debug_select_i(debug_select_o),`
238	12	mohor
239	80	mohor	`// WISHBONE common signals`
240			`.wb_rst_i (wb_rst_i),`
241			`.wb_clk_i (wb_clk_i),`
242
243			`// WISHBONE master interface`
244			`.wb_adr_o (wb_adr_o),`
245			`.wb_dat_o (wb_dat_o),`
246			`.wb_dat_i (wb_dat_i),`
247			`.wb_cyc_o (wb_cyc_o),`
248			`.wb_stb_o (wb_stb_o),`
249			`.wb_sel_o (wb_sel_o),`
250			`.wb_we_o (wb_we_o),`
251			`.wb_ack_i (wb_ack_i),`
252			`.wb_cab_o (wb_cab_o),`
253			`.wb_err_i (wb_err_i),`
254			`.wb_cti_o (wb_cti_o),`
255			`.wb_bte_o (wb_bte_o)`
256			`);`
257	12	mohor
258
259	80	mohor	`wb_slave_behavioral wb_slave`
260			`(`
261			`.CLK_I(wb_clk_i),`
262			`.RST_I(wb_rst_i),`
263			`.ACK_O(wb_ack_i),`
264			`.ADR_I(wb_adr_o),`
265			`.CYC_I(wb_cyc_o),`
266			`.DAT_O(wb_dat_i),`
267			`.DAT_I(wb_dat_o),`
268			`.ERR_O(wb_err_i),`
269			`.RTY_O(), // NOT USED for now!`
270			`.SEL_I(wb_sel_o),`
271			`.STB_I(wb_stb_o),`
272			`.WE_I (wb_we_o),`
273			`.CAB_I(1'b0)`
274			`);`
275	2	mohor
276
277	80	mohor	`// Initial values`
278	2	mohor	`initial`
279			`begin`
280	80	mohor	`test_enabled = 1'b0;`
281	88	mohor	`wb_data = 32'h01234567;`
282	80	mohor	`trst_pad_i = 1'b1;`
283			`tms_pad_i = 1'hz;`
284			`tck_pad_i = 1'hz;`
285			`tdi_pad_i = 1'hz;`
286
287			`#100;`
288			`trst_pad_i = 1'b0;`
289			`#100;`
290			`trst_pad_i = 1'b1;`
291			`#1 test_enabled<=#1 1'b1;`
292	2	mohor	`end`
293
294	80	mohor	`initial`
295			`begin`
296			`wb_rst_i = 1'b0;`
297			`#1000;`
298			`wb_rst_i = 1'b1;`
299			`#1000;`
300			`wb_rst_i = 1'b0;`
301	2	mohor
302	80	mohor	`// Initial values for wishbone slave model`
303			wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
304			`end`
305
306			`initial`
307	2	mohor	`begin`
308	80	mohor	`wb_clk_i = 1'b0;`
309			`forever #5 wb_clk_i = ~wb_clk_i;`
310	2	mohor	`end`
311
312	80	mohor	`always @ (posedge test_enabled)`
313			`begin`
314	2	mohor
315	80	mohor	`$display("//////////////////////////////////////////////////////////////////");`
316			`$display("// //");`
317			`$display("// (%0t) dbg_tb starting //", $time);`
318			`$display("// //");`
319			`$display("//////////////////////////////////////////////////////////////////");`
320	2	mohor
321	80	mohor	`initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000`
322	2	mohor
323	80	mohor	`reset_tap;`
324	95	mohor
325			`#500;`
326	80	mohor	`goto_run_test_idle;`
327	12	mohor
328	80	mohor	`// Testing read and write to internal registers`
329			`#10000;`
330			set_instruction(`IDCODE);
331			`read_id_code;`
332	12	mohor
333	80	mohor	set_instruction(`DEBUG);
334			`#10000;`
335	2	mohor
336	80	mohor	chain_select(`WISHBONE_SCAN_CHAIN, 32'hf2bcd929);
337	12	mohor
338	80	mohor	`// #10000;`
339			`// xxx(4'b1001, 32'he579b242);`
340	12	mohor
341	80	mohor	`#10000;`
342	2	mohor
343	88	mohor	// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 32'h57ecda62, result, "abc 1"); // {command, ready, addr, length, crc, result, text}
344			// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 32'h563476e5, result, "abc 2"); // {command, ready, addr, length, crc, result, text}
345			// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 32'h545d836c, result, "abc 3"); // {command, ready, addr, length, crc, result, text}
346			`//`
347			// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 32'h86156251, result, "abc 4"); // {command, ready, addr, length, crc, result, text}
348			// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 32'h85a43b5f, result, "abc 5"); // {command, ready, addr, length, crc, result, text}
349			`//`
350	90	mohor	debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 32'hc9420a40, result, "read32 1"); // {command, ready, addr, length, crc, result, text}
351	88	mohor	`//`
352			// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 32'h87cdced6, result, "abc 6"); // {command, ready, addr, length, crc, result, text}
353	2	mohor
354	80	mohor	`#10000;`
355			`// xxx(4'b1001, 32'he579b242);`
356
357	90	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 32'hc9420a40, result, "read32 2"); // {command, ready, addr, length, crc, result, text}
358	87	mohor
359			`#10000;`
360	80	mohor	wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
361	90	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "read32 3"); // {command, ready, addr, length, crc, result, text}
362	80	mohor
363			`#10000;`
364	88	mohor	wb_slave.cycle_response(`ERR_RESPONSE, 8'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries);
365	90	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "read32 4"); // {command, ready, addr, length, crc, result, text}
366	80	mohor
367			`#10000;`
368	88	mohor	debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 1"); // {command, ready, addr, length, crc, result, text}
369	80	mohor
370	87	mohor	`#10000;`
371	88	mohor	debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 2"); // {command, ready, addr, length, crc, result, text}
372	80	mohor
373	87	mohor	`#10000;`
374	92	mohor	wb_slave.cycle_response(`ACK_RESPONSE, 8'h0a, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
375	90	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "read32 5"); // {command, ready, addr, length, crc, result, text}
376	80	mohor
377	87	mohor	`#10000;`
378	90	mohor	debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "wr32 len8"); // {command, ready, addr, length, crc, result, text}
379	87	mohor
380			`#10000;`
381	90	mohor	debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 32'hed029606, result, "wr16 len8"); // {command, ready, addr, length, crc, result, text}
382	87	mohor
383	88	mohor	`#10000;`
384	91	mohor	debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 32'h359e2d2a, result, "wr8 len8"); // {command, ready, addr, length, crc, result, text}
385	87	mohor
386	88	mohor	`#10000;`
387	90	mohor	debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'h5e9dd377, result, "go 1"); // {command, ready, addr, length, crc, result, text}
388	87	mohor
389	89	mohor	`#10000;`
390	90	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 32'h8bbeb90d, result, "read32 6"); // {command, ready, addr, length, crc, result, text}
391	88	mohor
392	89	mohor	`#10000;`
393	90	mohor	debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 32'hcedab37c, result, "read16 7"); // {command, ready, addr, length, crc, result, text}
394	88	mohor
395	90	mohor	`#10000;`
396	93	mohor	debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 32'hbe993245, result, "read8 8"); // {command, ready, addr, length, crc, result, text}
397	89	mohor
398	90	mohor	`#10000;`
399			debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'hd4b43491, result, "go 2"); // {command, ready, addr, length, crc, result, text}
400	89	mohor
401
402	90	mohor
403
404	80	mohor	`/*`
405			`// Testing read and write to CPU0 registers`
406			`#10000;`
407			set_instruction(`CHAIN_SELECT);
408			chain_select(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
409			set_instruction(`DEBUG);
410			`WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc}`
411
412			`ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}`
413			`ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}`
414			`*/`
415			`#5000 gen_clk(1); // One extra TCLK for debugging purposes`
416	95	mohor	`$display("\n\nSimulation end.");`
417	5	mohor	`#1000 $stop;`
418	80	mohor
419	2	mohor	`end`
420
421	80	mohor
422			`task initialize_memory;`
423			`input [31:0] start_addr;`
424			`input [31:0] length;`
425			`integer i;`
426			`reg [31:0] addr;`
427			`begin`
428			`for (i=0; i<length; i=i+4)`
429			`begin`
430			`addr = start_addr + i;`
431			`wb_slave.wr_mem(addr, {addr[7:0], addr[15:8], addr[23:16], addr[31:24]}, 4'hf); // adr, data, sel`
432			`end`
433			`end`
434			`endtask`
435
436
437
438	2	mohor	`// Generation of the TCLK signal`
439	80	mohor	`task gen_clk;`
440			`input [7:0] num;`
441	2	mohor	`integer i;`
442			`begin`
443	80	mohor	`for(i=0; i<num; i=i+1)`
444	2	mohor	`begin`
445	80	mohor	`#TCLK tck_pad_i<=1;`
446			`#TCLK tck_pad_i<=0;`
447	2	mohor	`end`
448			`end`
449			`endtask`
450
451
452			`// TAP reset`
453	80	mohor	`task reset_tap;`
454	2	mohor	`begin`
455	80	mohor	`$display("(%0t) Task reset_tap", $time);`
456			`tms_pad_i<=#1 1'b1;`
457	95	mohor	`gen_clk(5);`
458	2	mohor	`end`
459			`endtask`
460
461
462			`// Goes to RunTestIdle state`
463	80	mohor	`task goto_run_test_idle;`
464	2	mohor	`begin`
465	80	mohor	`$display("(%0t) Task goto_run_test_idle", $time);`
466			`tms_pad_i<=#1 1'b0;`
467			`gen_clk(1);`
468	2	mohor	`end`
469			`endtask`
470
471
472			`// sets the instruction to the IR register and goes to the RunTestIdle state`
473	80	mohor	`task set_instruction;`
474			`input [3:0] instr;`
475	2	mohor	`integer i;`
476
477			`begin`
478	80	mohor	`$display("(%0t) Task set_instruction", $time);`
479			`tms_pad_i<=#1 1;`
480			`gen_clk(2);`
481			`tms_pad_i<=#1 0;`
482			`gen_clk(2); // we are in shiftIR`
483	2	mohor
484			for(i=0; i<`IR_LENGTH-1; i=i+1)
485			`begin`
486	80	mohor	`tdi_pad_i<=#1 instr[i];`
487			`gen_clk(1);`
488	2	mohor	`end`
489
490	80	mohor	`tdi_pad_i<=#1 instr[i]; // last shift`
491			`tms_pad_i<=#1 1; // going out of shiftIR`
492			`gen_clk(1);`
493	90	mohor	`tdi_pad_i<=#1 'hz; // tri-state`
494	80	mohor	`gen_clk(1);`
495			`tms_pad_i<=#1 0;`
496			`gen_clk(1); // we are in RunTestIdle`
497	2	mohor	`end`
498			`endtask`
499
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