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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_tb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.24  2004/01/15 10:47:13  mohor
// Working.
//
// Revision 1.23  2004/01/14 22:59:01  mohor
// Temp version.
//
// Revision 1.22  2004/01/13 11:28:30  mohor
// tmp version.
//
// Revision 1.21  2004/01/10 07:50:41  mohor
// temp version.
//
// Revision 1.20  2004/01/09 12:49:23  mohor
// tmp version.
//
// Revision 1.19  2004/01/08 17:53:12  mohor
// tmp version.
//
// Revision 1.18  2004/01/07 11:59:48  mohor
// temp4 version.
//
// Revision 1.17  2004/01/06 17:14:59  mohor
// temp3 version.
//
// Revision 1.16  2004/01/05 12:16:50  mohor
// tmp2 version.
//
// Revision 1.15  2003/12/23 14:26:01  mohor
// New version of the debug interface. Not finished, yet.
//
// Revision 1.14  2003/10/23 16:16:30  mohor
// CRC logic changed.
//
// Revision 1.13  2003/08/28 13:54:33  simons
// Three more chains added for cpu debug access.
//
// Revision 1.12  2002/05/07 14:44:52  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.11  2002/03/12 14:32:26  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.10  2002/03/08 15:27:08  mohor
// Structure changed. Hooks for jtag chain added.
//
// Revision 1.9  2001/10/19 11:39:20  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8  2001/10/17 10:39:17  mohor
// bs_chain_o added.
//
// Revision 1.7  2001/10/16 10:10:18  mohor
// Signal names changed to lowercase.
//
// Revision 1.6  2001/10/15 09:52:50  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5  2001/09/24 14:06:12  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4  2001/09/20 10:10:29  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:54:03  mohor
// Minor changes for simulation.
//
// Revision 1.2  2001/09/18 14:12:43  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:23:40  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:05  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:15  mohor
// Initial release
//
//
 
 
`include "timescale.v"
`include "dbg_defines.v"
`include "dbg_wb_defines.v"
`include "dbg_cpu_defines.v"
//`include "dbg_tb_defines.v"
 
// Test bench
module dbg_tb;
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
reg   tms_pad_i;
reg   tck_pad_i;
reg   trst_pad_i;
reg   tdi_pad_i;
wire  tdo_pad_o;
wire  tdo_padoe_o;
 
wire  shift_dr_o;
wire  pause_dr_o;
wire  update_dr_o;
 
wire  extest_select_o;
wire  sample_preload_select_o;
wire  mbist_select_o;
wire  debug_select_o;
 
// WISHBONE common signals
reg   wb_rst_i;
reg   wb_clk_i;
 
// WISHBONE master interface
wire [31:0] wb_adr_o;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
wire        wb_cyc_o;
wire        wb_stb_o;
wire  [3:0] wb_sel_o;
wire        wb_we_o;
wire        wb_ack_i;
wire        wb_cab_o;
wire        wb_err_i;
wire  [2:0] wb_cti_o;
wire  [1:0] wb_bte_o;
 
// Text used for easier debugging
reg [199:0] test_text;
reg   [2:0] last_wb_cmd;
reg [199:0] last_wb_cmd_text;
reg  [31:0] wb_data;
 
 
 
wire  tdo_o;
 
wire  debug_tdi_i;
wire  bs_chain_tdi_i;
wire  mbist_tdi_i;
 
reg   test_enabled;
 
reg [31:0] result;
 
reg  crc_out_en;
reg  crc_out_shift;
wire crc_out;
 
 
 
wire tdo;
 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
 
// Connecting TAP module
tap_top i_tap_top (
                    .tms_pad_i(tms_pad_i),
                    .tck_pad_i(tck_pad_i),
                    .trst_pad_i(!trst_pad_i),
                    .tdi_pad_i(tdi_pad_i),
                    .tdo_pad_o(tdo_pad_o),
                    .tdo_padoe_o(tdo_padoe_o),
 
                    // TAP states
                    .shift_dr_o(shift_dr_o),
                    .pause_dr_o(pause_dr_o),
                    .update_dr_o(update_dr_o),
 
                    // Select signals for boundary scan or mbist
                    .extest_select_o(extest_select_o),
                    .sample_preload_select_o(sample_preload_select_o),
                    .mbist_select_o(mbist_select_o),
                    .debug_select_o(debug_select_o),
 
                    // TDO signal that is connected to TDI of sub-modules.
                    .tdo_o(tdo_o),
 
                    // TDI signals from sub-modules
                    .debug_tdi_i(debug_tdi_i),        // from debug module
                    .bs_chain_tdi_i(bs_chain_tdi_i),  // from Boundary Scan Chain
                    .mbist_tdi_i(mbist_tdi_i)         // from Mbist Chain
 
               );
 
 
// Connecting debug top module
dbg_top i_dbg_top  (
                    .tck_i(tck_pad_i),
                    .tdi_i(tdo_o),
                    .tdo_o(debug_tdi_i),
 
                    // TAP states
                    .shift_dr_i   (shift_dr_o),
                    .pause_dr_i   (pause_dr_o),
                    .update_dr_i  (update_dr_o),
 
                    // Instructions
                    .debug_select_i(debug_select_o),
 
                    // WISHBONE common signals
                    .wb_rst_i      (wb_rst_i),
                    .wb_clk_i      (wb_clk_i),
 
                    // WISHBONE master interface
                    .wb_adr_o      (wb_adr_o),
                    .wb_dat_o      (wb_dat_o),
                    .wb_dat_i      (wb_dat_i),
                    .wb_cyc_o      (wb_cyc_o),
                    .wb_stb_o      (wb_stb_o),
                    .wb_sel_o      (wb_sel_o),
                    .wb_we_o       (wb_we_o),
                    .wb_ack_i      (wb_ack_i),
                    .wb_cab_o      (wb_cab_o),
                    .wb_err_i      (wb_err_i),
                    .wb_cti_o      (wb_cti_o),
                    .wb_bte_o      (wb_bte_o)
                   );
 
 
 
// Connecting CRC module that calculates CRC that is shifted into debug
dbg_crc32_d1 crc32_bench_out
             (
              .data       (tdi_pad_i),
              .enable     (crc_out_en),
              .shift      (crc_out_shift),
              .rst        (wb_rst_i),
              .sync_rst   (update_dr_o),
              .crc_out    (crc_out),
              .clk        (tck_pad_i),
              .crc_match  ()
             );
 
 
 
 
wb_slave_behavioral wb_slave
                   (
                    .CLK_I(wb_clk_i),
                    .RST_I(wb_rst_i),
                    .ACK_O(wb_ack_i),
                    .ADR_I(wb_adr_o),
                    .CYC_I(wb_cyc_o),
                    .DAT_O(wb_dat_i),
                    .DAT_I(wb_dat_o),
                    .ERR_O(wb_err_i),
                    .RTY_O(),      // NOT USED for now!
                    .SEL_I(wb_sel_o),
                    .STB_I(wb_stb_o),
                    .WE_I (wb_we_o),
                    .CAB_I(1'b0)
                   );
 
 
// Initial values
initial
begin
  test_enabled = 1'b0;
  crc_out_en = 1'b0;
  crc_out_shift = 1'b0;
  wb_data = 32'h01234567;
  trst_pad_i = 1'b1;
  tms_pad_i = 1'hz;
  tck_pad_i = 1'hz;
  tdi_pad_i = 1'hz;
 
  #100;
  trst_pad_i = 1'b0;
  #100;
  trst_pad_i = 1'b1;
  #1 test_enabled<=#1 1'b1;
end
 
initial
begin
  wb_rst_i = 1'b0;
  #1000;
  wb_rst_i = 1'b1;
  #1000;
  wb_rst_i = 1'b0;
 
  // Initial values for wishbone slave model
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
end
 
initial
begin
  wb_clk_i = 1'b0;
  forever #5 wb_clk_i = ~wb_clk_i;
end
 
always @ (posedge test_enabled)
begin
 
  $display("//////////////////////////////////////////////////////////////////");
  $display("//                                                              //");
  $display("//  (%0t) dbg_tb starting                                     //", $time);
  $display("//                                                              //");
  $display("//////////////////////////////////////////////////////////////////");
 
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
 
  reset_tap;
 
  #500;
  goto_run_test_idle;
 
  // Testing read and write to internal registers
  #10000;
  set_instruction(`IDCODE);
  read_id_code;
 
  set_instruction(`DEBUG);
  #10000;
 
  chain_select(`WISHBONE_SCAN_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
//  #10000;
//  xxx(4'b1001, 32'he579b242);
 
  #10000;
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "abc 1"); // {command, ready, addr, length, gen_crc_err, result, text}
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, result, "abc 2"); // {command, ready, addr, length, gen_crc_err, result, text}
//  debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, result, "abc 3"); // {command, ready, addr, length, gen_crc_err, result, text}
//
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "abc 4"); // {command, ready, addr, length, gen_crc_err, result, text}
//  debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, result, "abc 5"); // {command, ready, addr, length, gen_crc_err, result, text}
//
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "read32 1"); // {command, ready, addr, length, gen_crc_err, result, text}
//
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, result, "abc 6"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
//  xxx(4'b1001, 32'he579b242);
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, result, "read32 2"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, result, "read32 3"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2);   // (`ERR_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, result, "read32 4"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, result, "status 1"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, result, "status 2"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, result, "read32 5"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, result, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, result, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, result, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 1"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, result, "read32 6"); // {command, ready, addr, length, gen_crc_err, result, text}
//  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, result, "read32 6"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
//  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, result, "read16 7"); // {command, ready, addr, length, gen_crc_err, result, text}
//  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, result, "read16 7"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, result, "read8 8"); // {command, ready, addr, length, gen_crc_err, result, text}  
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, result, "read8 8"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  #10000;
  chain_select(`CPU_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
  #10000;
  debug_cpu(`CPU_WRITE_REG, 32'h00000001, 32'h0, 1'b0, result, "cpu_write_reg"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
/*
  // Testing read and write to CPU0 registers
  #10000;
  set_instruction(`CHAIN_SELECT);
  chain_select(`CPU_DEBUG_CHAIN_0, 8'h12);  // {chain, crc}
  set_instruction(`DEBUG);
  WriteCPURegister(32'h11001100, 32'h00110011, 8'h86);  // {data, addr, crc}
 
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
*/
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
  $display("\n\nSimulation end.");
  #1000 $stop;
 
end
 
 
task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin
//    for (i=0; i<length; i=i+4)    // inverted address
//      begin
//        addr = start_addr + i;
//        wb_slave.wr_mem(addr, {addr[7:0], addr[15:8], addr[23:16], addr[31:24]}, 4'hf);    // adr, data, sel
//      end
    for (i=0; i<length; i=i+4)
      begin
        addr = start_addr + i;
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
      end
  end
endtask
 
 
 
// Generation of the TCLK signal
task gen_clk;
  input [7:0] num;
  integer i;
  begin
    for(i=0; i<num; i=i+1)
      begin
        #TCLK tck_pad_i<=1;
        #TCLK tck_pad_i<=0;
      end
  end
endtask
 
 
// TAP reset
task reset_tap;
  begin
    $display("(%0t) Task reset_tap", $time);
    tms_pad_i<=#1 1'b1;
    gen_clk(5);
  end
endtask
 
 
// Goes to RunTestIdle state
task goto_run_test_idle;
  begin
    $display("(%0t) Task goto_run_test_idle", $time);
    tms_pad_i<=#1 1'b0;
    gen_clk(1);
  end
endtask
 
 
// sets the instruction to the IR register and goes to the RunTestIdle state
task set_instruction;
  input [3:0] instr;
  integer i;
 
  begin
    $display("(%0t) Task set_instruction", $time);
    tms_pad_i<=#1 1;
    gen_clk(2);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftIR
 
    for(i=0; i<`IR_LENGTH-1; i=i+1)
    begin
      tdi_pad_i<=#1 instr[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 instr[i]; // last shift
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
    tdi_pad_i<=#1 'hz;    // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Reads the ID code
task read_id_code;
  begin
    $display("(%0t) Task read_id_code", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 0;
    gen_clk(31);
 
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
 
    tdi_pad_i<=#1 'hz; // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task chain_select;
  input [3:0]  data;
  input        gen_crc_err;
  integer i;
 
  begin
    case (data)
      `CPU_DEBUG_CHAIN      : $display("(%0t) Task chain_select (CPU_DEBUG_CHAIN, gen_crc_err=%0d)", $time, gen_crc_err);
      `WISHBONE_SCAN_CHAIN  : $display("(%0t) Task chain_select (WISHBONE_SCAN_CHAIN gen_crc_err=%0d)", $time, gen_crc_err);
      default               : $display("(%0t) Task chain_select (ERROR!!! Unknown chain selected)", $time);
    endcase
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out_en = 1; // Enable CRC calculation
 
    tdi_pad_i<=#1 1'b1; // chain_select bit
    gen_clk(1);
 
    for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];
      gen_clk(1);
    end
 
    crc_out_en = 0;     // Disable CRC calculation
    crc_out_shift = 1;  // Enable CRC shifting
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out;   // error crc
      else
        tdi_pad_i<=#1 crc_out;    // ok crc
 
      gen_clk(1);
    end
 
    crc_out_shift = 0;  // Disable CRC shifting
 
    tdi_pad_i<=#1 'hz;  // tri-state
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
      gen_clk(1);
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask   // chain_select
 
 
 
 
 
 
 
task debug_wishbone;
  input [2:0]   command;
  input         ready;
  input [31:0]  addr;
  input [15:0]  length;
  input         gen_crc_err;
  output [31:0] result;
  input [99:0]  text;
  integer i;
 
  begin
   $write("(%0t) Task debug_wishbone: ", $time);
 
    test_text = text;
 
    case (command)
      `WB_STATUS   :
        begin
          $display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text);
          debug_wishbone_status(command, gen_crc_err);
          last_wb_cmd = `WB_STATUS;  last_wb_cmd_text = "WB_STATUS";
        end
      `WB_READ8    :
        begin
          $display("wb_read8 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
          last_wb_cmd = `WB_READ8;  last_wb_cmd_text = "WB_READ8";
        end
      `WB_READ16   :
        begin
          $display("wb_read16 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
          last_wb_cmd = `WB_READ16;  last_wb_cmd_text = "WB_READ16";
        end
      `WB_READ32   :
        begin
          $display("wb_read32 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
          last_wb_cmd = `WB_READ32;  last_wb_cmd_text = "WB_READ32";
        end
      `WB_WRITE8   :
        begin
          $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
          last_wb_cmd = `WB_WRITE8;  last_wb_cmd_text = "WB_WRITE8";
        end
      `WB_WRITE16  :
        begin
          $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
          last_wb_cmd = `WB_WRITE16;  last_wb_cmd_text = "WB_WRITE16";
        end
      `WB_WRITE32  :
        begin
          $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
          last_wb_cmd = `WB_WRITE32;  last_wb_cmd_text = "WB_WRITE32";
        end
      `WB_GO       :
        begin
          $display("wb_go, gen_crc_err=%0d (%0s))", gen_crc_err, text);
          debug_wishbone_go(command, gen_crc_err);
//          $display("wb_go_tmp, gen_crc_err=0x%0x (%0s))", gen_crc_err, text);
//          debug_wishbone_go_tmp(command, crc);
          last_wb_cmd = `WB_GO;  last_wb_cmd_text = "WB_GO";
        end
    endcase
  end
endtask       // debug_wishbone
 
 
 
 
 
 
task debug_wishbone_set_addr;
  input [2:0]   command;
  input         wait_for_wb_ready;    // igor !!! Change this since access only occurs in the "go" stage. Add condition "fifo_empty".
  input [31:0]  addr;
  input [15:0]  length;
  input         gen_crc_err;
  integer i;
 
  begin
    $display("(%0t) Task debug_wishbone_set_addr: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out_en = 1; // Enable CRC calculation
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      gen_clk(1);
    end
 
    for(i=15; i>=0; i=i-1)       // length
    begin
      tdi_pad_i<=#1 length[i];
      gen_clk(1);
    end
 
    crc_out_en = 0;     // Disable CRC calculation
    crc_out_shift = 1;  // Enable CRC shifting
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out;   // error crc
      else
        tdi_pad_i<=#1 crc_out;    // ok crc
 
      gen_clk(1);
    end
 
    crc_out_shift = 0;  // Disable CRC shifting
 
    tdi_pad_i<=#1 'hz;
    if (wait_for_wb_ready)
      begin
        gen_clk(`STATUS_LEN -1);   // Generating 4 clocks to read out status. Going to pause_dr at the end
        tms_pad_i<=#1 1;
        gen_clk(1);       // to exit1_dr
        tms_pad_i<=#1 0;
        gen_clk(1);       // to pause_dr
 
        while (dbg_tb.tdo_pad_o)     // waiting for wb to send "ready" 
        begin
          gen_clk(1);       // staying in pause_dr
        end
 
        tms_pad_i<=#1 1;
        gen_clk(1);       // to exit2_dr
        tms_pad_i<=#1 0;
        gen_clk(1);       // to shift_dr
      end
    else
      gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_set_addr
 
 
 
 
 
task debug_wishbone_status;
  input [2:0]   command;
  input         gen_crc_err;
  integer i;
 
  begin
    $display("(%0t) Task debug_wishbone_status: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out_en = 1; // Enable CRC calculation
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    crc_out_en = 0;     // Disable CRC calculation
    crc_out_shift = 1;  // Enable CRC shifting
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out;   // error crc
      else
        tdi_pad_i<=#1 crc_out;    // ok crc
 
      gen_clk(1);
    end
 
    crc_out_shift = 0;  // Disable CRC shifting
 
    tdi_pad_i<=#1 1'hz;
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_status
 
 
 
 
task debug_wishbone_go;
  input [2:0]   command;
  input         gen_crc_err;
  integer i;
  reg   [4:0]   pointer;
 
  begin
    $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out_en = 1; // Enable CRC calculation
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
 
    if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
          begin
            if (!(i%32))
              begin
                wb_data = wb_data + 32'h11111111;
                $display("\t\twb_data = 0x%x", wb_data);
              end
            pointer = 31-i[4:0];
            tdi_pad_i<=#1 wb_data[pointer];
            gen_clk(1);
 
          end
      end
 
    crc_out_en = 0;     // Disable CRC calculation
    crc_out_shift = 1;  // Enable CRC shifting
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out;   // error crc
      else
        tdi_pad_i<=#1 crc_out;    // ok crc
 
      gen_clk(1);
    end
 
    crc_out_shift = 0;  // Disable CRC shifting
 
    tdi_pad_i<=#1 1'hz;
 
 
 
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
          gen_clk(1);
      end
 
 
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_go
 
 
 
 
task debug_cpu;
  input [2:0]   command;
  input [31:0]  addr;
  input [31:0]  data;
  input         gen_crc_err;
  output [31:0] result;
  input [199:0]  text;
  integer i;
 
  begin
   $write("(%0t) Task debug_cpu: ", $time);
 
    test_text = text;
 
    case (command)
//      `WB_STATUS   : 
//        begin
//          $display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text);
//          debug_wishbone_status(command, gen_crc_err);
//          last_wb_cmd = `WB_STATUS;  last_wb_cmd_text = "WB_STATUS";
//        end 
      `CPU_READ_REG   :
        begin
          $display("cpu_read_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_READ_REG;  last_wb_cmd_text = "CPU_READ_REG";
        end
      `CPU_WRITE_REG  :
        begin
          $display("cpu_write_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_WRITE_REG;  last_wb_cmd_text = "CPU_WRITE_REG";
        end
      `CPU_READ8      :
        begin
          $display("cpu_read8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_READ8;  last_wb_cmd_text = "CPU_READ8";
        end
      `CPU_READ32     :
        begin
          $display("cpu_read32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_READ32;  last_wb_cmd_text = "CPU_READ32";
        end
      `CPU_WRITE8     :
        begin
          $display("cpu_write8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_WRITE8;  last_wb_cmd_text = "CPU_WRITE8";
        end
      `CPU_WRITE32    :
        begin
          $display("cpu_write32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_WRITE32;  last_wb_cmd_text = "CPU_WRITE32";
        end
      `CPU_GO         :
        begin
          $display("cpu_go, data = 0x%0x, gen_crc_err=%0d (%0s))", data, gen_crc_err, text);
          debug_cpu_go(command, data, gen_crc_err);
          last_wb_cmd = `CPU_GO;  last_wb_cmd_text = "CPU_GO";
        end
      default     :
        begin
          $display("\t\tERROR: Non-existing command while debugging %0s", gen_crc_err, text);
          $stop;
        end
    endcase
  end
endtask       // debug_cpu
 
 
 
task debug_cpu_set_addr;
  input [2:0]   command;
  input [31:0]  addr;
  input         gen_crc_err;
  integer i;
 
  begin
    $display("(%0t) Task debug_cpu_set_addr: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out_en = 1; // Enable CRC calculation
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      gen_clk(1);
    end
 
    crc_out_en = 0;     // Disable CRC calculation
    crc_out_shift = 1;  // Enable CRC shifting
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out;   // error crc
      else
        tdi_pad_i<=#1 crc_out;    // ok crc
 
      gen_clk(1);
    end
 
    crc_out_shift = 0;  // Disable CRC shifting
 
    tdi_pad_i<=#1 'hz;
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_cpu_set_addr
 
 
 
 
task debug_cpu_go;
  input [2:0]   command;
  input [31:0]  data;
  input         gen_crc_err;
  integer i, len;
 
 
  begin
    $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out_en = 1; // Enable CRC calculation
 
    tdi_pad_i<=#1 1'b0; // chain_select bit = 0
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      gen_clk(1);
    end
 
 
    if (last_wb_cmd == `CPU_WRITE32)
      begin
        len = 31;
        $display("\t\tdata = 0x%x", data);
      end
    else if ((last_wb_cmd == `CPU_WRITE8) | (last_wb_cmd == `CPU_WRITE_REG))
      begin
        len = 7;
        $display("\t\tdata = 0x%x", data[7:0]);
      end
    else
      len = 0;
 
    if (len>0)  // When CPU_WRITEx was previously activated, data needs to be shifted.
      begin
        for (i=len; i>=0; i=i-1)
          begin
            tdi_pad_i<=#1 data[i];
            gen_clk(1);
          end
      end
 
    crc_out_en = 0;     // Disable CRC calculation
    crc_out_shift = 1;  // Enable CRC shifting
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out;   // error crc
      else
        tdi_pad_i<=#1 crc_out;    // ok crc
 
      gen_clk(1);
    end
 
    crc_out_shift = 0;  // Disable CRC shifting
 
    tdi_pad_i<=#1 1'hz;
 
 
    if (last_wb_cmd == `CPU_READ32)
      len = 32;
    else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
      len = 8;
    else
      len = 0;
 
    if (len>0)    // When CPU_WRITEx was previously activated, data needs to be shifted.
      begin
        $display("\t\tGenerating %0d clocks to read out the data.", len);
        for (i=0; i<len; i=i+1)
          gen_clk(1);
      end
 
 
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_cpu_go
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Printing the information to the screen                                        *
*                                                                                 *
**********************************************************************************/
 
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.update_ir)
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
      `EXTEST         : $display("\tInstruction EXTEST entered");
      `SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
      `IDCODE         : $display("\tInstruction IDCODE entered");
      `MBIST          : $display("\tInstruction MBIST entered");
      `DEBUG          : $display("\tInstruction DEBUG entered");
      `BYPASS         : $display("\tInstruction BYPASS entered");
                default           :     $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
    endcase
end
 
 
 
// Print shifted IDCode
reg [31:0] tmp_data;
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.idcode_select)
    begin
      if(dbg_tb.i_tap_top.shift_dr)
        tmp_data[31:0]<=#1 {dbg_tb.tdo, tmp_data[31:1]};
      else
      if(dbg_tb.i_tap_top.update_dr)
        if (tmp_data[31:0] != `IDCODE_VALUE)
          begin
            $display("(%0t) ERROR: IDCODE not correct", $time);
            $stop;
          end
        else
          $display("\t\tIDCode = 0x%h", tmp_data[31:0]);
    end
end
 
 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
    begin
      $display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
      $display("(%0t) Simulation stopped !!!", $time);
      $stop;
    end
end
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task xxx;
  input [3:0]  data;
  input [31:0] crc;
  integer i;
 
  begin
    $display("(%0t) Task xxx", $time);
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    for(i=0; i<4; i=i+1)
    begin
      tdi_pad_i<=#1 data[i];
      gen_clk(1);
    end
 
    for(i=0; i<`CRC_LEN; i=i+1)
    begin
      tdi_pad_i<=#1 crc[`CRC_LEN - 1 - i];
      gen_clk(1);
    end
 
    gen_clk(`STATUS_LEN);   // Generating 5 clocks to read out status.
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
    begin
      tdi_pad_i<=#1 1'b0;
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 crc[i]; // last crc
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    tdi_pad_i<=#1 'hz;  // tri-state
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask
 
 
 
// Detecting CRC error
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en)
begin
  #2;
  if (~dbg_tb.i_dbg_top.crc_match)
    begin
      $display("\t\tCRC ERROR !!!");
      $stop;
    end
end
 
 
 
// Detecting errors in counters
always @ (dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt or
          dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end or
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt or
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end or
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt or
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or
          dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en or
          dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt2 or
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt3 or
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt4
          // dbg_tb.i_dbg_top.i_dbg_wb. or
         )
begin
  if ((~dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end) & (
                                                  dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en |
                                                  dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en     |
                                                  dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en      |
                                                  dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
                                                 )
     )
    begin
      $display("\n\n\t\t(%0t) ERROR in counters !!!", $time);
      #10000;
      $stop;
    end
 
 
 
end
 
 
 
 
 
 
endmodule // dbg_tb
 
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_tb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7	36	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	80	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	80	mohor	`//// Copyright (C) 2000 - 2003 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	99	mohor	`// Revision 1.24 2004/01/15 10:47:13 mohor`
47			`// Working.`
48			`//`
49	96	mohor	`// Revision 1.23 2004/01/14 22:59:01 mohor`
50			`// Temp version.`
51			`//`
52	95	mohor	`// Revision 1.22 2004/01/13 11:28:30 mohor`
53			`// tmp version.`
54			`//`
55	93	mohor	`// Revision 1.21 2004/01/10 07:50:41 mohor`
56			`// temp version.`
57			`//`
58	92	mohor	`// Revision 1.20 2004/01/09 12:49:23 mohor`
59			`// tmp version.`
60			`//`
61	91	mohor	`// Revision 1.19 2004/01/08 17:53:12 mohor`
62			`// tmp version.`
63			`//`
64	90	mohor	`// Revision 1.18 2004/01/07 11:59:48 mohor`
65			`// temp4 version.`
66			`//`
67	89	mohor	`// Revision 1.17 2004/01/06 17:14:59 mohor`
68			`// temp3 version.`
69			`//`
70	88	mohor	`// Revision 1.16 2004/01/05 12:16:50 mohor`
71			`// tmp2 version.`
72			`//`
73	87	mohor	`// Revision 1.15 2003/12/23 14:26:01 mohor`
74			`// New version of the debug interface. Not finished, yet.`
75			`//`
76	80	mohor	`// Revision 1.14 2003/10/23 16:16:30 mohor`
77			`// CRC logic changed.`
78			`//`
79	73	mohor	`// Revision 1.13 2003/08/28 13:54:33 simons`
80			`// Three more chains added for cpu debug access.`
81			`//`
82	63	simons	`// Revision 1.12 2002/05/07 14:44:52 mohor`
83			`// mon_cntl_o signals that controls monitor mux added.`
84			`//`
85	47	mohor	`// Revision 1.11 2002/03/12 14:32:26 mohor`
86			`// Few outputs for boundary scan chain added.`
87			`//`
88	38	mohor	`// Revision 1.10 2002/03/08 15:27:08 mohor`
89			`// Structure changed. Hooks for jtag chain added.`
90			`//`
91	36	mohor	`// Revision 1.9 2001/10/19 11:39:20 mohor`
92			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
93			`// few different cores in a single project.`
94			`//`
95	17	mohor	`// Revision 1.8 2001/10/17 10:39:17 mohor`
96			`// bs_chain_o added.`
97			`//`
98	15	mohor	`// Revision 1.7 2001/10/16 10:10:18 mohor`
99			`// Signal names changed to lowercase.`
100			`//`
101	13	mohor	`// Revision 1.6 2001/10/15 09:52:50 mohor`
102			`// Wishbone interface added, few fixes for better performance,`
103			`// hooks for boundary scan testing added.`
104			`//`
105	12	mohor	`// Revision 1.5 2001/09/24 14:06:12 mohor`
106			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
107			`//`
108	11	mohor	`// Revision 1.4 2001/09/20 10:10:29 mohor`
109			`// Working version. Few bugs fixed, comments added.`
110			`//`
111	9	mohor	`// Revision 1.3 2001/09/19 11:54:03 mohor`
112			`// Minor changes for simulation.`
113			`//`
114	6	mohor	`// Revision 1.2 2001/09/18 14:12:43 mohor`
115			`// Trace fixed. Some registers changed, trace simplified.`
116			`//`
117	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
118			`// Initial official release.`
119			`//`
120	2	mohor	`// Revision 1.3 2001/06/01 22:23:40 mohor`
121			`// This is a backup. It is not a fully working version. Not for use, yet.`
122			`//`
123			`// Revision 1.2 2001/05/18 13:10:05 mohor`
124			`// Headers changed. All additional information is now avaliable in the README.txt file.`
125			`//`
126			`// Revision 1.1.1.1 2001/05/18 06:35:15 mohor`
127			`// Initial release`
128			`//`
129			`//`
130
131
132	17	mohor	`include "timescale.v"
133	2	mohor	`include "dbg_defines.v"
134	80	mohor	`include "dbg_wb_defines.v"
135	99	mohor	`include "dbg_cpu_defines.v"
136	80	mohor	//`include "dbg_tb_defines.v"
137	2	mohor
138			`// Test bench`
139			`module dbg_tb;`
140
141	80	mohor	`parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)`
142	2	mohor
143	80	mohor	`reg tms_pad_i;`
144			`reg tck_pad_i;`
145			`reg trst_pad_i;`
146			`reg tdi_pad_i;`
147			`wire tdo_pad_o;`
148			`wire tdo_padoe_o;`
149	2	mohor
150	80	mohor	`wire shift_dr_o;`
151			`wire pause_dr_o;`
152			`wire update_dr_o;`
153	2	mohor
154	80	mohor	`wire extest_select_o;`
155			`wire sample_preload_select_o;`
156			`wire mbist_select_o;`
157			`wire debug_select_o;`
158	2	mohor
159	80	mohor	`// WISHBONE common signals`
160			`reg wb_rst_i;`
161			`reg wb_clk_i;`
162
163			`// WISHBONE master interface`
164			`wire [31:0] wb_adr_o;`
165			`wire [31:0] wb_dat_o;`
166			`wire [31:0] wb_dat_i;`
167			`wire wb_cyc_o;`
168			`wire wb_stb_o;`
169			`wire [3:0] wb_sel_o;`
170			`wire wb_we_o;`
171			`wire wb_ack_i;`
172			`wire wb_cab_o;`
173			`wire wb_err_i;`
174			`wire [2:0] wb_cti_o;`
175			`wire [1:0] wb_bte_o;`
176	2	mohor
177	87	mohor	`// Text used for easier debugging`
178	99	mohor	`reg [199:0] test_text;`
179	88	mohor	`reg [2:0] last_wb_cmd;`
180	99	mohor	`reg [199:0] last_wb_cmd_text;`
181	88	mohor	`reg [31:0] wb_data;`
182	2	mohor
183
184	12	mohor
185	80	mohor	`wire tdo_o;`
186	12	mohor
187	80	mohor	`wire debug_tdi_i;`
188			`wire bs_chain_tdi_i;`
189			`wire mbist_tdi_i;`
190	73	mohor
191	80	mohor	`reg test_enabled;`
192	73	mohor
193	80	mohor	`reg [31:0] result;`
194	2	mohor
195	99	mohor	`reg crc_out_en;`
196			`reg crc_out_shift;`
197			`wire crc_out;`
198	88	mohor
199	99	mohor
200
201	80	mohor	`wire tdo;`
202	73	mohor
203	80	mohor	`assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;`
204	73	mohor
205	80	mohor	`// Connecting TAP module`
206			`tap_top i_tap_top (`
207			`.tms_pad_i(tms_pad_i),`
208			`.tck_pad_i(tck_pad_i),`
209			`.trst_pad_i(!trst_pad_i),`
210			`.tdi_pad_i(tdi_pad_i),`
211			`.tdo_pad_o(tdo_pad_o),`
212			`.tdo_padoe_o(tdo_padoe_o),`
213	38	mohor
214	80	mohor	`// TAP states`
215			`.shift_dr_o(shift_dr_o),`
216			`.pause_dr_o(pause_dr_o),`
217			`.update_dr_o(update_dr_o),`
218	38	mohor
219	80	mohor	`// Select signals for boundary scan or mbist`
220			`.extest_select_o(extest_select_o),`
221			`.sample_preload_select_o(sample_preload_select_o),`
222			`.mbist_select_o(mbist_select_o),`
223			`.debug_select_o(debug_select_o),`
224	2	mohor
225	80	mohor	`// TDO signal that is connected to TDI of sub-modules.`
226			`.tdo_o(tdo_o),`
227	38	mohor
228	80	mohor	`// TDI signals from sub-modules`
229			`.debug_tdi_i(debug_tdi_i), // from debug module`
230			`.bs_chain_tdi_i(bs_chain_tdi_i), // from Boundary Scan Chain`
231			`.mbist_tdi_i(mbist_tdi_i) // from Mbist Chain`
232	73	mohor
233	38	mohor	`);`
234	2	mohor
235
236	99	mohor	`// Connecting debug top module`
237	80	mohor	`dbg_top i_dbg_top (`
238			`.tck_i(tck_pad_i),`
239			`.tdi_i(tdo_o),`
240			`.tdo_o(debug_tdi_i),`
241
242			`// TAP states`
243			`.shift_dr_i (shift_dr_o),`
244			`.pause_dr_i (pause_dr_o),`
245			`.update_dr_i (update_dr_o),`
246
247			`// Instructions`
248			`.debug_select_i(debug_select_o),`
249	12	mohor
250	80	mohor	`// WISHBONE common signals`
251			`.wb_rst_i (wb_rst_i),`
252			`.wb_clk_i (wb_clk_i),`
253
254			`// WISHBONE master interface`
255			`.wb_adr_o (wb_adr_o),`
256			`.wb_dat_o (wb_dat_o),`
257			`.wb_dat_i (wb_dat_i),`
258			`.wb_cyc_o (wb_cyc_o),`
259			`.wb_stb_o (wb_stb_o),`
260			`.wb_sel_o (wb_sel_o),`
261			`.wb_we_o (wb_we_o),`
262			`.wb_ack_i (wb_ack_i),`
263			`.wb_cab_o (wb_cab_o),`
264			`.wb_err_i (wb_err_i),`
265			`.wb_cti_o (wb_cti_o),`
266			`.wb_bte_o (wb_bte_o)`
267			`);`
268	12	mohor
269
270	99	mohor
271			`// Connecting CRC module that calculates CRC that is shifted into debug`
272			`dbg_crc32_d1 crc32_bench_out`
273			`(`
274			`.data (tdi_pad_i),`
275			`.enable (crc_out_en),`
276			`.shift (crc_out_shift),`
277			`.rst (wb_rst_i),`
278			`.sync_rst (update_dr_o),`
279			`.crc_out (crc_out),`
280			`.clk (tck_pad_i),`
281			`.crc_match ()`
282			`);`
283
284
285
286
287	80	mohor	`wb_slave_behavioral wb_slave`
288			`(`
289			`.CLK_I(wb_clk_i),`
290			`.RST_I(wb_rst_i),`
291			`.ACK_O(wb_ack_i),`
292			`.ADR_I(wb_adr_o),`
293			`.CYC_I(wb_cyc_o),`
294			`.DAT_O(wb_dat_i),`
295			`.DAT_I(wb_dat_o),`
296			`.ERR_O(wb_err_i),`
297			`.RTY_O(), // NOT USED for now!`
298			`.SEL_I(wb_sel_o),`
299			`.STB_I(wb_stb_o),`
300			`.WE_I (wb_we_o),`
301			`.CAB_I(1'b0)`
302			`);`
303	2	mohor
304
305	80	mohor	`// Initial values`
306	2	mohor	`initial`
307			`begin`
308	80	mohor	`test_enabled = 1'b0;`
309	99	mohor	`crc_out_en = 1'b0;`
310			`crc_out_shift = 1'b0;`
311	88	mohor	`wb_data = 32'h01234567;`
312	80	mohor	`trst_pad_i = 1'b1;`
313			`tms_pad_i = 1'hz;`
314			`tck_pad_i = 1'hz;`
315			`tdi_pad_i = 1'hz;`
316
317			`#100;`
318			`trst_pad_i = 1'b0;`
319			`#100;`
320			`trst_pad_i = 1'b1;`
321			`#1 test_enabled<=#1 1'b1;`
322	2	mohor	`end`
323
324	80	mohor	`initial`
325			`begin`
326			`wb_rst_i = 1'b0;`
327			`#1000;`
328			`wb_rst_i = 1'b1;`
329			`#1000;`
330			`wb_rst_i = 1'b0;`
331	2	mohor
332	80	mohor	`// Initial values for wishbone slave model`
333	96	mohor	wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
334	80	mohor	`end`
335
336			`initial`
337	2	mohor	`begin`
338	80	mohor	`wb_clk_i = 1'b0;`
339			`forever #5 wb_clk_i = ~wb_clk_i;`
340	2	mohor	`end`
341
342	80	mohor	`always @ (posedge test_enabled)`
343			`begin`
344	2	mohor
345	80	mohor	`$display("//////////////////////////////////////////////////////////////////");`
346			`$display("// //");`
347			`$display("// (%0t) dbg_tb starting //", $time);`
348			`$display("// //");`
349			`$display("//////////////////////////////////////////////////////////////////");`
350	2	mohor
351	80	mohor	`initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000`
352	2	mohor
353	80	mohor	`reset_tap;`
354	95	mohor
355			`#500;`
356	80	mohor	`goto_run_test_idle;`
357	12	mohor
358	80	mohor	`// Testing read and write to internal registers`
359			`#10000;`
360			set_instruction(`IDCODE);
361			`read_id_code;`
362	12	mohor
363	80	mohor	set_instruction(`DEBUG);
364			`#10000;`
365	2	mohor
366	99	mohor	chain_select(`WISHBONE_SCAN_CHAIN, 1'b0); // {chain, gen_crc_err}
367	12	mohor
368	80	mohor	`// #10000;`
369			`// xxx(4'b1001, 32'he579b242);`
370	12	mohor
371	80	mohor	`#10000;`
372	2	mohor
373	99	mohor	// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "abc 1"); // {command, ready, addr, length, gen_crc_err, result, text}
374			// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, result, "abc 2"); // {command, ready, addr, length, gen_crc_err, result, text}
375			// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, result, "abc 3"); // {command, ready, addr, length, gen_crc_err, result, text}
376	88	mohor	`//`
377	99	mohor	// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "abc 4"); // {command, ready, addr, length, gen_crc_err, result, text}
378			// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, result, "abc 5"); // {command, ready, addr, length, gen_crc_err, result, text}
379	88	mohor	`//`
380	99	mohor	debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, result, "read32 1"); // {command, ready, addr, length, gen_crc_err, result, text}
381	88	mohor	`//`
382	99	mohor	// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, result, "abc 6"); // {command, ready, addr, length, gen_crc_err, result, text}
383	2	mohor
384	80	mohor	`#10000;`
385			`// xxx(4'b1001, 32'he579b242);`
386
387	99	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, result, "read32 2"); // {command, ready, addr, length, gen_crc_err, result, text}
388	87	mohor
389			`#10000;`
390	96	mohor	wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
391	99	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, result, "read32 3"); // {command, ready, addr, length, gen_crc_err, result, text}
392	80	mohor
393			`#10000;`
394	96	mohor	wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries);
395	99	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, result, "read32 4"); // {command, ready, addr, length, gen_crc_err, result, text}
396	80	mohor
397			`#10000;`
398	99	mohor	debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, result, "status 1"); // {command, ready, addr, length, gen_crc_err, result, text}
399	80	mohor
400	87	mohor	`#10000;`
401	99	mohor	debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, result, "status 2"); // {command, ready, addr, length, gen_crc_err, result, text}
402	80	mohor
403	87	mohor	`#10000;`
404	96	mohor	wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
405	99	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, result, "read32 5"); // {command, ready, addr, length, gen_crc_err, result, text}
406	80	mohor
407	87	mohor	`#10000;`
408	99	mohor	debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, result, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, result, text}
409	87	mohor
410			`#10000;`
411	99	mohor	debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, result, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, result, text}
412	87	mohor
413	88	mohor	`#10000;`
414	99	mohor	debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, result, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, result, text}
415	87	mohor
416	88	mohor	`#10000;`
417	99	mohor	debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 1"); // {command, ready, addr, length, gen_crc_err, result, text}
418	87	mohor
419	89	mohor	`#10000;`
420	99	mohor	debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, result, "read32 6"); // {command, ready, addr, length, gen_crc_err, result, text}
421			// debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, result, "read32 6"); // {command, ready, addr, length, gen_crc_err, result, text}
422	88	mohor
423	89	mohor	`#10000;`
424	99	mohor	// debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, result, "read16 7"); // {command, ready, addr, length, gen_crc_err, result, text}
425			// debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, result, "read16 7"); // {command, ready, addr, length, gen_crc_err, result, text}
426	88	mohor
427	90	mohor	`#10000;`
428	99	mohor	// debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, result, "read8 8"); // {command, ready, addr, length, gen_crc_err, result, text}
429			// debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, result, "read8 8"); // {command, ready, addr, length, gen_crc_err, result, text}
430	89	mohor
431	90	mohor	`#10000;`
432	99	mohor	debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text}
433	89	mohor
434	99	mohor	`#10000;`
435			chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
436	89	mohor
437	99	mohor	`#10000;`
438			debug_cpu(`CPU_WRITE_REG, 32'h00000001, 32'h0, 1'b0, result, "cpu_write_reg"); // {command, addr, data, gen_crc_err, result, text}
439	90	mohor
440	99	mohor	`#10000;`
441			debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
442	90	mohor
443	99	mohor
444	80	mohor	`/*`
445			`// Testing read and write to CPU0 registers`
446			`#10000;`
447			set_instruction(`CHAIN_SELECT);
448			chain_select(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
449			set_instruction(`DEBUG);
450			`WriteCPURegister(32'h11001100, 32'h00110011, 8'h86); // {data, addr, crc}`
451
452			`ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}`
453			`ReadCPURegister(32'h11001100, 8'hdb); // {addr, crc}`
454			`*/`
455			`#5000 gen_clk(1); // One extra TCLK for debugging purposes`
456	95	mohor	`$display("\n\nSimulation end.");`
457	5	mohor	`#1000 $stop;`
458	80	mohor
459	2	mohor	`end`
460
461	80	mohor
462			`task initialize_memory;`
463			`input [31:0] start_addr;`
464			`input [31:0] length;`
465			`integer i;`
466			`reg [31:0] addr;`
467			`begin`
468	96	mohor	`// for (i=0; i<length; i=i+4) // inverted address`
469			`// begin`
470			`// addr = start_addr + i;`
471			`// wb_slave.wr_mem(addr, {addr[7:0], addr[15:8], addr[23:16], addr[31:24]}, 4'hf); // adr, data, sel`
472			`// end`
473	80	mohor	`for (i=0; i<length; i=i+4)`
474			`begin`
475			`addr = start_addr + i;`
476	96	mohor	`wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf); // adr, data, sel`
477	80	mohor	`end`
478			`end`
479			`endtask`
480
481
482
483	2	mohor	`// Generation of the TCLK signal`
484	80	mohor	`task gen_clk;`
485			`input [7:0] num;`
486	2	mohor	`integer i;`
487			`begin`
488	80	mohor	`for(i=0; i<num; i=i+1)`
489	2	mohor	`begin`
490	80	mohor	`#TCLK tck_pad_i<=1;`
491			`#TCLK tck_pad_i<=0;`
492	2	mohor	`end`
493			`end`
494			`endtask`
495
496
497			`// TAP reset`
498	80	mohor	`task reset_tap;`
499	2	mohor	`begin`
500	80	mohor	`$display("(%0t) Task reset_tap", $time);`

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