URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [wb_slave_behavioral.v] - Blame information for rev 80

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_slave_behavioral.v                                       ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////      Tadej Markovic, tadej@opencores.org                     ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
 
`include "timescale.v"
`include "wb_model_defines.v"
module wb_slave_behavioral
(
        CLK_I,
        RST_I,
        ACK_O,
        ADR_I,
        CYC_I,
        DAT_O,
        DAT_I,
        ERR_O,
        RTY_O,
        SEL_I,
        STB_I,
        WE_I,
        CAB_I
);
 
/*------------------------------------------------------------------------------------------------------
WISHBONE signals
------------------------------------------------------------------------------------------------------*/
input                   CLK_I;
input                   RST_I;
output                  ACK_O;
input   `WB_ADDR_TYPE   ADR_I;
input                   CYC_I;
output  `WB_DATA_TYPE   DAT_O;
input   `WB_DATA_TYPE   DAT_I;
output                  ERR_O;
output                  RTY_O;
input   `WB_SEL_TYPE    SEL_I;
input                   STB_I;
input                   WE_I;
input                   CAB_I;
 
reg     `WB_DATA_TYPE   DAT_O;
 
/*------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
------------------------------------------------------------------------------------------------------*/
//reg     `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
reg     `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
reg     `WB_DATA_TYPE mem_wr_data_out;
reg     `WB_DATA_TYPE mem_rd_data_in;
 
/*------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
------------------------------------------------------------------------------------------------------*/
reg     [2:0]  a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
reg     [7:0]  wait_cyc;
reg     [7:0]  max_retry;
 
// assign registers to default state while in reset
// always@(RST_I)
// begin
//   if (RST_I)
//   begin
//     a_e_r_resp <= 3'b000; // do not respond
//     wait_cyc   <= 8'b0; // no wait cycles
//     max_retry  <= 8'h0; // no retries
//   end
// end //reset
 
task cycle_response;
  input [2:0]  ack_err_rty_resp; // acknowledge, error or retry response input flags
  input [7:0]  wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
  input [7:0]  retry_cycles; // noumber of retry cycles before acknowledge cycle
begin
  // assign values
  a_e_r_resp <= #1 ack_err_rty_resp;
  wait_cyc   <= #1 wait_cycles;
  max_retry  <= #1 retry_cycles;
end
endtask // cycle_response
 
/*------------------------------------------------------------------------------------------------------
Tasks for writing and reading to and from memory !!!
------------------------------------------------------------------------------------------------------*/
reg    `WB_ADDR_TYPE task_wr_adr_i;
reg    `WB_ADDR_TYPE task_rd_adr_i;
reg    `WB_DATA_TYPE task_dat_i;
reg    `WB_DATA_TYPE task_dat_o;
reg    `WB_SEL_TYPE  task_sel_i;
reg                  task_wr_data;
reg                  task_data_written;
reg    `WB_DATA_TYPE task_mem_wr_data;
 
// write to memory
task wr_mem;
  input  `WB_ADDR_TYPE adr_i;
  input  `WB_DATA_TYPE dat_i;
  input  `WB_SEL_TYPE  sel_i;
begin
  task_data_written = 0;
  task_wr_adr_i = adr_i;
  task_dat_i = dat_i;
  task_sel_i = sel_i;
  task_wr_data = 1;
  wait(task_data_written);
  task_wr_data = 0;
end
endtask
 
// read from memory
task rd_mem;
  input  `WB_ADDR_TYPE adr_i;
  output `WB_DATA_TYPE dat_o;
  input  `WB_SEL_TYPE  sel_i;
begin
  task_rd_adr_i = adr_i;
  task_sel_i = sel_i;
  #1;
  dat_o = task_dat_o;
end
endtask
 
/*------------------------------------------------------------------------------------------------------
Internal signals and logic
------------------------------------------------------------------------------------------------------*/
reg            calc_ack;
reg            calc_err;
reg            calc_rty;
 
reg     [7:0]  retry_cnt;
reg     [7:0]  retry_num;
reg            retry_expired;
 
// Retry counter
always@(posedge RST_I or posedge CLK_I)
begin
  if (RST_I)
    retry_cnt <= #1 8'h00;
  else
  begin
    if (calc_ack || calc_err)
      retry_cnt <= #1 8'h00;
    else if (calc_rty)
      retry_cnt <= #1 retry_num;
  end
end
 
always@(retry_cnt or max_retry)
begin
  if (retry_cnt < max_retry)
  begin
    retry_num = retry_cnt + 1'b1;
    retry_expired = 1'b0;
  end
  else
  begin
    retry_num = retry_cnt;
    retry_expired = 1'b1;
  end
end
 
reg     [7:0]  wait_cnt;
reg     [7:0]  wait_num;
reg            wait_expired;
 
// Wait counter
always@(posedge RST_I or posedge CLK_I)
begin
  if (RST_I)
    wait_cnt <= #1 8'h0;
  else
  begin
    if (wait_expired || ~STB_I)
      wait_cnt <= #1 8'h0;
    else
      wait_cnt <= #1 wait_num;
  end
end
 
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
  if ((wait_cyc > 0) && (STB_I))
  begin
    if (wait_cnt < wait_cyc)
    begin
      wait_num = wait_cnt + 1'b1;
      wait_expired = 1'b0;
      calc_ack = 1'b0;
      calc_err = 1'b0;
      calc_rty = 1'b0;
    end
    else
    begin
      wait_num = wait_cnt;
      wait_expired = 1'b1;
      if (a_e_r_resp == 3'b100)
      begin
        calc_ack = 1'b1;
        calc_err = 1'b0;
        calc_rty = 1'b0;
      end
      else
      if (a_e_r_resp == 3'b010)
      begin
        calc_ack = 1'b0;
        calc_err = 1'b1;
        calc_rty = 1'b0;
      end
      else
      if (a_e_r_resp == 3'b001)
      begin
        calc_err = 1'b0;
        if (retry_expired)
        begin
          calc_ack = 1'b1;
          calc_rty = 1'b0;
        end
        else
        begin
          calc_ack = 1'b0;
          calc_rty = 1'b1;
        end
      end
      else
      begin
        calc_ack = 1'b0;
        calc_err = 1'b0;
        calc_rty = 1'b0;
      end
    end
  end
  else
  if ((wait_cyc == 0) && (STB_I))
  begin
    wait_num = 8'h0;
    wait_expired = 1'b1;
    if (a_e_r_resp == 3'b100)
    begin
      calc_ack = 1'b1;
      calc_err = 1'b0;
      calc_rty = 1'b0;
    end
    else if (a_e_r_resp == 3'b010)
    begin
      calc_ack = 1'b0;
      calc_err = 1'b1;
      calc_rty = 1'b0;
    end
    else if (a_e_r_resp == 3'b001)
    begin
      calc_err = 1'b0;
      if (retry_expired)
      begin
        calc_ack = 1'b1;
        calc_rty = 1'b0;
      end
      else
      begin
        calc_ack = 1'b0;
        calc_rty = 1'b1;
      end
    end
    else
    begin
      calc_ack = 1'b0;
      calc_err = 1'b0;
      calc_rty = 1'b0;
    end
  end
  else
  begin
    wait_num = 8'h0;
    wait_expired = 1'b0;
    calc_ack = 1'b0;
    calc_err = 1'b0;
    calc_rty = 1'b0;
  end
end
 
wire rd_sel = (CYC_I && STB_I && ~WE_I);
wire wr_sel = (CYC_I && STB_I && WE_I);
 
// Generate cycle termination signals
assign ACK_O = calc_ack && STB_I;
assign ERR_O = calc_err && STB_I;
assign RTY_O = calc_rty && STB_I;
 
// Assign address to asynchronous memory
always@(RST_I or ADR_I)
begin
  if (RST_I) // this is added because at start of test bench we need address change in order to get data!
  begin
    #1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
  end
  else
  begin
//    #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
    #1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
  end
end
 
// Data input/output interface
always@(rd_sel or mem_rd_data_in or RST_I)
begin
  if (RST_I)
    DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;       // assign outputs to unknown state while in reset
  else if (rd_sel)
    DAT_O <=#1 mem_rd_data_in;
  else
    DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
end
 
 
always@(RST_I or task_rd_adr_i)
begin
  if (RST_I)
    task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
  else
    task_dat_o = wb_memory[task_rd_adr_i[21:2]];
end
always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
        mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or
        SEL_I or task_sel_i)
begin
  if (task_wr_data)
  begin
    task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
 
    if (task_sel_i[3])
      task_mem_wr_data[31:24] = task_dat_i[31:24];
    if (task_sel_i[2])
      task_mem_wr_data[23:16] = task_dat_i[23:16];
    if (task_sel_i[1])
      task_mem_wr_data[15: 8] = task_dat_i[15: 8];
    if (task_sel_i[0])
      task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
 
    wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
    task_data_written = 1;
  end
  else if (wr_sel && CLK_I)
  begin
//    mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
    mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
 
    if (SEL_I[3])
      mem_wr_data_out[31:24] = DAT_I[31:24];
    if (SEL_I[2])
      mem_wr_data_out[23:16] = DAT_I[23:16];
    if (SEL_I[1])
      mem_wr_data_out[15: 8] = DAT_I[15: 8];
    if (SEL_I[0])
      mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
 
//    wb_memory[ADR_I[25:2]]  <= mem_wr_data_out; // write data
    wb_memory[ADR_I[21:2]]      = mem_wr_data_out; // write data
  end
end
 
endmodule

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [wb_slave_behavioral.v] - Blame information for rev 80

Line No.	Rev	Author	Line
1	80	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// wb_slave_behavioral.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Tadej Markovic, tadej@opencores.org ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`//`
47			`//`
48			`//`
49
50			`include "timescale.v"
51			`include "wb_model_defines.v"
52			`module wb_slave_behavioral`
53			`(`
54			`CLK_I,`
55			`RST_I,`
56			`ACK_O,`
57			`ADR_I,`
58			`CYC_I,`
59			`DAT_O,`
60			`DAT_I,`
61			`ERR_O,`
62			`RTY_O,`
63			`SEL_I,`
64			`STB_I,`
65			`WE_I,`
66			`CAB_I`
67			`);`
68
69			`/*------------------------------------------------------------------------------------------------------`
70			`WISHBONE signals`
71			`------------------------------------------------------------------------------------------------------*/`
72			`input CLK_I;`
73			`input RST_I;`
74			`output ACK_O;`
75			input `WB_ADDR_TYPE ADR_I;
76			`input CYC_I;`
77			output `WB_DATA_TYPE DAT_O;
78			input `WB_DATA_TYPE DAT_I;
79			`output ERR_O;`
80			`output RTY_O;`
81			input `WB_SEL_TYPE SEL_I;
82			`input STB_I;`
83			`input WE_I;`
84			`input CAB_I;`
85
86			reg `WB_DATA_TYPE DAT_O;
87
88			`/*------------------------------------------------------------------------------------------------------`
89			`Asynchronous dual-port RAM signals for storing and fetching the data`
90			`------------------------------------------------------------------------------------------------------*/`
91			//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
92			reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
93			reg `WB_DATA_TYPE mem_wr_data_out;
94			reg `WB_DATA_TYPE mem_rd_data_in;
95
96			`/*------------------------------------------------------------------------------------------------------`
97			`Maximum values for WAIT and RETRY counters and which response !!!`
98			`------------------------------------------------------------------------------------------------------*/`
99			`reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !`
100			`reg [7:0] wait_cyc;`
101			`reg [7:0] max_retry;`
102
103			`// assign registers to default state while in reset`
104			`// always@(RST_I)`
105			`// begin`
106			`// if (RST_I)`
107			`// begin`
108			`// a_e_r_resp <= 3'b000; // do not respond`
109			`// wait_cyc <= 8'b0; // no wait cycles`
110			`// max_retry <= 8'h0; // no retries`
111			`// end`
112			`// end //reset`
113
114			`task cycle_response;`
115			`input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags`
116			`input [7:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)`
117			`input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle`
118			`begin`
119			`// assign values`
120			`a_e_r_resp <= #1 ack_err_rty_resp;`
121			`wait_cyc <= #1 wait_cycles;`
122			`max_retry <= #1 retry_cycles;`
123			`end`
124			`endtask // cycle_response`
125
126			`/*------------------------------------------------------------------------------------------------------`
127			`Tasks for writing and reading to and from memory !!!`
128			`------------------------------------------------------------------------------------------------------*/`
129			reg `WB_ADDR_TYPE task_wr_adr_i;
130			reg `WB_ADDR_TYPE task_rd_adr_i;
131			reg `WB_DATA_TYPE task_dat_i;
132			reg `WB_DATA_TYPE task_dat_o;
133			reg `WB_SEL_TYPE task_sel_i;
134			`reg task_wr_data;`
135			`reg task_data_written;`
136			reg `WB_DATA_TYPE task_mem_wr_data;
137
138			`// write to memory`
139			`task wr_mem;`
140			input `WB_ADDR_TYPE adr_i;
141			input `WB_DATA_TYPE dat_i;
142			input `WB_SEL_TYPE sel_i;
143			`begin`
144			`task_data_written = 0;`
145			`task_wr_adr_i = adr_i;`
146			`task_dat_i = dat_i;`
147			`task_sel_i = sel_i;`
148			`task_wr_data = 1;`
149			`wait(task_data_written);`
150			`task_wr_data = 0;`
151			`end`
152			`endtask`
153
154			`// read from memory`
155			`task rd_mem;`
156			input `WB_ADDR_TYPE adr_i;
157			output `WB_DATA_TYPE dat_o;
158			input `WB_SEL_TYPE sel_i;
159			`begin`
160			`task_rd_adr_i = adr_i;`
161			`task_sel_i = sel_i;`
162			`#1;`
163			`dat_o = task_dat_o;`
164			`end`
165			`endtask`
166
167			`/*------------------------------------------------------------------------------------------------------`
168			`Internal signals and logic`
169			`------------------------------------------------------------------------------------------------------*/`
170			`reg calc_ack;`
171			`reg calc_err;`
172			`reg calc_rty;`
173
174			`reg [7:0] retry_cnt;`
175			`reg [7:0] retry_num;`
176			`reg retry_expired;`
177
178			`// Retry counter`
179			`always@(posedge RST_I or posedge CLK_I)`
180			`begin`
181			`if (RST_I)`
182			`retry_cnt <= #1 8'h00;`
183			`else`
184			`begin`
185			`if (calc_ack \|\| calc_err)`
186			`retry_cnt <= #1 8'h00;`
187			`else if (calc_rty)`
188			`retry_cnt <= #1 retry_num;`
189			`end`
190			`end`
191
192			`always@(retry_cnt or max_retry)`
193			`begin`
194			`if (retry_cnt < max_retry)`
195			`begin`
196			`retry_num = retry_cnt + 1'b1;`
197			`retry_expired = 1'b0;`
198			`end`
199			`else`
200			`begin`
201			`retry_num = retry_cnt;`
202			`retry_expired = 1'b1;`
203			`end`
204			`end`
205
206			`reg [7:0] wait_cnt;`
207			`reg [7:0] wait_num;`
208			`reg wait_expired;`
209
210			`// Wait counter`
211			`always@(posedge RST_I or posedge CLK_I)`
212			`begin`
213			`if (RST_I)`
214			`wait_cnt <= #1 8'h0;`
215			`else`
216			`begin`
217			`if (wait_expired \|\| ~STB_I)`
218			`wait_cnt <= #1 8'h0;`
219			`else`
220			`wait_cnt <= #1 wait_num;`
221			`end`
222			`end`
223
224			`always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)`
225			`begin`
226			`if ((wait_cyc > 0) && (STB_I))`
227			`begin`
228			`if (wait_cnt < wait_cyc)`
229			`begin`
230			`wait_num = wait_cnt + 1'b1;`
231			`wait_expired = 1'b0;`
232			`calc_ack = 1'b0;`
233			`calc_err = 1'b0;`
234			`calc_rty = 1'b0;`
235			`end`
236			`else`
237			`begin`
238			`wait_num = wait_cnt;`
239			`wait_expired = 1'b1;`
240			`if (a_e_r_resp == 3'b100)`
241			`begin`
242			`calc_ack = 1'b1;`
243			`calc_err = 1'b0;`
244			`calc_rty = 1'b0;`
245			`end`
246			`else`
247			`if (a_e_r_resp == 3'b010)`
248			`begin`
249			`calc_ack = 1'b0;`
250			`calc_err = 1'b1;`
251			`calc_rty = 1'b0;`
252			`end`
253			`else`
254			`if (a_e_r_resp == 3'b001)`
255			`begin`
256			`calc_err = 1'b0;`
257			`if (retry_expired)`
258			`begin`
259			`calc_ack = 1'b1;`
260			`calc_rty = 1'b0;`
261			`end`
262			`else`
263			`begin`
264			`calc_ack = 1'b0;`
265			`calc_rty = 1'b1;`
266			`end`
267			`end`
268			`else`
269			`begin`
270			`calc_ack = 1'b0;`
271			`calc_err = 1'b0;`
272			`calc_rty = 1'b0;`
273			`end`
274			`end`
275			`end`
276			`else`
277			`if ((wait_cyc == 0) && (STB_I))`
278			`begin`
279			`wait_num = 8'h0;`
280			`wait_expired = 1'b1;`
281			`if (a_e_r_resp == 3'b100)`
282			`begin`
283			`calc_ack = 1'b1;`
284			`calc_err = 1'b0;`
285			`calc_rty = 1'b0;`
286			`end`
287			`else if (a_e_r_resp == 3'b010)`
288			`begin`
289			`calc_ack = 1'b0;`
290			`calc_err = 1'b1;`
291			`calc_rty = 1'b0;`
292			`end`
293			`else if (a_e_r_resp == 3'b001)`
294			`begin`
295			`calc_err = 1'b0;`
296			`if (retry_expired)`
297			`begin`
298			`calc_ack = 1'b1;`
299			`calc_rty = 1'b0;`
300			`end`
301			`else`
302			`begin`
303			`calc_ack = 1'b0;`
304			`calc_rty = 1'b1;`
305			`end`
306			`end`
307			`else`
308			`begin`
309			`calc_ack = 1'b0;`
310			`calc_err = 1'b0;`
311			`calc_rty = 1'b0;`
312			`end`
313			`end`
314			`else`
315			`begin`
316			`wait_num = 8'h0;`
317			`wait_expired = 1'b0;`
318			`calc_ack = 1'b0;`
319			`calc_err = 1'b0;`
320			`calc_rty = 1'b0;`
321			`end`
322			`end`
323
324			`wire rd_sel = (CYC_I && STB_I && ~WE_I);`
325			`wire wr_sel = (CYC_I && STB_I && WE_I);`
326
327			`// Generate cycle termination signals`
328			`assign ACK_O = calc_ack && STB_I;`
329			`assign ERR_O = calc_err && STB_I;`
330			`assign RTY_O = calc_rty && STB_I;`
331
332			`// Assign address to asynchronous memory`
333			`always@(RST_I or ADR_I)`
334			`begin`
335			`if (RST_I) // this is added because at start of test bench we need address change in order to get data!`
336			`begin`
337			#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
338			`end`
339			`else`
340			`begin`
341			`// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];`
342			`#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];`
343			`end`
344			`end`
345
346			`// Data input/output interface`
347			`always@(rd_sel or mem_rd_data_in or RST_I)`
348			`begin`
349			`if (RST_I)`
350			DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
351			`else if (rd_sel)`
352			`DAT_O <=#1 mem_rd_data_in;`
353			`else`
354			DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
355			`end`
356
357
358			`always@(RST_I or task_rd_adr_i)`
359			`begin`
360			`if (RST_I)`
361			task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
362			`else`
363			`task_dat_o = wb_memory[task_rd_adr_i[21:2]];`
364			`end`
365			`always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or`
366			`mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or`
367			`SEL_I or task_sel_i)`
368			`begin`
369			`if (task_wr_data)`
370			`begin`
371			`task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];`
372
373			`if (task_sel_i[3])`
374			`task_mem_wr_data[31:24] = task_dat_i[31:24];`
375			`if (task_sel_i[2])`
376			`task_mem_wr_data[23:16] = task_dat_i[23:16];`
377			`if (task_sel_i[1])`
378			`task_mem_wr_data[15: 8] = task_dat_i[15: 8];`
379			`if (task_sel_i[0])`
380			`task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];`
381
382			`wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data`
383			`task_data_written = 1;`
384			`end`
385			`else if (wr_sel && CLK_I)`
386			`begin`
387			`// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written`
388			`mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written`
389
390			`if (SEL_I[3])`
391			`mem_wr_data_out[31:24] = DAT_I[31:24];`
392			`if (SEL_I[2])`
393			`mem_wr_data_out[23:16] = DAT_I[23:16];`
394			`if (SEL_I[1])`
395			`mem_wr_data_out[15: 8] = DAT_I[15: 8];`
396			`if (SEL_I[0])`
397			`mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];`
398
399			`// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data`
400			`wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data`
401			`end`
402			`end`
403
404			`endmodule`