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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2004/01/22 13:58:53  mohor
// Port signals are all set to zero after reset.
//
// Revision 1.5  2004/01/19 07:32:41  simons
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
//
// Revision 1.4  2004/01/17 18:38:11  mohor
// cpu_tall_o is set with cpu_stb_o or register.
//
// Revision 1.3  2004/01/17 18:01:24  mohor
// New version.
//
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:31  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
// Top module
module dbg_cpu(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                cpu_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
 
                // CPU signals
                cpu_clk_i,
                cpu_addr_o,
                cpu_data_i,
                cpu_data_o,
                cpu_bp_i,
                cpu_stall_o,
                cpu_stall_all_o,
                cpu_stb_o,
                cpu_sel_o,          // Not synchronized
                cpu_we_o,
                cpu_ack_i,
                cpu_rst_o
 
 
              );
 
// JTAG signals
input         tck_i;
input         tdi_i;
output        tdo_o;
 
// TAP states
input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;
 
input         cpu_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;
 
 
// CPU signals
input         cpu_clk_i;
output [31:0] cpu_addr_o;
input  [31:0] cpu_data_i;
output [31:0] cpu_data_o;
input         cpu_bp_i;
output        cpu_stall_o;
output        cpu_stall_all_o;
output        cpu_stb_o;
output [`CPU_NUM -1:0]  cpu_sel_o;
output        cpu_we_o;
input         cpu_ack_i;
output        cpu_rst_o;
 
 
 
reg           tdo_o;
 
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_cnt_en;
reg     [5:0] addr_cnt;
reg     [5:0] addr_cnt_limit;
wire          addr_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg     [5:0] data_cnt;
reg     [5:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
wire          status_cnt_end;
reg           status_cnt1, status_cnt2, status_cnt3, status_cnt4;
reg     [3:0] status;
 
reg           crc_match_reg;
wire          enable;
 
reg           read_cycle_reg;
reg           read_cycle_reg_q;
reg           read_cycle_cpu;
reg           read_cycle_cpu_q;
reg           write_cycle_reg;
reg           write_cycle_cpu;
wire          read_cycle;
wire          write_cycle;
 
reg    [31:0] dr;
wire    [7:0] reg_data_out;
 
wire          dr_read_reg;
wire          dr_write_reg;
wire          dr_read_cpu8;
wire          dr_read_cpu32;
wire          dr_write_cpu8;
wire          dr_write_cpu32;
wire          dr_go;
 
reg           dr_read_reg_latched;
reg           dr_write_reg_latched;
reg           dr_read_cpu8_latched;
reg           dr_read_cpu32_latched;
reg           dr_write_cpu8_latched;
reg           dr_write_cpu32_latched;
reg           dr_go_latched;
 
reg           cmd_read_reg;
reg           cmd_read_cpu;
reg           cmd_write_reg;
reg           cmd_write_cpu;
reg           cycle_32_bit;
reg           reg_access;
 
reg    [31:0] adr;
reg           cpu_ack_sync;
reg           cpu_ack_tck;
reg           cpu_ack_tck_q;
reg           cpu_stb;
reg           cpu_stb_sync;
reg           cpu_stb_o;
wire          cpu_stall_tmp;
 
wire          go_prelim;
wire          crc_cnt_31;
 
 
 
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <= #1 2'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 2'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_cnt <= #1 6'h0;
  else if (update_dr_i)
    addr_cnt <= #1 6'h0;
  else if (addr_cnt_en)
    addr_cnt <= #1 addr_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <= #1 6'h0;
  else if (update_dr_i)
    data_cnt <= #1 6'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end  & (~write_cycle) | (data_cnt_end & write_cycle));
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <= #1 6'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 6'h0;
end
 
 
// Upper limit. Address/length counter counts until this value is reached
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_cnt_limit = 6'd0;
  else if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))                                   // (current command is WB_STATUS or WB_GO)
        addr_cnt_limit = 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_cnt_limit = 6'd32;
    end
end
 
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_cnt_end = addr_cnt == addr_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign crc_cnt_31 = crc_cnt  == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      crc_cnt_end_q  <= #1 1'b0;
      cmd_cnt_end_q  <= #1 1'b0;
      data_cnt_end_q <= #1 1'b0;
    end
  else
    begin
      crc_cnt_end_q  <= #1 crc_cnt_end;
      cmd_cnt_end_q  <= #1 cmd_cnt_end;
      data_cnt_end_q <= #1 data_cnt_end;
    end
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & read_cycle |
           crc_cnt_end & (~read_cycle)
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
assign status_cnt_end = status_cnt4;
 
 
 
 
// Latching address
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    adr <= #1 32'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))
    adr <= #1 dr[31:0];
end
 
 
assign cpu_addr_o = adr;
 
 
// Shift register for shifting in and out the data
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    dr <= #1 32'h0;
  else if (reg_access)
    dr[31:24] <= #1 reg_data_out;
  else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
    begin
      if (cycle_32_bit)
        dr[31:0] <= #1 cpu_data_i;
      else
        dr[31:24] <= #1 cpu_data_i[7:0];
    end
  else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
    begin
      dr <= #1 {dr[30:0], tdi_i};
    end
end
 
 
assign dr_read_reg    = dr[2:0] == `CPU_READ_REG;
assign dr_write_reg   = dr[2:0] == `CPU_WRITE_REG;
assign dr_read_cpu8   = dr[2:0] == `CPU_READ8;
assign dr_read_cpu32  = dr[2:0] == `CPU_READ32;
assign dr_write_cpu8  = dr[2:0] == `CPU_WRITE8;
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
assign dr_go          = dr[2:0] == `CPU_GO;
 
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      dr_read_reg_latched  <= #1 1'b0;
      dr_read_cpu8_latched  <= #1 1'b0;
      dr_read_cpu32_latched  <= #1 1'b0;
      dr_write_reg_latched  <= #1 1'b0;
      dr_write_cpu8_latched  <= #1 1'b0;
      dr_write_cpu32_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      dr_read_reg_latched  <= #1 1'b0;
      dr_read_cpu8_latched  <= #1 1'b0;
      dr_read_cpu32_latched  <= #1 1'b0;
      dr_write_reg_latched  <= #1 1'b0;
      dr_write_cpu8_latched  <= #1 1'b0;
      dr_write_cpu32_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_read_reg_latched <= #1 dr_read_reg;
      dr_read_cpu8_latched <= #1 dr_read_cpu8;
      dr_read_cpu32_latched <= #1 dr_read_cpu32;
      dr_write_reg_latched <= #1 dr_write_reg;
      dr_write_cpu8_latched <= #1 dr_write_cpu8;
      dr_write_cpu32_latched <= #1 dr_write_cpu32;
      dr_go_latched <= #1 dr_go;
    end
end
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cmd_read_reg    <= #1 1'b0;
      cmd_read_cpu    <= #1 1'b0;
      cmd_write_reg   <= #1 1'b0;
      cmd_write_cpu   <= #1 1'b0;
      cycle_32_bit    <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd_read_reg    <= #1 dr_read_reg_latched;
      cmd_read_cpu    <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
      cmd_write_reg   <= #1 dr_write_reg_latched;
      cmd_write_cpu   <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
      cycle_32_bit    <= #1 dr_read_cpu32_latched | dr_write_cpu32_latched;
    end
end
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <= #1 6'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))
    begin
      if (dr_read_cpu32_latched | dr_write_cpu32_latched)
        data_cnt_limit <= #1 6'd32;
      else
        data_cnt_limit <= #1 6'd8;
    end
end
 
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    read_cycle_reg <= #1 1'b0;
  else if (update_dr_i)
    read_cycle_reg <= #1 1'b0;
  else if (cmd_read_reg & go_prelim)
    read_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    read_cycle_cpu <= #1 1'b0;
  else if (update_dr_i)
    read_cycle_cpu <= #1 1'b0;
  else if (cmd_read_cpu & go_prelim)
    read_cycle_cpu <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      read_cycle_reg_q <= #1 1'b0;
      read_cycle_cpu_q <= #1 1'b0;
    end
  else
    begin
      read_cycle_reg_q <= #1 read_cycle_reg;
      read_cycle_cpu_q <= #1 read_cycle_cpu;
    end
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    write_cycle_reg <= #1 1'b0;
  else if (update_dr_i)
    write_cycle_reg <= #1 1'b0;
  else if (cmd_write_reg & go_prelim)
    write_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    write_cycle_cpu <= #1 1'b0;
  else if (update_dr_i)
    write_cycle_cpu <= #1 1'b0;
  else if (cmd_write_cpu & go_prelim)
    write_cycle_cpu <= #1 1'b1;
end
 
 
assign read_cycle = read_cycle_reg | read_cycle_cpu;
assign write_cycle = write_cycle_reg | write_cycle_cpu;
 
 
 
// Start register access cycle
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    reg_access <= #1 1'b0;
  else if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q))
    reg_access <= #1 1'b1;
  else
    reg_access <= #1 1'b0;
end
 
 
 
// Connecting dbg_cpu_registers
dbg_cpu_registers i_dbg_cpu_registers
     (
      .data_i           (dr[7:0]),
      .data_o           (reg_data_out),
      .addr_i           (adr[1:0]),
      .we_i             (write_cycle_reg),
      .en_i             (reg_access),
      .clk_i            (tck_i),
      .bp_i             (cpu_bp_i),
      .rst_i            (rst_i),
      .cpu_clk_i        (cpu_clk_i),
      .cpu_stall_o      (cpu_stall_tmp),
      .cpu_stall_all_o  (cpu_stall_all_o),
      .cpu_sel_o        (cpu_sel_o),
      .cpu_rst_o        (cpu_rst_o)
     );
 
 
 
assign cpu_we_o   = write_cycle_cpu;
assign cpu_data_o = dr[31:0];
assign cpu_stall_o = cpu_stb_o | cpu_stall_tmp;
 
 
 
// Synchronizing ack signal from cpu
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_ack_sync      <= #1 1'b0;
      cpu_ack_tck       <= #1 1'b0;
      cpu_ack_tck_q     <= #1 1'b0;
    end
  else
    begin
      cpu_ack_sync      <= #1 cpu_ack_i;
      cpu_ack_tck       <= #1 cpu_ack_sync;
      cpu_ack_tck_q     <= #1 cpu_ack_tck;
    end
end
 
 
 
// Start cpu access cycle
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cpu_stb <= #1 1'b0;
  else if (update_dr_i | cpu_ack_tck)
    cpu_stb <= #1 1'b0;
  else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) | read_cycle_cpu & (~read_cycle_cpu_q))
    cpu_stb <= #1 1'b1;
end
 
 
 
// Synchronizing cpu_stb to cpu_clk_i clock
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_stb_sync  <= #1 1'b0;
      cpu_stb_o     <= #1 1'b0;
    end
  else
    begin
      cpu_stb_sync  <= #1 cpu_stb;
      cpu_stb_o     <= #1 cpu_stb_sync;
    end
end
 
 
// Latching crc
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_match_reg <= #1 1'b0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <= #1 crc_match_i;
end
 
 
 
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status <= #1 4'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
    status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
  else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
    status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[3:1]};
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1'b0
// 3. bit:          1'b1
// 4. bit:          1'b0
 
 
 
// TDO multiplexer
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or data_cnt_end or data_cnt_end_q or
          read_cycle or crc_match_reg or status or dr)
begin
  if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
    begin
      tdo_o = crc_match_i;
    end
  else if (read_cycle & crc_cnt_end & (~data_cnt_end))
    begin
    tdo_o = dr[31];
    end
  else if (read_cycle & data_cnt_end & (~data_cnt_end_q))     // cmd is already updated
    begin
      tdo_o = crc_match_reg;
    end
  else if (crc_cnt_end)
    begin
      tdo_o = status[0];
    end
  else
    begin
      tdo_o = 1'b0;
    end
end
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	123	mohor	`// Revision 1.6 2004/01/22 13:58:53 mohor`
47			`// Port signals are all set to zero after reset.`
48			`//`
49	121	mohor	`// Revision 1.5 2004/01/19 07:32:41 simons`
50			`// Reset values width added because of FV, a good sentence changed because some tools can not handle it.`
51			`//`
52	108	simons	`// Revision 1.4 2004/01/17 18:38:11 mohor`
53			`// cpu_tall_o is set with cpu_stb_o or register.`
54			`//`
55	104	mohor	`// Revision 1.3 2004/01/17 18:01:24 mohor`
56			`// New version.`
57			`//`
58	102	mohor	`// Revision 1.2 2004/01/17 17:01:14 mohor`
59			`// Almost finished.`
60			`//`
61	101	mohor	`// Revision 1.1 2004/01/16 14:53:31 mohor`
62			`// * empty log message *`
63	100	mohor	`//`
64			`//`
65	101	mohor	`//`
66	100	mohor
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "dbg_cpu_defines.v"
71
72			`// Top module`
73			`module dbg_cpu(`
74			`// JTAG signals`
75			`tck_i,`
76			`tdi_i,`
77			`tdo_o,`
78
79			`// TAP states`
80			`shift_dr_i,`
81			`pause_dr_i,`
82			`update_dr_i,`
83
84			`cpu_ce_i,`
85			`crc_match_i,`
86			`crc_en_o,`
87			`shift_crc_o,`
88			`rst_i,`
89
90	101	mohor	`// CPU signals`
91			`cpu_clk_i,`
92			`cpu_addr_o,`
93			`cpu_data_i,`
94			`cpu_data_o,`
95			`cpu_bp_i,`
96			`cpu_stall_o,`
97			`cpu_stall_all_o,`
98			`cpu_stb_o,`
99			`cpu_sel_o, // Not synchronized`
100			`cpu_we_o,`
101			`cpu_ack_i,`
102			`cpu_rst_o`
103	100	mohor
104	101	mohor
105	100	mohor	`);`
106
107			`// JTAG signals`
108			`input tck_i;`
109			`input tdi_i;`
110			`output tdo_o;`
111
112			`// TAP states`
113			`input shift_dr_i;`
114			`input pause_dr_i;`
115			`input update_dr_i;`
116
117			`input cpu_ce_i;`
118			`input crc_match_i;`
119			`output crc_en_o;`
120			`output shift_crc_o;`
121			`input rst_i;`
122	101	mohor
123
124			`// CPU signals`
125			`input cpu_clk_i;`
126			`output [31:0] cpu_addr_o;`
127			`input [31:0] cpu_data_i;`
128			`output [31:0] cpu_data_o;`
129			`input cpu_bp_i;`
130			`output cpu_stall_o;`
131			`output cpu_stall_all_o;`
132			`output cpu_stb_o;`
133			output [`CPU_NUM -1:0] cpu_sel_o;
134			`output cpu_we_o;`
135			`input cpu_ack_i;`
136			`output cpu_rst_o;`
137
138
139	100	mohor
140			`reg tdo_o;`
141
142			`wire cmd_cnt_en;`
143			`reg [1:0] cmd_cnt;`
144			`wire cmd_cnt_end;`
145			`reg cmd_cnt_end_q;`
146			`wire addr_cnt_en;`
147			`reg [5:0] addr_cnt;`
148			`reg [5:0] addr_cnt_limit;`
149			`wire addr_cnt_end;`
150			`wire crc_cnt_en;`
151			`reg [5:0] crc_cnt;`
152			`wire crc_cnt_end;`
153			`reg crc_cnt_end_q;`
154			`wire data_cnt_en;`
155			`reg [5:0] data_cnt;`
156			`reg [5:0] data_cnt_limit;`
157			`wire data_cnt_end;`
158			`reg data_cnt_end_q;`
159			`wire status_cnt_end;`
160			`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
161			`reg [3:0] status;`
162
163	102	mohor	`reg crc_match_reg;`
164	100	mohor	`wire enable;`
165
166			`reg read_cycle_reg;`
167	101	mohor	`reg read_cycle_reg_q;`
168	100	mohor	`reg read_cycle_cpu;`
169	101	mohor	`reg read_cycle_cpu_q;`
170	100	mohor	`reg write_cycle_reg;`
171			`reg write_cycle_cpu;`
172			`wire read_cycle;`
173			`wire write_cycle;`
174
175	121	mohor	`reg [31:0] dr;`
176	101	mohor	`wire [7:0] reg_data_out;`
177	100	mohor
178			`wire dr_read_reg;`
179			`wire dr_write_reg;`
180			`wire dr_read_cpu8;`
181			`wire dr_read_cpu32;`
182			`wire dr_write_cpu8;`
183			`wire dr_write_cpu32;`
184			`wire dr_go;`
185
186			`reg dr_read_reg_latched;`
187			`reg dr_write_reg_latched;`
188			`reg dr_read_cpu8_latched;`
189			`reg dr_read_cpu32_latched;`
190			`reg dr_write_cpu8_latched;`
191			`reg dr_write_cpu32_latched;`
192			`reg dr_go_latched;`
193
194			`reg cmd_read_reg;`
195			`reg cmd_read_cpu;`
196			`reg cmd_write_reg;`
197			`reg cmd_write_cpu;`
198	101	mohor	`reg cycle_32_bit;`
199			`reg reg_access;`
200	100	mohor
201	104	mohor	`reg [31:0] adr;`
202			`reg cpu_ack_sync;`
203			`reg cpu_ack_tck;`
204			`reg cpu_ack_tck_q;`
205			`reg cpu_stb;`
206			`reg cpu_stb_sync;`
207			`reg cpu_stb_o;`
208			`wire cpu_stall_tmp;`
209	101	mohor
210	100	mohor	`wire go_prelim;`
211			`wire crc_cnt_31;`
212
213
214	101	mohor
215	100	mohor	`assign enable = cpu_ce_i & shift_dr_i;`
216			`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
217			`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
218
219
220			`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
221
222
223			`// Command counter`
224			`always @ (posedge tck_i or posedge rst_i)`
225			`begin`
226			`if (rst_i)`
227	108	simons	`cmd_cnt <= #1 2'h0;`
228	100	mohor	`else if (update_dr_i)`
229	108	simons	`cmd_cnt <= #1 2'h0;`
230	100	mohor	`else if (cmd_cnt_en)`
231			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
232			`end`
233
234
235			`assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);`
236
237
238			`// Address/length counter`
239			`always @ (posedge tck_i or posedge rst_i)`
240			`begin`
241			`if (rst_i)`
242	108	simons	`addr_cnt <= #1 6'h0;`
243	100	mohor	`else if (update_dr_i)`
244	108	simons	`addr_cnt <= #1 6'h0;`
245	100	mohor	`else if (addr_cnt_en)`
246			`addr_cnt <= #1 addr_cnt + 1'b1;`
247			`end`
248
249
250			`assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle \| crc_cnt_end & read_cycle);`
251
252
253			`// Data counter`
254			`always @ (posedge tck_i or posedge rst_i)`
255			`begin`
256			`if (rst_i)`
257	108	simons	`data_cnt <= #1 6'h0;`
258	100	mohor	`else if (update_dr_i)`
259	108	simons	`data_cnt <= #1 6'h0;`
260	100	mohor	`else if (data_cnt_en)`
261			`data_cnt <= #1 data_cnt + 1'b1;`
262			`end`
263
264
265			`assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end & (~write_cycle) \| (data_cnt_end & write_cycle));`
266
267
268			`// crc counter`
269			`always @ (posedge tck_i or posedge rst_i)`
270			`begin`
271			`if (rst_i)`
272	108	simons	`crc_cnt <= #1 6'h0;`
273	100	mohor	`else if(crc_cnt_en)`
274			`crc_cnt <= #1 crc_cnt + 1'b1;`
275			`else if (update_dr_i)`
276	108	simons	`crc_cnt <= #1 6'h0;`
277	100	mohor	`end`
278
279
280			`// Upper limit. Address/length counter counts until this value is reached`
281	123	mohor	`always @ (posedge tck_i or posedge rst_i)`
282	100	mohor	`begin`
283	123	mohor	`if (rst_i)`
284			`addr_cnt_limit = 6'd0;`
285			`else if (cmd_cnt == 2'h2)`
286	100	mohor	`begin`
287			`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
288			`addr_cnt_limit = 6'd0;`
289			`else // (current command is WB_WRITEx or WB_READx)`
290			`addr_cnt_limit = 6'd32;`
291			`end`
292			`end`
293
294
295			`assign cmd_cnt_end = cmd_cnt == 2'h3;`
296			`assign addr_cnt_end = addr_cnt == addr_cnt_limit;`
297			`assign crc_cnt_end = crc_cnt == 6'd32;`
298			`assign crc_cnt_31 = crc_cnt == 6'd31;`
299			`assign data_cnt_end = (data_cnt == data_cnt_limit);`
300
301	123	mohor	`always @ (posedge tck_i or posedge rst_i)`
302	100	mohor	`begin`
303	123	mohor	`if (rst_i)`
304			`begin`
305			`crc_cnt_end_q <= #1 1'b0;`
306			`cmd_cnt_end_q <= #1 1'b0;`
307			`data_cnt_end_q <= #1 1'b0;`
308			`end`
309			`else`
310			`begin`
311			`crc_cnt_end_q <= #1 crc_cnt_end;`
312			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
313			`data_cnt_end_q <= #1 data_cnt_end;`
314			`end`
315	100	mohor	`end`
316
317
318			`// Status counter is made of 4 serialy connected registers`
319			`always @ (posedge tck_i or posedge rst_i)`
320			`begin`
321			`if (rst_i)`
322			`status_cnt1 <= #1 1'b0;`
323			`else if (update_dr_i)`
324			`status_cnt1 <= #1 1'b0;`
325			`else if (data_cnt_end & read_cycle \|`
326			`crc_cnt_end & (~read_cycle)`
327			`)`
328			`status_cnt1 <= #1 1'b1;`
329			`end`
330
331
332			`always @ (posedge tck_i or posedge rst_i)`
333			`begin`
334			`if (rst_i)`
335			`begin`
336			`status_cnt2 <= #1 1'b0;`
337			`status_cnt3 <= #1 1'b0;`
338			`status_cnt4 <= #1 1'b0;`
339			`end`
340			`else if (update_dr_i)`
341			`begin`
342			`status_cnt2 <= #1 1'b0;`
343			`status_cnt3 <= #1 1'b0;`
344			`status_cnt4 <= #1 1'b0;`
345			`end`
346			`else`
347			`begin`
348			`status_cnt2 <= #1 status_cnt1;`
349			`status_cnt3 <= #1 status_cnt2;`
350			`status_cnt4 <= #1 status_cnt3;`
351			`end`
352			`end`
353
354
355			`assign status_cnt_end = status_cnt4;`
356
357
358
359
360			`// Latching address`
361	121	mohor	`always @ (posedge tck_i or posedge rst_i)`
362	100	mohor	`begin`
363	121	mohor	`if (rst_i)`
364			`adr <= #1 32'h0;`
365			`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))`
366			`adr <= #1 dr[31:0];`
367	100	mohor	`end`
368
369
370	101	mohor	`assign cpu_addr_o = adr;`
371	100	mohor
372	101	mohor
373	100	mohor	`// Shift register for shifting in and out the data`
374	121	mohor	`always @ (posedge tck_i or posedge rst_i)`
375	100	mohor	`begin`
376	121	mohor	`if (rst_i)`
377			`dr <= #1 32'h0;`
378			`else if (reg_access)`
379			`dr[31:24] <= #1 reg_data_out;`
380	101	mohor	`else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)`
381			`begin`
382			`if (cycle_32_bit)`
383			`dr[31:0] <= #1 cpu_data_i;`
384			`else`
385			`dr[31:24] <= #1 cpu_data_i[7:0];`
386			`end`
387			`else if (enable & ((~addr_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle) \| (crc_cnt_end & (~data_cnt_end) & read_cycle)))`
388			`begin`
389	121	mohor	`dr <= #1 {dr[30:0], tdi_i};`
390	100	mohor	`end`
391			`end`
392
393
394			assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
395			assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
396			assign dr_read_cpu8 = dr[2:0] == `CPU_READ8;
397			assign dr_read_cpu32 = dr[2:0] == `CPU_READ32;
398			assign dr_write_cpu8 = dr[2:0] == `CPU_WRITE8;
399			assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
400			assign dr_go = dr[2:0] == `CPU_GO;
401
402
403			`// Latching instruction`
404	123	mohor	`always @ (posedge tck_i or posedge rst_i)`
405	100	mohor	`begin`
406	123	mohor	`if (rst_i)`
407	100	mohor	`begin`
408			`dr_read_reg_latched <= #1 1'b0;`
409			`dr_read_cpu8_latched <= #1 1'b0;`
410			`dr_read_cpu32_latched <= #1 1'b0;`
411			`dr_write_reg_latched <= #1 1'b0;`
412			`dr_write_cpu8_latched <= #1 1'b0;`
413			`dr_write_cpu32_latched <= #1 1'b0;`
414			`dr_go_latched <= #1 1'b0;`
415			`end`
416	123	mohor	`else if (update_dr_i)`
417			`begin`
418			`dr_read_reg_latched <= #1 1'b0;`
419			`dr_read_cpu8_latched <= #1 1'b0;`
420			`dr_read_cpu32_latched <= #1 1'b0;`
421			`dr_write_reg_latched <= #1 1'b0;`
422			`dr_write_cpu8_latched <= #1 1'b0;`
423			`dr_write_cpu32_latched <= #1 1'b0;`
424			`dr_go_latched <= #1 1'b0;`
425			`end`
426	100	mohor	`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
427			`begin`
428			`dr_read_reg_latched <= #1 dr_read_reg;`
429			`dr_read_cpu8_latched <= #1 dr_read_cpu8;`
430			`dr_read_cpu32_latched <= #1 dr_read_cpu32;`
431			`dr_write_reg_latched <= #1 dr_write_reg;`
432			`dr_write_cpu8_latched <= #1 dr_write_cpu8;`
433			`dr_write_cpu32_latched <= #1 dr_write_cpu32;`
434			`dr_go_latched <= #1 dr_go;`
435			`end`
436			`end`
437
438			`// Latching instruction`
439			`always @ (posedge tck_i or posedge rst_i)`
440			`begin`
441			`if (rst_i)`
442			`begin`
443			`cmd_read_reg <= #1 1'b0;`
444			`cmd_read_cpu <= #1 1'b0;`
445			`cmd_write_reg <= #1 1'b0;`
446	101	mohor	`cmd_write_cpu <= #1 1'b0;`
447			`cycle_32_bit <= #1 1'b0;`
448	100	mohor	`end`
449			`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
450			`begin`
451			`cmd_read_reg <= #1 dr_read_reg_latched;`
452			`cmd_read_cpu <= #1 dr_read_cpu8_latched \| dr_read_cpu32_latched;`
453			`cmd_write_reg <= #1 dr_write_reg_latched;`
454			`cmd_write_cpu <= #1 dr_write_cpu8_latched \| dr_write_cpu32_latched;`
455	101	mohor	`cycle_32_bit <= #1 dr_read_cpu32_latched \| dr_write_cpu32_latched;`
456	100	mohor	`end`
457			`end`
458
459
460			`// Upper limit. Data counter counts until this value is reached.`
461			`always @ (posedge tck_i or posedge rst_i)`
462			`begin`
463			`if (rst_i)`
464			`data_cnt_limit <= #1 6'h0;`
465	101	mohor	`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))`
466	100	mohor	`begin`
467			`if (dr_read_cpu32_latched \| dr_write_cpu32_latched)`
468			`data_cnt_limit <= #1 6'd32;`
469			`else`
470			`data_cnt_limit <= #1 6'd8;`
471			`end`
472			`end`
473
474
475			`assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);`
476
477
478	123	mohor	`always @ (posedge tck_i or posedge rst_i)`
479	100	mohor	`begin`
480	123	mohor	`if (rst_i)`
481	100	mohor	`read_cycle_reg <= #1 1'b0;`
482	123	mohor	`else if (update_dr_i)`
483			`read_cycle_reg <= #1 1'b0;`
484	100	mohor	`else if (cmd_read_reg & go_prelim)`
485			`read_cycle_reg <= #1 1'b1;`
486			`end`
487
488
489	123	mohor	`always @ (posedge tck_i or posedge rst_i)`
490	100	mohor	`begin`
491	123	mohor	`if (rst_i)`
492	100	mohor	`read_cycle_cpu <= #1 1'b0;`
493	123	mohor	`else if (update_dr_i)`
494			`read_cycle_cpu <= #1 1'b0;`
495	100	mohor	`else if (cmd_read_cpu & go_prelim)`
496			`read_cycle_cpu <= #1 1'b1;`
497			`end`
498
499
500	123	mohor	`always @ (posedge tck_i or posedge rst_i)`

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