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mohor |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_registers.v ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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simons |
// Revision 1.9 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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//
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simons |
// Revision 1.8 2002/10/10 02:42:55 mohor
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// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
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//
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mohor |
// Revision 1.7 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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mohor |
// Revision 1.6 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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//
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mohor |
// Revision 1.5 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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mohor |
// Revision 1.4 2001/10/19 11:40:02 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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//
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mohor |
// Revision 1.3 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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//
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mohor |
// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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mohor |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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mohor |
// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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// Revision 1.1.1.1 2001/05/18 06:35:10 mohor
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// Initial release
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//
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//
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mohor |
// synopsys translate_off
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mohor |
`include "timescale.v"
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mohor |
// synopsys translate_on
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2 |
mohor |
`include "dbg_defines.v"
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mohor |
module dbg_registers(data_in, data_out, address, rw, access, clk, bp, reset,
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mohor |
`ifdef TRACE_ENABLED
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ContinMode,
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mohor |
TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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mohor |
ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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mohor |
QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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RecordSDATA, RecordReadSPR, RecordWriteSPR, RecordINSTR,
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mohor |
WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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mohor |
LSSStopValid, IStopValid,
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mohor |
`endif
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simons |
risc_stall, risc_stall_all, risc_sel, risc_reset, mon_cntl_o
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mohor |
);
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parameter Tp = 1;
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mohor |
input [31:0] data_in;
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input [4:0] address;
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mohor |
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mohor |
input rw;
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input access;
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input clk;
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input bp;
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input reset;
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mohor |
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mohor |
output [31:0] data_out;
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reg [31:0] data_out;
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2 |
mohor |
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`ifdef TRACE_ENABLED
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output ContinMode;
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output TraceEnable;
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output [10:0] WpTrigger;
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output BpTrigger;
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output [3:0] LSSTrigger;
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output [1:0] ITrigger;
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output [1:0] TriggerOper;
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output WpTriggerValid;
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output BpTriggerValid;
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output LSSTriggerValid;
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output ITriggerValid;
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output [10:0] WpQualif;
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output BpQualif;
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output [3:0] LSSQualif;
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output [1:0] IQualif;
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output [1:0] QualifOper;
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output WpQualifValid;
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output BpQualifValid;
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output LSSQualifValid;
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output IQualifValid;
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output [10:0] WpStop;
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output BpStop;
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output [3:0] LSSStop;
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output [1:0] IStop;
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output [1:0] StopOper;
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output WpStopValid;
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output BpStopValid;
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output LSSStopValid;
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output IStopValid;
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mohor |
output RecordPC;
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output RecordLSEA;
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output RecordLDATA;
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output RecordSDATA;
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output RecordReadSPR;
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output RecordWriteSPR;
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output RecordINSTR;
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2 |
mohor |
`endif
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mohor |
output risc_stall;
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simons |
output risc_stall_all;
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output [`RISC_NUM-1:0] risc_sel;
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mohor |
output risc_reset;
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mohor |
output [3:0] mon_cntl_o;
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mohor |
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mohor |
wire MODER_Acc = (address == `MODER_ADR) & access;
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wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
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simons |
wire RISCSEL_Acc = (address == `RISCSEL_ADR) & access;
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mohor |
wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
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mohor |
`ifdef TRACE_ENABLED
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mohor |
wire TSEL_Acc = (address == `TSEL_ADR) & access;
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wire QSEL_Acc = (address == `QSEL_ADR) & access;
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wire SSEL_Acc = (address == `SSEL_ADR) & access;
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wire RECSEL_Acc = (address == `RECSEL_ADR) & access;
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mohor |
`endif
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mohor |
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mohor |
wire MODER_Wr = MODER_Acc & rw;
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wire RISCOP_Wr = RISCOP_Acc & rw;
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simons |
wire RISCSEL_Wr = RISCSEL_Acc & rw;
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mohor |
wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
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mohor |
`ifdef TRACE_ENABLED
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mohor |
wire TSEL_Wr = TSEL_Acc & rw;
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wire QSEL_Wr = QSEL_Acc & rw;
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wire SSEL_Wr = SSEL_Acc & rw;
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wire RECSEL_Wr = RECSEL_Acc & rw;
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mohor |
`endif
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mohor |
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mohor |
wire MODER_Rd = MODER_Acc & ~rw;
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wire RISCOP_Rd = RISCOP_Acc & ~rw;
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simons |
wire RISCSEL_Rd = RISCSEL_Acc & ~rw;
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mohor |
wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
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5 |
mohor |
`ifdef TRACE_ENABLED
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mohor |
wire TSEL_Rd = TSEL_Acc & ~rw;
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wire QSEL_Rd = QSEL_Acc & ~rw;
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wire SSEL_Rd = SSEL_Acc & ~rw;
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wire RECSEL_Rd = RECSEL_Acc & ~rw;
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mohor |
`endif
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simons |
wire [31:0] MODEROut;
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wire [2:1] RISCOPOut;
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wire [`RISC_NUM-1:0] RISCSELOut;
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wire [3:0] MONCNTLOut;
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5 |
mohor |
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2 |
mohor |
`ifdef TRACE_ENABLED
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simons |
wire [31:0] TSELOut;
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wire [31:0] QSELOut;
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wire [31:0] SSELOut;
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wire [6:0] RECSELOut;
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2 |
mohor |
`endif
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`ifdef TRACE_ENABLED
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mohor |
assign MODEROut[15:0] = 16'h0001;
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assign MODEROut[31:18] = 14'h0;
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`else
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assign MODEROut[31:0] = 32'h0000;
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mohor |
`endif
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mohor |
reg RiscStallBp;
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mohor |
always @(posedge clk or posedge reset)
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12 |
mohor |
begin
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mohor |
if(reset)
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12 |
mohor |
RiscStallBp <= 1'b0;
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else
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44 |
mohor |
if(bp) // Breakpoint sets bit
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12 |
mohor |
RiscStallBp <= 1'b1;
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else
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if(RISCOP_Wr) // Register access can set or clear bit
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44 |
mohor |
RiscStallBp <= data_in[0];
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12 |
mohor |
end
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5 |
mohor |
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57 |
simons |
dbg_register #(2, 0) RISCOP (.data_in(data_in[2:1]), .data_out(RISCOPOut[2:1]), .write(RISCOP_Wr), .clk(clk), .reset(reset));
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simons |
dbg_register #(`RISC_NUM, 1) RISCSEL (.data_in(data_in[`RISC_NUM-1:0]), .data_out(RISCSELOut), .write(RISCSEL_Wr), .clk(clk), .reset(reset));
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51 |
mohor |
dbg_register #(4, `MON_CNTL_DEF) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset));
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12 |
mohor |
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250 |
2 |
mohor |
`ifdef TRACE_ENABLED
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51 |
mohor |
dbg_register #(2, `MODER_DEF) MODER (.data_in(data_in[17:16]), .data_out(MODEROut[17:16]), .write(MODER_Wr), .clk(clk), .reset(reset));
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dbg_register #(32, `TSEL_DEF) TSEL (.data_in(data_in), .data_out(TSELOut), .write(TSEL_Wr), .clk(clk), .reset(reset));
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dbg_register #(32, `QSEL_DEF) QSEL (.data_in(data_in), .data_out(QSELOut), .write(QSEL_Wr), .clk(clk), .reset(reset));
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254 |
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dbg_register #(32, `SSEL_DEF) SSEL (.data_in(data_in), .data_out(SSELOut), .write(SSEL_Wr), .clk(clk), .reset(reset));
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dbg_register #(7, `RECSEL_DEF) RECSEL (.data_in(data_in[6:0]), .data_out(RECSELOut), .write(RECSEL_Wr), .clk(clk), .reset(reset));
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256 |
5 |
mohor |
`endif
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257 |
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258 |
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259 |
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260 |
44 |
mohor |
always @ (posedge clk)
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261 |
2 |
mohor |
begin
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262 |
44 |
mohor |
if(MODER_Rd) data_out<= #Tp MODEROut;
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263 |
2 |
mohor |
else
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264 |
57 |
simons |
if(RISCOP_Rd) data_out<= #Tp {29'h0, RISCOPOut[2:1], risc_stall};
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265 |
47 |
mohor |
else
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266 |
57 |
simons |
if(RISCSEL_Rd) data_out<= #Tp {{(32-`RISC_NUM){1'b0}}, RISCSELOut};
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267 |
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else
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268 |
47 |
mohor |
if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
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269 |
5 |
mohor |
`ifdef TRACE_ENABLED
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270 |
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else
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271 |
44 |
mohor |
if(TSEL_Rd) data_out<= #Tp TSELOut;
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272 |
2 |
mohor |
else
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273 |
44 |
mohor |
if(QSEL_Rd) data_out<= #Tp QSELOut;
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274 |
2 |
mohor |
else
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275 |
44 |
mohor |
if(SSEL_Rd) data_out<= #Tp SSELOut;
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276 |
2 |
mohor |
else
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277 |
44 |
mohor |
if(RECSEL_Rd) data_out<= #Tp {25'h0, RECSELOut};
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278 |
5 |
mohor |
`endif
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279 |
44 |
mohor |
else data_out<= #Tp 'h0;
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280 |
2 |
mohor |
end
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281 |
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282 |
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`ifdef TRACE_ENABLED
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283 |
5 |
mohor |
assign TraceEnable = MODEROut[16];
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284 |
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assign ContinMode = MODEROut[17];
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285 |
2 |
mohor |
|
286 |
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assign WpTrigger[10:0] = TSELOut[10:0];
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287 |
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assign WpTriggerValid = TSELOut[11];
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288 |
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assign BpTrigger = TSELOut[12];
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289 |
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assign BpTriggerValid = TSELOut[13];
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290 |
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assign LSSTrigger[3:0] = TSELOut[19:16];
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291 |
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assign LSSTriggerValid = TSELOut[20];
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292 |
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assign ITrigger[1:0] = TSELOut[22:21];
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293 |
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assign ITriggerValid = TSELOut[23];
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294 |
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assign TriggerOper[1:0] = TSELOut[31:30];
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295 |
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296 |
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assign WpQualif[10:0] = QSELOut[10:0];
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297 |
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assign WpQualifValid = QSELOut[11];
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298 |
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assign BpQualif = QSELOut[12];
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299 |
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assign BpQualifValid = QSELOut[13];
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300 |
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assign LSSQualif[3:0] = QSELOut[19:16];
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301 |
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assign LSSQualifValid = QSELOut[20];
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302 |
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assign IQualif[1:0] = QSELOut[22:21];
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303 |
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assign IQualifValid = QSELOut[23];
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304 |
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assign QualifOper[1:0] = QSELOut[31:30];
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305 |
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306 |
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assign WpStop[10:0] = SSELOut[10:0];
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307 |
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assign WpStopValid = SSELOut[11];
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308 |
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assign BpStop = SSELOut[12];
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309 |
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assign BpStopValid = SSELOut[13];
|
310 |
|
|
assign LSSStop[3:0] = SSELOut[19:16];
|
311 |
|
|
assign LSSStopValid = SSELOut[20];
|
312 |
|
|
assign IStop[1:0] = SSELOut[22:21];
|
313 |
|
|
assign IStopValid = SSELOut[23];
|
314 |
|
|
assign StopOper[1:0] = SSELOut[31:30];
|
315 |
|
|
|
316 |
|
|
|
317 |
5 |
mohor |
assign RecordPC = RECSELOut[0];
|
318 |
|
|
assign RecordLSEA = RECSELOut[1];
|
319 |
|
|
assign RecordLDATA = RECSELOut[2];
|
320 |
|
|
assign RecordSDATA = RECSELOut[3];
|
321 |
|
|
assign RecordReadSPR = RECSELOut[4];
|
322 |
|
|
assign RecordWriteSPR = RECSELOut[5];
|
323 |
|
|
assign RecordINSTR = RECSELOut[6];
|
324 |
2 |
mohor |
`endif
|
325 |
|
|
|
326 |
44 |
mohor |
assign risc_stall = bp | RiscStallBp; // bp asynchronously sets the risc_stall, then RiscStallBp (from register) holds it active
|
327 |
57 |
simons |
assign risc_stall_all = RISCOPOut[2]; // this signal is used to stall all the cpus except the one that is selected in riscsel register
|
328 |
|
|
assign risc_sel = RISCSELOut;
|
329 |
44 |
mohor |
assign risc_reset = RISCOPOut[1];
|
330 |
47 |
mohor |
assign mon_cntl_o = MONCNTLOut;
|
331 |
2 |
mohor |
|
332 |
|
|
endmodule
|