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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001, 2002 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
 
                // TAP states
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
 
                // Instructions
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
 
                // TDO from dbg module
                TDOData_dbg, BypassRegister,
 
                // From Boundary Scan Chain
                bs_chain_i
 
              );
 
parameter Tp = 1;
 
// JTAG pins
input   tms_pad_i;                  // JTAG test mode select pad
input   tck_pad_i;                  // JTAG test clock pad
input   trst_pad_i;                 // JTAG test reset pad
input   tdi_pad_i;                  // JTAG test data input pad
output  tdo_pad_o;                  // JTAG test data output pad
output  tdo_padoe_o;                // Output enable for JTAG test data output pad 
 
// TAP states
output  ShiftDR;
output  Exit1DR;
output  UpdateDR;
output  UpdateDR_q;
output  CaptureDR;
 
// Instructions
output  IDCODESelected;
output  CHAIN_SELECTSelected;
output  DEBUGSelected;
output  EXTESTSelected;
 
input   TDOData_dbg;
output  BypassRegister;
 
// From Boundary Scan Chain
input   bs_chain_i;
 
 
reg     tdo_pad_o;
 
// TAP states
reg     TestLogicReset;
reg     RunTestIdle;
reg     SelectDRScan;
reg     CaptureDR;
reg     ShiftDR;
reg     Exit1DR;
reg     PauseDR;
reg     Exit2DR;
reg     UpdateDR;
 
reg     SelectIRScan;
reg     CaptureIR;
reg     ShiftIR;
reg     Exit1IR;
reg     PauseIR;
reg     Exit2IR;
reg     UpdateIR;
 
 
// Defining which instruction is selected
reg     EXTESTSelected;
reg     SAMPLE_PRELOADSelected;
reg     IDCODESelected;
reg     CHAIN_SELECTSelected;
reg     INTESTSelected;
reg     CLAMPSelected;
reg     CLAMPZSelected;
reg     HIGHZSelected;
reg     DEBUGSelected;
reg     BYPASSSelected;
 
reg     BypassRegister;               // Bypass register
 
wire    trst;
wire    tck;
wire    TMS;
wire    tdi;
 
wire    RiscDebugScanChain;
wire    WishboneScanChain;
wire    RegisterScanChain;
 
 
assign trst = trst_pad_i;                // trst_pad_i is active high !!! Inverted on higher layer 
assign tck  = tck_pad_i;
assign TMS  = tms_pad_i;
assign tdi  = tdi_pad_i;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
  if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
    RunTestIdle<=#Tp 1;
  else
    RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
  if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
    SelectDRScan<=#Tp 1;
  else
    SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
  if(~TMS & SelectDRScan)
    CaptureDR<=#Tp 1;
  else
    CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
  if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
    ShiftDR<=#Tp 1;
  else
    ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
  if(TMS & (CaptureDR | ShiftDR))
    Exit1DR<=#Tp 1;
  else
    Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
  if(~TMS & (Exit1DR | PauseDR))
    PauseDR<=#Tp 1;
  else
    PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
  if(TMS & PauseDR)
    Exit2DR<=#Tp 1;
  else
    Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
  if(TMS & (Exit1DR | Exit2DR))
    UpdateDR<=#Tp 1;
  else
    UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
  if(TMS & SelectDRScan)
    SelectIRScan<=#Tp 1;
  else
    SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
  if(~TMS & SelectIRScan)
    CaptureIR<=#Tp 1;
  else
    CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
  if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
    ShiftIR<=#Tp 1;
  else
    ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
  if(TMS & (CaptureIR | ShiftIR))
    Exit1IR<=#Tp 1;
  else
    Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
  if(~TMS & (Exit1IR | PauseIR))
    PauseIR<=#Tp 1;
  else
    PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
  if(TMS & PauseIR)
    Exit2IR<=#Tp 1;
  else
    Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
  if(TMS & (Exit1IR | Exit2IR))
    UpdateIR<=#Tp 1;
  else
    UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
  if(CaptureIR)
    begin
      JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
      JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
    end
  else
  if(ShiftIR)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
 
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
    begin
      if(ShiftDR)
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
      else
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
    end
  else
  if(CHAIN_SELECTSelected & ShiftDR)
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
  else
  if(DEBUGSelected & ShiftDR)
    begin
      if(RiscDebugScanChain | WishboneScanChain)
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
      else
      if(RegisterScanChain)
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
    end
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
  if(ShiftDR)
    BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
  TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
begin
  if(ShiftIR | Exit1IR)
    tdo_pad_o <=#Tp TDOInstruction;
  else
    begin
      case(LatchedJTAG_IR)
        `IDCODE:            tdo_pad_o <=#Tp TDOData_dbg;      // Reading ID code
        `CHAIN_SELECT:      tdo_pad_o <=#Tp TDOData_dbg;      // Selecting the chain
        `DEBUG:             tdo_pad_o <=#Tp TDOData_dbg;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o <=#Tp bs_chain_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o <=#Tp bs_chain_i;   // External test
        default:            tdo_pad_o <=#Tp TDOBypassed;  // BYPASS instruction
      endcase
    end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoe_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

Line No.	Rev	Author	Line
1	36	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000, 2001, 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	53	mohor	`// Revision 1.6 2002/04/22 12:55:56 mohor`
49			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
50			`//`
51	45	mohor	`// Revision 1.5 2002/03/26 14:23:38 mohor`
52			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
53			`//`
54	40	mohor	`// Revision 1.4 2002/03/25 13:16:15 mohor`
55			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
56			`// not named correctly.`
57			`//`
58	39	mohor	`// Revision 1.3 2002/03/12 14:30:05 mohor`
59			`// Few outputs for boundary scan chain added.`
60			`//`
61	38	mohor	`// Revision 1.2 2002/03/12 10:31:53 mohor`
62			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
63			`// contains only tap state machine and related logic. dbg_top contains all`
64			`// logic necessery for debugging.`
65			`//`
66	37	mohor	`// Revision 1.1 2002/03/08 15:28:16 mohor`
67			`// Structure changed. Hooks for jtag chain added.`
68	36	mohor	`//`
69			`//`
70			`//`
71	37	mohor	`//`
72	36	mohor
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "dbg_defines.v"
77
78			`// Top module`
79			`module tap_top(`
80			`// JTAG pins`
81	45	mohor	`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,`
82	36	mohor
83	37	mohor	`// TAP states`
84	38	mohor	`ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,`
85	36	mohor
86	37	mohor	`// Instructions`
87	38	mohor	`IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,`
88	37	mohor
89			`// TDO from dbg module`
90	38	mohor	`TDOData_dbg, BypassRegister,`
91
92			`// From Boundary Scan Chain`
93			`bs_chain_i`
94
95	36	mohor	`);`
96
97			`parameter Tp = 1;`
98
99			`// JTAG pins`
100			`input tms_pad_i; // JTAG test mode select pad`
101			`input tck_pad_i; // JTAG test clock pad`
102			`input trst_pad_i; // JTAG test reset pad`
103			`input tdi_pad_i; // JTAG test data input pad`
104			`output tdo_pad_o; // JTAG test data output pad`
105	45	mohor	`output tdo_padoe_o; // Output enable for JTAG test data output pad`
106	36	mohor
107	37	mohor	`// TAP states`
108			`output ShiftDR;`
109			`output Exit1DR;`
110			`output UpdateDR;`
111			`output UpdateDR_q;`
112	38	mohor	`output CaptureDR;`
113	36	mohor
114	37	mohor	`// Instructions`
115			`output IDCODESelected;`
116			`output CHAIN_SELECTSelected;`
117			`output DEBUGSelected;`
118	38	mohor	`output EXTESTSelected;`
119	36	mohor
120	37	mohor	`input TDOData_dbg;`
121			`output BypassRegister;`
122	36	mohor
123	38	mohor	`// From Boundary Scan Chain`
124			`input bs_chain_i;`
125
126
127	36	mohor	`reg tdo_pad_o;`
128
129			`// TAP states`
130			`reg TestLogicReset;`
131			`reg RunTestIdle;`
132			`reg SelectDRScan;`
133			`reg CaptureDR;`
134			`reg ShiftDR;`
135			`reg Exit1DR;`
136			`reg PauseDR;`
137			`reg Exit2DR;`
138			`reg UpdateDR;`
139
140			`reg SelectIRScan;`
141			`reg CaptureIR;`
142			`reg ShiftIR;`
143			`reg Exit1IR;`
144			`reg PauseIR;`
145			`reg Exit2IR;`
146			`reg UpdateIR;`
147
148
149			`// Defining which instruction is selected`
150			`reg EXTESTSelected;`
151			`reg SAMPLE_PRELOADSelected;`
152			`reg IDCODESelected;`
153			`reg CHAIN_SELECTSelected;`
154			`reg INTESTSelected;`
155			`reg CLAMPSelected;`
156			`reg CLAMPZSelected;`
157			`reg HIGHZSelected;`
158			`reg DEBUGSelected;`
159			`reg BYPASSSelected;`
160
161			`reg BypassRegister; // Bypass register`
162
163	53	mohor	`wire trst;`
164	36	mohor	`wire tck;`
165			`wire TMS;`
166			`wire tdi;`
167
168			`wire RiscDebugScanChain;`
169			`wire WishboneScanChain;`
170			`wire RegisterScanChain;`
171
172
173	53	mohor	`assign trst = trst_pad_i; // trst_pad_i is active high !!! Inverted on higher layer`
174	36	mohor	`assign tck = tck_pad_i;`
175			`assign TMS = tms_pad_i;`
176			`assign tdi = tdi_pad_i;`
177
178
179			`/**********************************************************************************`
180			`* *`
181			`* TAP State Machine: Fully JTAG compliant *`
182			`* *`
183			`**********************************************************************************/`
184
185			`// TestLogicReset state`
186			`always @ (posedge tck or posedge trst)`
187			`begin`
188			`if(trst)`
189			`TestLogicReset<=#Tp 1;`
190			`else`
191			`begin`
192			`if(TMS & (TestLogicReset \| SelectIRScan))`
193			`TestLogicReset<=#Tp 1;`
194			`else`
195			`TestLogicReset<=#Tp 0;`
196			`end`
197			`end`
198
199			`// RunTestIdle state`
200			`always @ (posedge tck or posedge trst)`
201			`begin`
202			`if(trst)`
203			`RunTestIdle<=#Tp 0;`
204			`else`
205			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
206			`RunTestIdle<=#Tp 1;`
207			`else`
208			`RunTestIdle<=#Tp 0;`
209			`end`
210
211			`// SelectDRScan state`
212			`always @ (posedge tck or posedge trst)`
213			`begin`
214			`if(trst)`
215			`SelectDRScan<=#Tp 0;`
216			`else`
217			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
218			`SelectDRScan<=#Tp 1;`
219			`else`
220			`SelectDRScan<=#Tp 0;`
221			`end`
222
223			`// CaptureDR state`
224			`always @ (posedge tck or posedge trst)`
225			`begin`
226			`if(trst)`
227			`CaptureDR<=#Tp 0;`
228			`else`
229			`if(~TMS & SelectDRScan)`
230			`CaptureDR<=#Tp 1;`
231			`else`
232			`CaptureDR<=#Tp 0;`
233			`end`
234
235			`// ShiftDR state`
236			`always @ (posedge tck or posedge trst)`
237			`begin`
238			`if(trst)`
239			`ShiftDR<=#Tp 0;`
240			`else`
241			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
242			`ShiftDR<=#Tp 1;`
243			`else`
244			`ShiftDR<=#Tp 0;`
245			`end`
246
247			`// Exit1DR state`
248			`always @ (posedge tck or posedge trst)`
249			`begin`
250			`if(trst)`
251			`Exit1DR<=#Tp 0;`
252			`else`
253			`if(TMS & (CaptureDR \| ShiftDR))`
254			`Exit1DR<=#Tp 1;`
255			`else`
256			`Exit1DR<=#Tp 0;`
257			`end`
258
259			`// PauseDR state`
260			`always @ (posedge tck or posedge trst)`
261			`begin`
262			`if(trst)`
263			`PauseDR<=#Tp 0;`
264			`else`
265			`if(~TMS & (Exit1DR \| PauseDR))`
266			`PauseDR<=#Tp 1;`
267			`else`
268			`PauseDR<=#Tp 0;`
269			`end`
270
271			`// Exit2DR state`
272			`always @ (posedge tck or posedge trst)`
273			`begin`
274			`if(trst)`
275			`Exit2DR<=#Tp 0;`
276			`else`
277			`if(TMS & PauseDR)`
278			`Exit2DR<=#Tp 1;`
279			`else`
280			`Exit2DR<=#Tp 0;`
281			`end`
282
283			`// UpdateDR state`
284			`always @ (posedge tck or posedge trst)`
285			`begin`
286			`if(trst)`
287			`UpdateDR<=#Tp 0;`
288			`else`
289			`if(TMS & (Exit1DR \| Exit2DR))`
290			`UpdateDR<=#Tp 1;`
291			`else`
292			`UpdateDR<=#Tp 0;`
293			`end`
294
295			`// Delayed UpdateDR state`
296			`reg UpdateDR_q;`
297			`always @ (posedge tck)`
298			`begin`
299			`UpdateDR_q<=#Tp UpdateDR;`
300			`end`
301
302			`// SelectIRScan state`
303			`always @ (posedge tck or posedge trst)`
304			`begin`
305			`if(trst)`
306			`SelectIRScan<=#Tp 0;`
307			`else`
308			`if(TMS & SelectDRScan)`
309			`SelectIRScan<=#Tp 1;`
310			`else`
311			`SelectIRScan<=#Tp 0;`
312			`end`
313
314			`// CaptureIR state`
315			`always @ (posedge tck or posedge trst)`
316			`begin`
317			`if(trst)`
318			`CaptureIR<=#Tp 0;`
319			`else`
320			`if(~TMS & SelectIRScan)`
321			`CaptureIR<=#Tp 1;`
322			`else`
323			`CaptureIR<=#Tp 0;`
324			`end`
325
326			`// ShiftIR state`
327			`always @ (posedge tck or posedge trst)`
328			`begin`
329			`if(trst)`
330			`ShiftIR<=#Tp 0;`
331			`else`
332			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
333			`ShiftIR<=#Tp 1;`
334			`else`
335			`ShiftIR<=#Tp 0;`
336			`end`
337
338			`// Exit1IR state`
339			`always @ (posedge tck or posedge trst)`
340			`begin`
341			`if(trst)`
342			`Exit1IR<=#Tp 0;`
343			`else`
344			`if(TMS & (CaptureIR \| ShiftIR))`
345			`Exit1IR<=#Tp 1;`
346			`else`
347			`Exit1IR<=#Tp 0;`
348			`end`
349
350			`// PauseIR state`
351			`always @ (posedge tck or posedge trst)`
352			`begin`
353			`if(trst)`
354			`PauseIR<=#Tp 0;`
355			`else`
356			`if(~TMS & (Exit1IR \| PauseIR))`
357			`PauseIR<=#Tp 1;`
358			`else`
359			`PauseIR<=#Tp 0;`
360			`end`
361
362			`// Exit2IR state`
363			`always @ (posedge tck or posedge trst)`
364			`begin`
365			`if(trst)`
366			`Exit2IR<=#Tp 0;`
367			`else`
368			`if(TMS & PauseIR)`
369			`Exit2IR<=#Tp 1;`
370			`else`
371			`Exit2IR<=#Tp 0;`
372			`end`
373
374			`// UpdateIR state`
375			`always @ (posedge tck or posedge trst)`
376			`begin`
377			`if(trst)`
378			`UpdateIR<=#Tp 0;`
379			`else`
380			`if(TMS & (Exit1IR \| Exit2IR))`
381			`UpdateIR<=#Tp 1;`
382			`else`
383			`UpdateIR<=#Tp 0;`
384			`end`
385
386			`/**********************************************************************************`
387			`* *`
388			`* End: TAP State Machine *`
389			`* *`
390			`**********************************************************************************/`
391
392
393
394			`/**********************************************************************************`
395			`* *`
396			`* JTAG_IR: JTAG Instruction Register *`
397			`* *`
398			`**********************************************************************************/`
399			`wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.`
400
401			reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
402			reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
403
404			`reg TDOInstruction;`
405
406			`always @ (posedge tck or posedge trst)`
407			`begin`
408			`if(trst)`
409			JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
410			`else`
411			`if(CaptureIR)`
412			`begin`
413			`JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection`
414			`JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip`
415			`end`
416			`else`
417			`if(ShiftIR)`
418			JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
419			`end`
420
421
422			`//TDO is changing on the falling edge of tck`
423			`always @ (negedge tck)`
424			`begin`
425			`if(ShiftIR)`
426			`TDOInstruction <= #Tp JTAG_IR[0];`
427			`end`
428
429			`/**********************************************************************************`
430			`* *`
431			`* End: JTAG_IR *`
432			`* *`
433			`**********************************************************************************/`
434
435
436			`/**********************************************************************************`
437			`* *`
438			`* JTAG_DR: JTAG Data Register *`
439			`* *`
440			`**********************************************************************************/`
441			reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
442
443
444			`always @ (posedge tck or posedge trst)`
445			`begin`
446			`if(trst)`
447			JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
448			`else`
449			`if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE`
450			`begin`
451			`if(ShiftDR)`
452			`JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};`
453			`else`
454			JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
455			`end`
456			`else`
457			`if(CHAIN_SELECTSelected & ShiftDR)`
458			`JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};`
459			`else`
460			`if(DEBUGSelected & ShiftDR)`
461			`begin`
462			`if(RiscDebugScanChain \| WishboneScanChain)`
463			`JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};`
464			`else`
465			`if(RegisterScanChain)`
466			`JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};`
467			`end`
468			`end`
469
470
471
472			`/**********************************************************************************`
473			`* *`
474			`* End: JTAG_DR *`
475			`* *`
476			`**********************************************************************************/`
477
478
479
480
481
482			`/**********************************************************************************`
483			`* *`
484			`* Bypass logic *`
485			`* *`
486			`**********************************************************************************/`
487			`reg TDOBypassed;`
488
489			`always @ (posedge tck)`
490			`begin`
491			`if(ShiftDR)`
492			`BypassRegister<=#Tp tdi;`
493			`end`
494
495			`always @ (negedge tck)`
496			`begin`
497			`TDOBypassed<=#Tp BypassRegister;`
498			`end`
499			`/**********************************************************************************`
500			`* *`

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