URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
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36 |
mohor |
#write format wave -window .wave C:/cvsroot/ethernet/sim/rtl_sim/run/wave.do
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vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb_defines.v}
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vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/timescale.v}
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2 |
mohor |
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_crc8_d1.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_defines.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_register.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_registers.v}
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11 |
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v}
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14 |
36 |
mohor |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/tap_top.v}
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vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/jtag_chain.v}
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16 |
2 |
mohor |
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17 |
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vsim work.dbg_tb
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18 |
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add wave -r -hexadecimal /*
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36 |
mohor |
#do C:/cvsroot/ethernet/sim/rtl_sim/run/wave.do
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2 |
mohor |
run -all
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24 |
36 |
mohor |
.wave.tree zoomfull
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