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[/] [dbg_interface/] [tags/] [sdram_test_working/] [bench/] [verilog/] [dbg_tb_defines.v] - Blame information for rev 49

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbgTB_defines.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:23:40  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:05  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:12  mohor
// Initial release
//
//
 
// Following defines are used in the testbench only
 
  // MODER register
  `define ENABLE          32'h00010000
  `define CONTIN          32'h00020000
 
  // TSEL register
  `define WPTRIG_0        32'h00000001
  `define WPTRIG_1        32'h00000002
  `define WPTRIG_2        32'h00000004
  `define WPTRIG_3        32'h00000008
  `define WPTRIG_4        32'h00000010
  `define WPTRIG_5        32'h00000020
  `define WPTRIG_6        32'h00000040
  `define WPTRIG_7        32'h00000080
  `define WPTRIG_8        32'h00000100
  `define WPTRIG_9        32'h00000200
  `define WPTRIG_10       32'h00000400
  `define WPTRIGVALID     32'h00000800
 
  `define BPTRIG          32'h00001000
  `define BPTRIGVALID     32'h00002000
 
  `define LSSTRIG_0       32'h00010000
  `define LSSTRIG_1       32'h00020000
  `define LSSTRIG_2       32'h00040000
  `define LSSTRIG_3       32'h00080000
  `define LSSTRIGVALID    32'h00100000
 
  `define ISTRIGVALID     32'h00800000
 
  `define TRIGOP_AND      32'hc0000000
  `define TRIGOP_OR       32'h80000000
 
  // QSEL register
  `define WPQUALIF_0      32'h00000001
  `define WPQUALIF_1      32'h00000002
  `define WPQUALIF_2      32'h00000004
  `define WPQUALIF_3      32'h00000008
  `define WPQUALIF_4      32'h00000010
  `define WPQUALIF_5      32'h00000020
  `define WPQUALIF_6      32'h00000040
  `define WPQUALIF_7      32'h00000080
  `define WPQUALIF_8      32'h00000100
  `define WPQUALIF_9      32'h00000200
  `define WPQUALIF_10     32'h00000400
  `define WPQUALIFVALID   32'h00000800
 
  `define BPQUALIF        32'h00001000
  `define BPQUALIFVALID   32'h00002000
 
  `define LSSQUALIF_0     32'h00010000
  `define LSSQUALIF_1     32'h00020000
  `define LSSQUALIF_2     32'h00040000
  `define LSSQUALIF_3     32'h00080000
  `define LSSQUALIFVALID  32'h00100000
 
  `define ISQUALIFVALID   32'h00800000
 
  `define QUALIFOP_AND    32'hc0000000
  `define QUALIFOP_OR     32'h80000000
 
 
  // SSEL register
  `define WPSTOP_0      32'h00000001
  `define WPSTOP_1      32'h00000002
  `define WPSTOP_2      32'h00000004
  `define WPSTOP_3      32'h00000008
  `define WPSTOP_4      32'h00000010
  `define WPSTOP_5      32'h00000020
  `define WPSTOP_6      32'h00000040
  `define WPSTOP_7      32'h00000080
  `define WPSTOP_8      32'h00000100
  `define WPSTOP_9      32'h00000200
  `define WPSTOP_10     32'h00000400
  `define WPSTOPVALID   32'h00000800
 
  `define BPSTOP        32'h00001000
  `define BPSTOPVALID   32'h00002000
 
  `define LSSSTOP_0     32'h00010000
  `define LSSSTOP_1     32'h00020000
  `define LSSSTOP_2     32'h00040000
  `define LSSSTOP_3     32'h00080000
  `define LSSSTOPVALID  32'h00100000
 
  `define ISSTOPVALID   32'h00800000
 
  `define STOPOP_AND    32'hc0000000
  `define STOPOP_OR     32'h80000000
 
  `define IS_NO_FETCH     32'h00000000
  `define IS_FETCH        32'h00200000
  `define IS_BRANCH       32'h00400000
  `define IS_FETCH_DELAY  32'h00600000
 
  `define LSS_NO_LOADSTORE      32'h00000000
  `define LSS_LOADBYTE_ZEROEXT  32'h00020000
  `define LSS_LOADBYTE_SIGNEXT  32'h00030000
  `define LSS_LOADHALF_ZEROEXT  32'h00040000
  `define LSS_LOADHALF_SIGNEXT  32'h00050000
  `define LSS_LOADWORD_ZEROEXT  32'h00060000
  `define LSS_LOADWORD_SIGNEXT  32'h00070000
  `define LSS_STORE_BYTE        32'h000A0000
  `define LSS_STORE_HALF        32'h000C0000
 
// End: Following defines are used in the testbench only
 
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbgTB_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
49			`// Initial official release.`
50			`//`
51	2	mohor	`// Revision 1.3 2001/06/01 22:23:40 mohor`
52			`// This is a backup. It is not a fully working version. Not for use, yet.`
53			`//`
54			`// Revision 1.2 2001/05/18 13:10:05 mohor`
55			`// Headers changed. All additional information is now avaliable in the README.txt file.`
56			`//`
57			`// Revision 1.1.1.1 2001/05/18 06:35:12 mohor`
58			`// Initial release`
59			`//`
60			`//`
61
62			`// Following defines are used in the testbench only`
63
64			`// MODER register`
65	5	mohor	`define ENABLE 32'h00010000
66			`define CONTIN 32'h00020000
67	2	mohor
68			`// TSEL register`
69			`define WPTRIG_0 32'h00000001
70			`define WPTRIG_1 32'h00000002
71			`define WPTRIG_2 32'h00000004
72			`define WPTRIG_3 32'h00000008
73			`define WPTRIG_4 32'h00000010
74			`define WPTRIG_5 32'h00000020
75			`define WPTRIG_6 32'h00000040
76			`define WPTRIG_7 32'h00000080
77			`define WPTRIG_8 32'h00000100
78			`define WPTRIG_9 32'h00000200
79			`define WPTRIG_10 32'h00000400
80			`define WPTRIGVALID 32'h00000800
81
82			`define BPTRIG 32'h00001000
83			`define BPTRIGVALID 32'h00002000
84
85			`define LSSTRIG_0 32'h00010000
86			`define LSSTRIG_1 32'h00020000
87			`define LSSTRIG_2 32'h00040000
88			`define LSSTRIG_3 32'h00080000
89			`define LSSTRIGVALID 32'h00100000
90
91			`define ISTRIGVALID 32'h00800000
92
93			`define TRIGOP_AND 32'hc0000000
94			`define TRIGOP_OR 32'h80000000
95
96			`// QSEL register`
97			`define WPQUALIF_0 32'h00000001
98			`define WPQUALIF_1 32'h00000002
99			`define WPQUALIF_2 32'h00000004
100			`define WPQUALIF_3 32'h00000008
101			`define WPQUALIF_4 32'h00000010
102			`define WPQUALIF_5 32'h00000020
103			`define WPQUALIF_6 32'h00000040
104			`define WPQUALIF_7 32'h00000080
105			`define WPQUALIF_8 32'h00000100
106			`define WPQUALIF_9 32'h00000200
107			`define WPQUALIF_10 32'h00000400
108			`define WPQUALIFVALID 32'h00000800
109
110			`define BPQUALIF 32'h00001000
111			`define BPQUALIFVALID 32'h00002000
112
113			`define LSSQUALIF_0 32'h00010000
114			`define LSSQUALIF_1 32'h00020000
115			`define LSSQUALIF_2 32'h00040000
116			`define LSSQUALIF_3 32'h00080000
117			`define LSSQUALIFVALID 32'h00100000
118
119			`define ISQUALIFVALID 32'h00800000
120
121			`define QUALIFOP_AND 32'hc0000000
122			`define QUALIFOP_OR 32'h80000000
123
124
125			`// SSEL register`
126			`define WPSTOP_0 32'h00000001
127			`define WPSTOP_1 32'h00000002
128			`define WPSTOP_2 32'h00000004
129			`define WPSTOP_3 32'h00000008
130			`define WPSTOP_4 32'h00000010
131			`define WPSTOP_5 32'h00000020
132			`define WPSTOP_6 32'h00000040
133			`define WPSTOP_7 32'h00000080
134			`define WPSTOP_8 32'h00000100
135			`define WPSTOP_9 32'h00000200
136			`define WPSTOP_10 32'h00000400
137			`define WPSTOPVALID 32'h00000800
138
139			`define BPSTOP 32'h00001000
140			`define BPSTOPVALID 32'h00002000
141
142			`define LSSSTOP_0 32'h00010000
143			`define LSSSTOP_1 32'h00020000
144			`define LSSSTOP_2 32'h00040000
145			`define LSSSTOP_3 32'h00080000
146			`define LSSSTOPVALID 32'h00100000
147
148			`define ISSTOPVALID 32'h00800000
149
150			`define STOPOP_AND 32'hc0000000
151			`define STOPOP_OR 32'h80000000
152
153			`define IS_NO_FETCH 32'h00000000
154			`define IS_FETCH 32'h00200000
155			`define IS_BRANCH 32'h00400000
156			`define IS_FETCH_DELAY 32'h00600000
157
158			`define LSS_NO_LOADSTORE 32'h00000000
159			`define LSS_LOADBYTE_ZEROEXT 32'h00020000
160			`define LSS_LOADBYTE_SIGNEXT 32'h00030000
161			`define LSS_LOADHALF_ZEROEXT 32'h00040000
162			`define LSS_LOADHALF_SIGNEXT 32'h00050000
163			`define LSS_LOADWORD_ZEROEXT 32'h00060000
164			`define LSS_LOADWORD_SIGNEXT 32'h00070000
165			`define LSS_STORE_BYTE 32'h000A0000
166			`define LSS_STORE_HALF 32'h000C0000
167
168			`// End: Following defines are used in the testbench only`
169
170

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [bench/] [verilog/] [dbg_tb_defines.v] - Blame information for rev 49