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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:08  mohor
// Initial release
//
//
 
 
 
// Enable TRACE
`define TRACE_ENABLED  // Uncomment this define to activate the trace
 
 
// Define IDCODE Value
`define IDCODE_VALUE  32'hdeadbeef
 
// Define master clock (RISC clock)
//`define       RISC_CLOCK  50   // Half period = 50 ns => MCLK = 10 Mhz
`define RISC_CLOCK  2.5   // Half period = 5 ns => MCLK = 200 Mhz
 
// Length of the Instruction register
`define IR_LENGTH       4
 
// Length of the Data register (must be equal to the longest scan chain)
`define DR_LENGTH       73
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 4
 
// Length of the CRC
`define CRC_LENGTH      8
 
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH        5
`define TRACEBUFFERLENGTH        32 // 2^5
 
`define TRACESAMPLEWIDTH         36
 
// OpSelect width
`define OPSELECTWIDTH            3
`define OPSELECTIONCOUNTER       8    //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_PC            0
`define DEBUG_READ_LSEA          1
`define DEBUG_READ_LDATA         2
`define DEBUG_READ_SDATA         3
`define DEBUG_READ_SPR           4
`define DEBUG_WRITE_SPR          5
`define DEBUG_READ_INSTR         6
//`define Reserved                 7
 
// Supported Instructions
`define EXTEST          5'b00000
`define SAMPLE_PRELOAD  5'b00001
`define IDCODE          5'b00010
`define CHAIN_SELECT    5'b00011
`define INTEST          5'b00100
`define CLAMP           5'b00101
`define CLAMPZ          5'b00110
`define HIGHZ           5'b00111
`define DEBUG           5'b01000
`define BYPASS          5'b01111
 
// Chains
`define GLOBAL_BS_CHAIN     4'b0000
`define RISC_DEBUG_CHAIN    4'b0001
`define RISC_TEST_CHAIN     4'b0010
`define TRACE_TEST_CHAIN    4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
`define WISHBONE_SCAN_CHAIN 4'b0101
 
// Registers addresses
`define MODER_ADR           5'h00
`define TSEL_ADR            5'h01
`define QSEL_ADR            5'h02
`define SSEL_ADR            5'h03
`define RISCOP_ADR          5'h04
`define RECSEL_ADR          5'h10
 
 
// Registers default values (after reset)
`define MODER_DEF           2'h0
`define TSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define RISCOP_DEF          2'h0
`define RECSEL_DEF          7'h0

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	12	mohor	`// Revision 1.4 2001/09/24 14:06:42 mohor`
49			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
50			`//`
51	11	mohor	`// Revision 1.3 2001/09/20 10:11:25 mohor`
52			`// Working version. Few bugs fixed, comments added.`
53			`//`
54	9	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
55			`// Trace fixed. Some registers changed, trace simplified.`
56			`//`
57	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
58			`// Initial official release.`
59			`//`
60	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
61			`// This is a backup. It is not a fully working version. Not for use, yet.`
62			`//`
63			`// Revision 1.2 2001/05/18 13:10:00 mohor`
64			`// Headers changed. All additional information is now avaliable in the README.txt file.`
65			`//`
66			`// Revision 1.1.1.1 2001/05/18 06:35:08 mohor`
67			`// Initial release`
68			`//`
69			`//`
70
71
72
73			`// Enable TRACE`
74	5	mohor	`define TRACE_ENABLED // Uncomment this define to activate the trace
75	2	mohor
76
77			`// Define IDCODE Value`
78			`define IDCODE_VALUE 32'hdeadbeef
79
80			`// Define master clock (RISC clock)`
81	5	mohor	//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
82			`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
83	2	mohor
84			`// Length of the Instruction register`
85			`define IR_LENGTH 4
86
87			`// Length of the Data register (must be equal to the longest scan chain)`
88			`define DR_LENGTH 73
89
90			`// Length of the CHAIN ID register`
91			`define CHAIN_ID_LENGTH 4
92
93			`// Length of the CRC`
94			`define CRC_LENGTH 8
95
96	9	mohor	`// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable`
97			`define TRACECOUNTERWIDTH 5
98			`define TRACEBUFFERLENGTH 32 // 2^5
99
100	2	mohor	`define TRACESAMPLEWIDTH 36
101
102			`// OpSelect width`
103			`define OPSELECTWIDTH 3
104			`define OPSELECTIONCOUNTER 8 //2^3
105
106	11	mohor	`// OpSelect (dbg_op_i) signal meaning`
107			`define DEBUG_READ_PC 0
108			`define DEBUG_READ_LSEA 1
109			`define DEBUG_READ_LDATA 2
110			`define DEBUG_READ_SDATA 3
111			`define DEBUG_READ_SPR 4
112			`define DEBUG_WRITE_SPR 5
113			`define DEBUG_READ_INSTR 6
114			//`define Reserved 7
115
116	2	mohor	`// Supported Instructions`
117	9	mohor	`define EXTEST 5'b00000
118			`define SAMPLE_PRELOAD 5'b00001
119			`define IDCODE 5'b00010
120			`define CHAIN_SELECT 5'b00011
121			`define INTEST 5'b00100
122			`define CLAMP 5'b00101
123			`define CLAMPZ 5'b00110
124			`define HIGHZ 5'b00111
125			`define DEBUG 5'b01000
126			`define BYPASS 5'b01111
127	2	mohor
128			`// Chains`
129			`define GLOBAL_BS_CHAIN 4'b0000
130			`define RISC_DEBUG_CHAIN 4'b0001
131			`define RISC_TEST_CHAIN 4'b0010
132			`define TRACE_TEST_CHAIN 4'b0011
133			`define REGISTER_SCAN_CHAIN 4'b0100
134	12	mohor	`define WISHBONE_SCAN_CHAIN 4'b0101
135	2	mohor
136			`// Registers addresses`
137			`define MODER_ADR 5'h00
138			`define TSEL_ADR 5'h01
139			`define QSEL_ADR 5'h02
140			`define SSEL_ADR 5'h03
141	5	mohor	`define RISCOP_ADR 5'h04
142			`define RECSEL_ADR 5'h10
143	2	mohor
144
145			`// Registers default values (after reset)`
146	5	mohor	`define MODER_DEF 2'h0
147	2	mohor	`define TSEL_DEF 32'h00000000
148			`define QSEL_DEF 32'h00000000
149			`define SSEL_DEF 32'h00000000
150	5	mohor	`define RISCOP_DEF 2'h0
151	9	mohor	`define RECSEL_DEF 7'h0

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 12