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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 23

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:08  mohor
// Initial release
//
//
 
 
 
// Enable TRACE
//`define TRACE_ENABLED  // Uncomment this define to activate the trace
 
 
// Define IDCODE Value
`define IDCODE_VALUE  32'hdeadbeef
 
// Define master clock (RISC clock)
//`define       RISC_CLOCK  50   // Half period = 50 ns => MCLK = 10 Mhz
`define RISC_CLOCK  2.5   // Half period = 5 ns => MCLK = 200 Mhz
 
// Length of the Instruction register
`define IR_LENGTH       4
 
// Length of the Data register (must be equal to the longest scan chain)
`define DR_LENGTH       73
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 4
 
// Length of the CRC
`define CRC_LENGTH      8
 
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH        5
`define TRACEBUFFERLENGTH        32 // 2^5
 
`define TRACESAMPLEWIDTH         36
 
// OpSelect width
`define OPSELECTWIDTH            3
`define OPSELECTIONCOUNTER       8    //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_PC            0
`define DEBUG_READ_LSEA          1
`define DEBUG_READ_LDATA         2
`define DEBUG_READ_SDATA         3
`define DEBUG_READ_SPR           4
`define DEBUG_WRITE_SPR          5
`define DEBUG_READ_INSTR         6
//`define Reserved                 7
 
// Supported Instructions
`define EXTEST          5'b00000
`define SAMPLE_PRELOAD  5'b00001
`define IDCODE          5'b00010
`define CHAIN_SELECT    5'b00011
`define INTEST          5'b00100
`define CLAMP           5'b00101
`define CLAMPZ          5'b00110
`define HIGHZ           5'b00111
`define DEBUG           5'b01000
`define BYPASS          5'b01111
 
// Chains
`define GLOBAL_BS_CHAIN     4'b0000
`define RISC_DEBUG_CHAIN    4'b0001
`define RISC_TEST_CHAIN     4'b0010
`define TRACE_TEST_CHAIN    4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
`define WISHBONE_SCAN_CHAIN 4'b0101
 
// Registers addresses
`define MODER_ADR           5'h00
`define TSEL_ADR            5'h01
`define QSEL_ADR            5'h02
`define SSEL_ADR            5'h03
`define RISCOP_ADR          5'h04
`define RECSEL_ADR          5'h10
 
 
// Registers default values (after reset)
`define MODER_DEF           2'h0
`define TSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define RISCOP_DEF          2'h0
`define RECSEL_DEF          7'h0

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	23	mohor	`// Revision 1.5 2001/10/15 09:55:47 mohor`
49			`// Wishbone interface added, few fixes for better performance,`
50			`// hooks for boundary scan testing added.`
51			`//`
52	12	mohor	`// Revision 1.4 2001/09/24 14:06:42 mohor`
53			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
54			`//`
55	11	mohor	`// Revision 1.3 2001/09/20 10:11:25 mohor`
56			`// Working version. Few bugs fixed, comments added.`
57			`//`
58	9	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
59			`// Trace fixed. Some registers changed, trace simplified.`
60			`//`
61	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
62			`// Initial official release.`
63			`//`
64	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
65			`// This is a backup. It is not a fully working version. Not for use, yet.`
66			`//`
67			`// Revision 1.2 2001/05/18 13:10:00 mohor`
68			`// Headers changed. All additional information is now avaliable in the README.txt file.`
69			`//`
70			`// Revision 1.1.1.1 2001/05/18 06:35:08 mohor`
71			`// Initial release`
72			`//`
73			`//`
74
75
76
77			`// Enable TRACE`
78	23	mohor	//`define TRACE_ENABLED // Uncomment this define to activate the trace
79	2	mohor
80
81			`// Define IDCODE Value`
82			`define IDCODE_VALUE 32'hdeadbeef
83
84			`// Define master clock (RISC clock)`
85	5	mohor	//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
86			`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
87	2	mohor
88			`// Length of the Instruction register`
89			`define IR_LENGTH 4
90
91			`// Length of the Data register (must be equal to the longest scan chain)`
92			`define DR_LENGTH 73
93
94			`// Length of the CHAIN ID register`
95			`define CHAIN_ID_LENGTH 4
96
97			`// Length of the CRC`
98			`define CRC_LENGTH 8
99
100	9	mohor	`// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable`
101			`define TRACECOUNTERWIDTH 5
102			`define TRACEBUFFERLENGTH 32 // 2^5
103
104	2	mohor	`define TRACESAMPLEWIDTH 36
105
106			`// OpSelect width`
107			`define OPSELECTWIDTH 3
108			`define OPSELECTIONCOUNTER 8 //2^3
109
110	11	mohor	`// OpSelect (dbg_op_i) signal meaning`
111			`define DEBUG_READ_PC 0
112			`define DEBUG_READ_LSEA 1
113			`define DEBUG_READ_LDATA 2
114			`define DEBUG_READ_SDATA 3
115			`define DEBUG_READ_SPR 4
116			`define DEBUG_WRITE_SPR 5
117			`define DEBUG_READ_INSTR 6
118			//`define Reserved 7
119
120	2	mohor	`// Supported Instructions`
121	9	mohor	`define EXTEST 5'b00000
122			`define SAMPLE_PRELOAD 5'b00001
123			`define IDCODE 5'b00010
124			`define CHAIN_SELECT 5'b00011
125			`define INTEST 5'b00100
126			`define CLAMP 5'b00101
127			`define CLAMPZ 5'b00110
128			`define HIGHZ 5'b00111
129			`define DEBUG 5'b01000
130			`define BYPASS 5'b01111
131	2	mohor
132			`// Chains`
133			`define GLOBAL_BS_CHAIN 4'b0000
134			`define RISC_DEBUG_CHAIN 4'b0001
135			`define RISC_TEST_CHAIN 4'b0010
136			`define TRACE_TEST_CHAIN 4'b0011
137			`define REGISTER_SCAN_CHAIN 4'b0100
138	12	mohor	`define WISHBONE_SCAN_CHAIN 4'b0101
139	2	mohor
140			`// Registers addresses`
141			`define MODER_ADR 5'h00
142			`define TSEL_ADR 5'h01
143			`define QSEL_ADR 5'h02
144			`define SSEL_ADR 5'h03
145	5	mohor	`define RISCOP_ADR 5'h04
146			`define RECSEL_ADR 5'h10
147	2	mohor
148
149			`// Registers default values (after reset)`
150	5	mohor	`define MODER_DEF 2'h0
151	2	mohor	`define TSEL_DEF 32'h00000000
152			`define QSEL_DEF 32'h00000000
153			`define SSEL_DEF 32'h00000000
154	5	mohor	`define RISCOP_DEF 2'h0
155	9	mohor	`define RECSEL_DEF 7'h0

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 23