Subversion Repositories dbg_interface

//////////////////////////////////////////////////////////////////////

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////  dbg_register.v                                              ////

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////                                                              ////

////  This file is part of the SoC/OpenRISC Development Interface ////

////  http://www.opencores.org/cores/DebugInterface/              ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////       Igor Mohor                                             ////

////       igorm@opencores.org                                    ////

////                                                              ////

////                                                              ////

////  All additional information is avaliable in the README.txt   ////

////  file.                                                       ////

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//// Copyright (C) 2000,2001 Authors                              ////

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//// This source file is free software; you can redistribute it   ////

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`include "dbg_timescale.v"

module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default);

parameter WIDTH = 8; // default parameter of the register width

input [WIDTH-1:0] DataIn;

input Write;

input Clk;

input Reset;

input [WIDTH-1:0] Default;

output [WIDTH-1:0] DataOut;

reg    [WIDTH-1:0] DataOut;

//always @ (posedge Clk or posedge Reset)

always @ (posedge Clk)

begin

  if(Reset)

    DataOut[WIDTH-1:0]<=#1 Default;

  else

    begin

      if(Write)                         // write

        DataOut[WIDTH-1:0]<=#1 DataIn[WIDTH-1:0];

    end

end

endmodule   // Register