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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_sync_clk1_clk2.v] - Blame information for rev 17

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_sync_clk1_clk2.v                                        ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
//
//
//
// 
 
`include "timescale.v"
 
// FF in clock domain 1 is being set by a signal from the clock domain 2
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
 
parameter   Tp = 1;
 
input   clk1;
input   clk2;
input   reset1;
input   reset2;
input   set2;
 
output  sync_out;
 
reg     set2_q;
reg     set2_q2;
reg     set1_q;
reg     set1_q2;
reg     clear2_q;
reg     clear2_q2;
reg     sync_out;
 
wire    z;
 
assign z = set2 | set2_q & ~clear2_q2;
 
 
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    set2_q <=#Tp 1'b0;
  else
    set2_q <=#Tp z;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    set2_q2 <=#Tp 1'b0;
  else
    set2_q2 <=#Tp set2_q;
end
 
 
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    set1_q <=#Tp 1'b0;
  else
    set1_q <=#Tp set2_q2;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    set1_q2 <=#Tp 1'b0;
  else
    set1_q2 <=#Tp set1_q;
end
 
 
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    clear2_q <=#Tp 1'b0;
  else
    clear2_q <=#Tp set1_q2;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    clear2_q2 <=#Tp 1'b0;
  else
    clear2_q2 <=#Tp clear2_q;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    sync_out <=#Tp 1'b0;
  else
    sync_out <=#Tp set1_q2;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_sync_clk1_clk2.v ////`
4			`//// ////`
5			`//// This file is part of the SoC/OpenRISC Development Interface ////`
6			`//// http://www.opencores.org/cores/DebugInterface/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	17	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
45			`// Initial official release.`
46	2	mohor	`//`
47			`//`
48			`//`
49	17	mohor	`//`
50	2	mohor	`//`
51
52	17	mohor	`include "timescale.v"
53	2	mohor
54			`// FF in clock domain 1 is being set by a signal from the clock domain 2`
55			`module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);`
56
57			`parameter Tp = 1;`
58
59			`input clk1;`
60			`input clk2;`
61			`input reset1;`
62			`input reset2;`
63			`input set2;`
64
65			`output sync_out;`
66
67			`reg set2_q;`
68			`reg set2_q2;`
69			`reg set1_q;`
70			`reg set1_q2;`
71			`reg clear2_q;`
72			`reg clear2_q2;`
73			`reg sync_out;`
74
75			`wire z;`
76
77			`assign z = set2 \| set2_q & ~clear2_q2;`
78
79
80			`// Latching and synchronizing "set" to clk2`
81			`always @ (posedge clk2 or posedge reset2)`
82			`begin`
83			`if(reset2)`
84			`set2_q <=#Tp 1'b0;`
85			`else`
86			`set2_q <=#Tp z;`
87			`end`
88
89
90			`always @ (posedge clk2 or posedge reset2)`
91			`begin`
92			`if(reset2)`
93			`set2_q2 <=#Tp 1'b0;`
94			`else`
95			`set2_q2 <=#Tp set2_q;`
96			`end`
97
98
99			`// Synchronizing "set" to clk1`
100			`always @ (posedge clk1 or posedge reset1)`
101			`begin`
102			`if(reset1)`
103			`set1_q <=#Tp 1'b0;`
104			`else`
105			`set1_q <=#Tp set2_q2;`
106			`end`
107
108
109			`always @ (posedge clk1 or posedge reset1)`
110			`begin`
111			`if(reset1)`
112			`set1_q2 <=#Tp 1'b0;`
113			`else`
114			`set1_q2 <=#Tp set1_q;`
115			`end`
116
117
118			`// Synchronizing "clear" to clk2`
119			`always @ (posedge clk2 or posedge reset2)`
120			`begin`
121			`if(reset2)`
122			`clear2_q <=#Tp 1'b0;`
123			`else`
124			`clear2_q <=#Tp set1_q2;`
125			`end`
126
127
128			`always @ (posedge clk2 or posedge reset2)`
129			`begin`
130			`if(reset2)`
131			`clear2_q2 <=#Tp 1'b0;`
132			`else`
133			`clear2_q2 <=#Tp clear2_q;`
134			`end`
135
136
137			`always @ (posedge clk1 or posedge reset1)`
138			`begin`
139			`if(reset1)`
140			`sync_out <=#Tp 1'b0;`
141			`else`
142			`sync_out <=#Tp set1_q2;`
143			`end`
144
145			`endmodule`

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_sync_clk1_clk2.v] - Blame information for rev 17