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1 2 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  dbg_top.v                                                   ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the SoC/OpenRISC Development Interface ////
7 
////  http://www.opencores.org/cores/DebugInterface/              ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is avaliable in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000,2001 Authors                              ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 17 mohor 
// Revision 1.8  2001/10/17 10:39:03  mohor
49 
// bs_chain_o added.
50 
//
51 15 mohor 
// Revision 1.7  2001/10/16 10:09:56  mohor
52 
// Signal names changed to lowercase.
53 13 mohor 
//
54 15 mohor 
//
55 13 mohor 
// Revision 1.6  2001/10/15 09:55:47  mohor
56 
// Wishbone interface added, few fixes for better performance,
57 
// hooks for boundary scan testing added.
58 
//
59 12 mohor 
// Revision 1.5  2001/09/24 14:06:42  mohor
60 
// Changes connected to the OpenRISC access (SPR read, SPR write).
61 
//
62 11 mohor 
// Revision 1.4  2001/09/20 10:11:25  mohor
63 
// Working version. Few bugs fixed, comments added.
64 
//
65 9 mohor 
// Revision 1.3  2001/09/19 11:55:13  mohor
66 
// Asynchronous set/reset not used in trace any more.
67 
//
68 8 mohor 
// Revision 1.2  2001/09/18 14:13:47  mohor
69 
// Trace fixed. Some registers changed, trace simplified.
70 
//
71 5 mohor 
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
72 
// Initial official release.
73 
//
74 2 mohor 
// Revision 1.3  2001/06/01 22:22:35  mohor
75 
// This is a backup. It is not a fully working version. Not for use, yet.
76 
//
77 
// Revision 1.2  2001/05/18 13:10:00  mohor
78 
// Headers changed. All additional information is now avaliable in the README.txt file.
79 
//
80 
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
81 
// Initial release
82 
//
83 
//
84 
 
85 17 mohor 
`include "timescale.v"
86 2 mohor 
`include "dbg_defines.v"
87 
 
88 
// Top module
89 9 mohor 
module dbg_top(
90 
                // JTAG pins
91 
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
92 12 mohor 
 
93 
                // Boundary Scan signals
94 15 mohor 
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
95 9 mohor 
 
96 
                // RISC signals
97 11 mohor 
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
98 
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
99 9 mohor 
 
100 12 mohor 
                // WISHBONE common signals
101 
                wb_rst_i, wb_clk_i,
102 
 
103 
                // WISHBONE master interface
104 
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
105 
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
106 
 
107 
 
108 2 mohor 
              );
109 
 
110 
parameter Tp = 1;
111 
 
112 9 mohor 
// JTAG pins
113 
input         tms_pad_i;                  // JTAG test mode select pad
114 
input         tck_pad_i;                  // JTAG test clock pad
115 
input         trst_pad_i;                 // JTAG test reset pad
116 
input         tdi_pad_i;                  // JTAG test data input pad
117 
output        tdo_pad_o;                  // JTAG test data output pad
118 2 mohor 
 
119 
 
120 12 mohor 
// Boundary Scan signals
121 13 mohor 
output capture_dr_o;
122 
output shift_dr_o;
123 
output update_dr_o;
124 
output extest_selected_o;
125 
input  bs_chain_i;
126 15 mohor 
output bs_chain_o;
127 12 mohor 
 
128 9 mohor 
// RISC signals
129 11 mohor 
input         risc_clk_i;                 // Master clock (RISC clock)
130 9 mohor 
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
131 
input  [10:0] wp_i;                       // Watchpoint inputs
132 
input         bp_i;                       // Breakpoint input
133 
input  [3:0]  lsstatus_i;                 // Load/store status inputs
134 
input  [1:0]  istatus_i;                  // Instruction status inputs
135 
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
136 
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
137 
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
138 
output                      risc_stall_o; // Stalls the RISC
139 11 mohor 
output                      reset_o;      // Resets the RISC
140 2 mohor 
 
141 
 
142 12 mohor 
// WISHBONE common signals
143 9 mohor 
input         wb_rst_i;                   // WISHBONE reset
144 12 mohor 
input         wb_clk_i;                   // WISHBONE clock
145 9 mohor 
 
146 12 mohor 
// WISHBONE master interface
147 
output [31:0] wb_adr_o;
148 
output [31:0] wb_dat_o;
149 
input  [31:0] wb_dat_i;
150 
output        wb_cyc_o;
151 
output        wb_stb_o;
152 
output  [3:0] wb_sel_o;
153 
output        wb_we_o;
154 
input         wb_ack_i;
155 
output        wb_cab_o;
156 
input         wb_err_i;
157 9 mohor 
 
158 12 mohor 
reg    [31:0] wb_adr_o;
159 
reg    [31:0] wb_dat_o;
160 
reg           wb_we_o;
161 
reg           wb_cyc_o;
162 
 
163 9 mohor 
// TAP states
164 2 mohor 
reg TestLogicReset;
165 
reg RunTestIdle;
166 
reg SelectDRScan;
167 
reg CaptureDR;
168 
reg ShiftDR;
169 
reg Exit1DR;
170 
reg PauseDR;
171 
reg Exit2DR;
172 
reg UpdateDR;
173 
 
174 
reg SelectIRScan;
175 
reg CaptureIR;
176 
reg ShiftIR;
177 
reg Exit1IR;
178 
reg PauseIR;
179 
reg Exit2IR;
180 
reg UpdateIR;
181 
 
182 9 mohor 
 
183 
// Defining which instruction is selected
184 2 mohor 
reg EXTESTSelected;
185 
reg SAMPLE_PRELOADSelected;
186 
reg IDCODESelected;
187 
reg CHAIN_SELECTSelected;
188 
reg INTESTSelected;
189 
reg CLAMPSelected;
190 
reg CLAMPZSelected;
191 
reg HIGHZSelected;
192 
reg DEBUGSelected;
193 
reg BYPASSSelected;
194 
 
195 9 mohor 
reg [31:0]  ADDR;
196 
reg [31:0]  DataOut;
197 
 
198 11 mohor 
reg [`OPSELECTWIDTH-1:0] opselect_o;      // Operation selection (selecting what kind of data is set to the risc_data_i)
199 
 
200 2 mohor 
reg [`CHAIN_ID_LENGTH-1:0] Chain;         // Selected chain
201 11 mohor 
reg [31:0]  RISC_DATAINLatch;             // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is
202 2 mohor 
                                          // accessed for reading
203 9 mohor 
reg [31:0]  RegisterReadLatch;            // Data when reading register is latched one TCK clock after the register is read.
204 
reg         RegAccessTck;                 // Indicates access to the registers (read or write)
205 
reg         RISCAccessTck;                // Indicates access to the RISC (read or write)
206 
reg [7:0]   BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
207 
reg         RW;                           // Read/Write bit
208 
reg         CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
209 2 mohor 
 
210 9 mohor 
reg         RegAccess_q;                  // Delayed signals used for accessing the registers
211 
reg         RegAccess_q2;                 // Delayed signals used for accessing the registers
212 
reg         RISCAccess_q;                 // Delayed signals used for accessing the RISC
213 
reg         RISCAccess_q2;                // Delayed signals used for accessing the RISC
214 2 mohor 
 
215 12 mohor 
reg         wb_AccessTck;                 // Indicates access to the WISHBONE
216 
reg [31:0]  WBReadLatch;                  // Data latched during WISHBONE read
217 
reg         WBErrorLatch;                 // Error latched during WISHBONE read
218 2 mohor 
 
219 9 mohor 
wire TCK = tck_pad_i;
220 
wire TMS = tms_pad_i;
221 
wire TDI = tdi_pad_i;
222 12 mohor 
wire RESET = ~trst_pad_i | wb_rst_i;      // trst_pad_i is active low
223 2 mohor 
 
224 9 mohor 
wire [31:0]             RegDataIn;        // Data from registers (read data)
225 
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
226 2 mohor 
 
227 9 mohor 
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
228 
wire RiscReset_reg;                       // RISC is reset by setting the register bit
229 
wire RiscStall_trace;                     // RISC is stalled by trace module
230 
 
231 
 
232 
wire RegisterScanChain;                   // Register Scan chain selected
233 
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
234 12 mohor 
wire WishboneScanChain;                   // WISHBONE Scan chain selected
235 11 mohor 
 
236 
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
237 
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
238 
wire RiscStall_access;                    // Stalling RISC because of the read or write access
239 
 
240 9 mohor 
 
241 13 mohor 
assign capture_dr_o       = CaptureDR;
242 
assign shift_dr_o         = ShiftDR;
243 
assign update_dr_o        = UpdateDR;
244 
assign extest_selected_o  = EXTESTSelected;
245 
wire   BS_CHAIN_I         = bs_chain_i;
246 15 mohor 
assign bs_chain_o         = tdi_pad_i;
247 
 
248 
 
249 9 mohor 
// This signals are used only when TRACE is used in the design
250 2 mohor 
`ifdef TRACE_ENABLED
251 9 mohor 
  wire [39:0] TraceChain;                 // Chain that comes from trace module
252 
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with TCK)
253 
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
254 
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
255 
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
256 2 mohor 
 
257 
  // Outputs from registers
258 9 mohor 
  wire ContinMode;                        // Trace working in continous mode
259 
  wire TraceEnable;                       // Trace enabled
260 2 mohor 
 
261 9 mohor 
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
262 
  wire        BpTrigger;                  // Breakpoint starts trigger
263 
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
264 
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
265 
  wire [1:0]  TriggerOper;                // Trigger operation
266 2 mohor 
 
267 9 mohor 
  wire        WpTriggerValid;             // Watchpoint trigger is valid
268 
  wire        BpTriggerValid;             // Breakpoint trigger is valid
269 
  wire        LSSTriggerValid;            // Load/store status trigger is valid
270 
  wire        ITriggerValid;              // Instruction status trigger is valid
271 2 mohor 
 
272 9 mohor 
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
273 
  wire        BpQualif;                   // Breakpoint starts qualifier
274 
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
275 
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
276 
  wire [1:0]  QualifOper;                 // Qualifier operation
277 2 mohor 
 
278 9 mohor 
  wire        WpQualifValid;              // Watchpoint qualifier is valid
279 
  wire        BpQualifValid;              // Breakpoint qualifier is valid
280 
  wire        LSSQualifValid;             // Load/store status qualifier is valid
281 
  wire        IQualifValid;               // Instruction status qualifier is valid
282 2 mohor 
 
283 9 mohor 
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
284 
  wire        BpStop;                     // Breakpoint stops recording of the trace
285 
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
286 
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
287 
  wire [1:0]  StopOper;                   // Stop operation
288 2 mohor 
 
289 9 mohor 
  wire WpStopValid;                       // Watchpoint stop is valid
290 
  wire BpStopValid;                       // Breakpoint stop is valid
291 
  wire LSSStopValid;                      // Load/store status stop is valid
292 
  wire IStopValid;                        // Instruction status stop is valid
293 2 mohor 
 
294 9 mohor 
  wire RecordPC;                          // Recording program counter
295 
  wire RecordLSEA;                        // Recording load/store effective address
296 
  wire RecordLDATA;                       // Recording load data
297 
  wire RecordSDATA;                       // Recording store data
298 
  wire RecordReadSPR;                     // Recording read SPR
299 
  wire RecordWriteSPR;                    // Recording write SPR
300 
  wire RecordINSTR;                       // Recording instruction
301 2 mohor 
 
302 
  // End: Outputs from registers
303 
 
304 9 mohor 
  wire TraceTestScanChain;                // Trace Test Scan chain selected
305 
  wire [47:0] Trace_Data;                 // Trace data
306 2 mohor 
 
307 11 mohor 
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
308 
                                          // data is set to the risc_data_i)
309 
 
310 2 mohor 
`endif
311 
 
312 
 
313 
/**********************************************************************************
314 
*                                                                                 *
315 
*   TAP State Machine: Fully JTAG compliant                                       *
316 
*                                                                                 *
317 
**********************************************************************************/
318 
 
319 
// TestLogicReset state
320 
always @ (posedge TCK or posedge RESET)
321 
begin
322 
  if(RESET)
323 
    TestLogicReset<=#Tp 1;
324 
  else
325 
    begin
326 
      if(TMS & (TestLogicReset | SelectIRScan))
327 
        TestLogicReset<=#Tp 1;
328 
      else
329 
        TestLogicReset<=#Tp 0;
330 
    end
331 
end
332 
 
333 
// RunTestIdle state
334 
always @ (posedge TCK or posedge RESET)
335 
begin
336 
  if(RESET)
337 
    RunTestIdle<=#Tp 0;
338 
  else
339 
    begin
340 
      if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
341 
        RunTestIdle<=#Tp 1;
342 
      else
343 
        RunTestIdle<=#Tp 0;
344 
    end
345 
end
346 
 
347 
// SelectDRScan state
348 
always @ (posedge TCK or posedge RESET)
349 
begin
350 
  if(RESET)
351 
    SelectDRScan<=#Tp 0;
352 
  else
353 
    begin
354 
      if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
355 
        SelectDRScan<=#Tp 1;
356 
      else
357 
        SelectDRScan<=#Tp 0;
358 
    end
359 
end
360 
 
361 
// CaptureDR state
362 
always @ (posedge TCK or posedge RESET)
363 
begin
364 
  if(RESET)
365 
    CaptureDR<=#Tp 0;
366 
  else
367 
    begin
368 
      if(~TMS & SelectDRScan)
369 
        CaptureDR<=#Tp 1;
370 
      else
371 
        CaptureDR<=#Tp 0;
372 
    end
373 
end
374 
 
375 
// ShiftDR state
376 
always @ (posedge TCK or posedge RESET)
377 
begin
378 
  if(RESET)
379 
    ShiftDR<=#Tp 0;
380 
  else
381 
    begin
382 
      if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
383 
        ShiftDR<=#Tp 1;
384 
      else
385 
        ShiftDR<=#Tp 0;
386 
    end
387 
end
388 
 
389 
// Exit1DR state
390 
always @ (posedge TCK or posedge RESET)
391 
begin
392 
  if(RESET)
393 
    Exit1DR<=#Tp 0;
394 
  else
395 
    begin
396 
      if(TMS & (CaptureDR | ShiftDR))
397 
        Exit1DR<=#Tp 1;
398 
      else
399 
        Exit1DR<=#Tp 0;
400 
    end
401 
end
402 
 
403 
// PauseDR state
404 
always @ (posedge TCK or posedge RESET)
405 
begin
406 
  if(RESET)
407 
    PauseDR<=#Tp 0;
408 
  else
409 
    begin
410 
      if(~TMS & (Exit1DR | PauseDR))
411 
        PauseDR<=#Tp 1;
412 
      else
413 
        PauseDR<=#Tp 0;
414 
    end
415 
end
416 
 
417 
// Exit2DR state
418 
always @ (posedge TCK or posedge RESET)
419 
begin
420 
  if(RESET)
421 
    Exit2DR<=#Tp 0;
422 
  else
423 
    begin
424 
      if(TMS & PauseDR)
425 
        Exit2DR<=#Tp 1;
426 
      else
427 
        Exit2DR<=#Tp 0;
428 
    end
429 
end
430 
 
431 
// UpdateDR state
432 
always @ (posedge TCK or posedge RESET)
433 
begin
434 
  if(RESET)
435 
    UpdateDR<=#Tp 0;
436 
  else
437 
    begin
438 
      if(TMS & (Exit1DR | Exit2DR))
439 
        UpdateDR<=#Tp 1;
440 
      else
441 
        UpdateDR<=#Tp 0;
442 
    end
443 
end
444 
 
445 9 mohor 
// Delayed UpdateDR state
446 2 mohor 
reg UpdateDR_q;
447 
always @ (posedge TCK)
448 
begin
449 
  UpdateDR_q<=#Tp UpdateDR;
450 
end
451 
 
452 
 
453 
// SelectIRScan state
454 
always @ (posedge TCK or posedge RESET)
455 
begin
456 
  if(RESET)
457 
    SelectIRScan<=#Tp 0;
458 
  else
459 
    begin
460 
      if(TMS & SelectDRScan)
461 
        SelectIRScan<=#Tp 1;
462 
      else
463 
        SelectIRScan<=#Tp 0;
464 
    end
465 
end
466 
 
467 
// CaptureIR state
468 
always @ (posedge TCK or posedge RESET)
469 
begin
470 
  if(RESET)
471 
    CaptureIR<=#Tp 0;
472 
  else
473 
    begin
474 
      if(~TMS & SelectIRScan)
475 
        CaptureIR<=#Tp 1;
476 
      else
477 
        CaptureIR<=#Tp 0;
478 
    end
479 
end
480 
 
481 
// ShiftIR state
482 
always @ (posedge TCK or posedge RESET)
483 
begin
484 
  if(RESET)
485 
    ShiftIR<=#Tp 0;
486 
  else
487 
    begin
488 
      if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
489 
        ShiftIR<=#Tp 1;
490 
      else
491 
        ShiftIR<=#Tp 0;
492 
    end
493 
end
494 
 
495 
// Exit1IR state
496 
always @ (posedge TCK or posedge RESET)
497 
begin
498 
  if(RESET)
499 
    Exit1IR<=#Tp 0;
500 
  else
501 
    begin
502 
      if(TMS & (CaptureIR | ShiftIR))
503 
        Exit1IR<=#Tp 1;
504 
      else
505 
        Exit1IR<=#Tp 0;
506 
    end
507 
end
508 
 
509 
// PauseIR state
510 
always @ (posedge TCK or posedge RESET)
511 
begin
512 
  if(RESET)
513 
    PauseIR<=#Tp 0;
514 
  else
515 
    begin
516 
      if(~TMS & (Exit1IR | PauseIR))
517 
        PauseIR<=#Tp 1;
518 
      else
519 
        PauseIR<=#Tp 0;
520 
    end
521 
end
522 
 
523 
// Exit2IR state
524 
always @ (posedge TCK or posedge RESET)
525 
begin
526 
  if(RESET)
527 
    Exit2IR<=#Tp 0;
528 
  else
529 
    begin
530 
      if(TMS & PauseIR)
531 
        Exit2IR<=#Tp 1;
532 
      else
533 
        Exit2IR<=#Tp 0;
534 
    end
535 
end
536 
 
537 
// UpdateIR state
538 
always @ (posedge TCK or posedge RESET)
539 
begin
540 
  if(RESET)
541 
    UpdateIR<=#Tp 0;
542 
  else
543 
    begin
544 
      if(TMS & (Exit1IR | Exit2IR))
545 
        UpdateIR<=#Tp 1;
546 
      else
547 
        UpdateIR<=#Tp 0;
548 
    end
549 
end
550 
 
551 
/**********************************************************************************
552 
*                                                                                 *
553 
*   End: TAP State Machine                                                        *
554 
*                                                                                 *
555 
**********************************************************************************/
556 
 
557 
 
558 
 
559 
/**********************************************************************************
560 
*                                                                                 *
561 
*   JTAG_IR:  JTAG Instruction Register                                           *
562 
*                                                                                 *
563 
**********************************************************************************/
564 9 mohor 
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
565 2 mohor 
 
566 9 mohor 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
567 
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
568 
 
569 2 mohor 
reg TDOInstruction;
570 
 
571 
always @ (posedge TCK or posedge RESET)
572 
begin
573 
  if(RESET)
574 
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
575 
  else
576 
    begin
577 
      if(CaptureIR)
578 
        begin
579 
          JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
580 
          JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
581 
        end
582 
      else
583 
        begin
584 
          if(ShiftIR)
585 
            begin
586 
              JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
587 
            end
588 
        end
589 
    end
590 
end
591 
 
592 
 
593 
//TDO is changing on the falling edge of TCK
594 
always @ (negedge TCK)
595 
begin
596 
  if(ShiftIR)
597 
    TDOInstruction <= #Tp JTAG_IR[0];
598 
end
599 9 mohor 
 
600 2 mohor 
/**********************************************************************************
601 
*                                                                                 *
602 
*   End: JTAG_IR                                                                  *
603 
*                                                                                 *
604 
**********************************************************************************/
605 
 
606 
 
607 
/**********************************************************************************
608 
*                                                                                 *
609 
*   JTAG_DR:  JTAG Data Register                                                  *
610 
*                                                                                 *
611 
**********************************************************************************/
612 
wire [31:0] IDCodeValue = `IDCODE_VALUE;  // IDCODE value is 32-bit long.
613 
 
614 
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
615 
reg TDOData;
616 
 
617 
 
618 
always @ (posedge TCK or posedge RESET)
619 
begin
620 
  if(RESET)
621 
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
622 
  else
623 
  if(ShiftDR)
624 
    JTAG_DR_IN[BitCounter]<=#Tp TDI;
625 
end
626 
 
627 
wire [72:0] RISC_Data;
628 
wire [45:0] Register_Data;
629 12 mohor 
wire [72:0] WISHBONE_Data;
630 
wire wb_Access_wbClk;
631 2 mohor 
 
632 
assign RISC_Data      = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
633 
assign Register_Data  = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
634 12 mohor 
assign WISHBONE_Data  = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
635 2 mohor 
 
636 12 mohor 
 
637 2 mohor 
`ifdef TRACE_ENABLED
638 
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
639 
`endif
640 
 
641 
//TDO is changing on the falling edge of TCK
642 
always @ (negedge TCK or posedge RESET)
643 
begin
644 
  if(RESET)
645 
    begin
646 
      TDOData <= #Tp 0;
647 
      `ifdef TRACE_ENABLED
648 
      ReadBuffer_Tck<=#Tp 0;
649 
      `endif
650 
    end
651 
  else
652 
  if(UpdateDR)
653 
    begin
654 
      TDOData <= #Tp CrcMatch;
655 
      `ifdef TRACE_ENABLED
656 9 mohor 
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
657 
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
658 2 mohor 
      `endif
659 
    end
660 
  else
661 
    begin
662 
      if(ShiftDR)
663 
        begin
664 
          if(IDCODESelected)
665 9 mohor 
            TDOData <= #Tp IDCodeValue[BitCounter];           // IDCODE is shifted out
666 2 mohor 
          else
667 
          if(CHAIN_SELECTSelected)
668 
            TDOData <= #Tp 0;
669 
          else
670 
          if(DEBUGSelected)
671 
            begin
672 
              if(RiscDebugScanChain)
673 9 mohor 
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
674 2 mohor 
              else
675 
              if(RegisterScanChain)
676 9 mohor 
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
677 12 mohor 
              else
678 
              if(WishboneScanChain)
679 
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
680 2 mohor 
              `ifdef TRACE_ENABLED
681 
              else
682 
              if(TraceTestScanChain)
683 9 mohor 
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
684 2 mohor 
              `endif
685 
            end
686 
        end
687 
      else
688 
        begin
689 
          TDOData <= #Tp 0;
690 
          `ifdef TRACE_ENABLED
691 
          ReadBuffer_Tck<=#Tp 0;
692 
          `endif
693 
        end
694 
    end
695 
end
696 
 
697 
/**********************************************************************************
698 
*                                                                                 *
699 
*   End: JTAG_DR                                                                  *
700 
*                                                                                 *
701 
**********************************************************************************/
702 
 
703 
 
704 
 
705 
/**********************************************************************************
706 
*                                                                                 *
707 
*   CHAIN_SELECT logic                                                            *
708 
*                                                                                 *
709 
**********************************************************************************/
710 
always @ (posedge TCK or posedge RESET)
711 
begin
712 
  if(RESET)
713 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
714 2 mohor 
  else
715 
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
716 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
717 2 mohor 
end
718 
 
719 
 
720 
 
721 
/**********************************************************************************
722 
*                                                                                 *
723 
*   Register read/write logic                                                     *
724 
*   RISC registers read/write logic                                               *
725 
*                                                                                 *
726 
**********************************************************************************/
727 
always @ (posedge TCK or posedge RESET)
728 
begin
729 
  if(RESET)
730 
    begin
731 
      ADDR[31:0]        <=#Tp 32'h0;
732 
      DataOut[31:0]     <=#Tp 32'h0;
733 
      RW                <=#Tp 1'b0;
734 
      RegAccessTck      <=#Tp 1'b0;
735 
      RISCAccessTck     <=#Tp 1'b0;
736 12 mohor 
      wb_adr_o          <=#Tp 32'h0;
737 
      wb_we_o           <=#Tp 1'h0;
738 
      wb_dat_o          <=#Tp 32'h0;
739 
      wb_AccessTck      <=#Tp 1'h0;
740 2 mohor 
    end
741 
  else
742 
  if(UpdateDR & DEBUGSelected & CrcMatch)
743 
    begin
744 
      if(RegisterScanChain)
745 
        begin
746 
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
747 
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
748 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
749 
          RegAccessTck      <=#Tp 1'b1;
750 
        end
751 
      else
752 
      if(RiscDebugScanChain)
753 
        begin
754 
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
755 
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
756 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
757 
          RISCAccessTck     <=#Tp 1'b1;
758 
        end
759 12 mohor 
      else
760 
      if(WishboneScanChain)
761 
        begin
762 
          wb_adr_o          <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
763 
          wb_we_o           <=#Tp JTAG_DR_IN[32];     // latch R/W bit
764 
          wb_dat_o          <=#Tp JTAG_DR_IN[64:33];  // latch data for write
765 
          wb_AccessTck      <=#Tp 1'b1;               //
766 
        end
767 2 mohor 
    end
768 
  else
769 
    begin
770 
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one TCK clock period only
771 
      RISCAccessTck     <=#Tp 1'b0;
772 12 mohor 
      wb_AccessTck      <=#Tp 1'b0;
773 2 mohor 
    end
774 
end
775 
 
776 12 mohor 
assign wb_sel_o[3:0] = 4'hf;
777 
assign wb_cab_o = 1'b0;
778 9 mohor 
 
779 2 mohor 
 
780 11 mohor 
// Synchronizing the RegAccess signal to risc_clk_i clock
781 
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(TCK),           .reset1(RESET),  .reset2(RESET),
782 2 mohor 
                         .set2(RegAccessTck), .sync_out(RegAccess)
783 
                        );
784 
 
785 11 mohor 
// Synchronizing the RISCAccess signal to risc_clk_i clock
786 
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(TCK),           .reset1(RESET),  .reset2(RESET),
787 2 mohor 
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
788 
                        );
789 
 
790 
 
791 12 mohor 
// Synchronizing the wb_Access signal to wishbone clock
792 
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),      .clk2(TCK),          .reset1(RESET),  .reset2(RESET),
793 
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
794 
                        );
795 
 
796 
 
797 
 
798 
 
799 
 
800 9 mohor 
// Delayed signals used for accessing registers and RISC
801 11 mohor 
always @ (posedge risc_clk_i or posedge RESET)
802 2 mohor 
begin
803 
  if(RESET)
804 
    begin
805 
      RegAccess_q   <=#Tp 1'b0;
806 
      RegAccess_q2  <=#Tp 1'b0;
807 
      RISCAccess_q  <=#Tp 1'b0;
808 
      RISCAccess_q2 <=#Tp 1'b0;
809 
    end
810 
  else
811 
    begin
812 
      RegAccess_q   <=#Tp RegAccess;
813 
      RegAccess_q2  <=#Tp RegAccess_q;
814 
      RISCAccess_q  <=#Tp RISCAccess;
815 
      RISCAccess_q2 <=#Tp RISCAccess_q;
816 
    end
817 
end
818 
 
819 9 mohor 
 
820 2 mohor 
// Latching data read from registers
821 11 mohor 
always @ (posedge risc_clk_i or posedge RESET)
822 2 mohor 
begin
823 
  if(RESET)
824 
    RegisterReadLatch[31:0]<=#Tp 0;
825 
  else
826 
  if(RegAccess_q & ~RegAccess_q2)
827 
    RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
828 
end
829 
 
830 
 
831 9 mohor 
// Chip select and read/write signals for accessing RISC
832 11 mohor 
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
833 
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
834 
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
835 2 mohor 
 
836 
 
837 12 mohor 
reg wb_Access_wbClk_q;
838 
// Delayed signals used for accessing WISHBONE
839 
always @ (posedge wb_clk_i or posedge RESET)
840 
begin
841 
  if(RESET)
842 
    wb_Access_wbClk_q <=#Tp 1'b0;
843 
  else
844 
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
845 
end
846 
 
847 
always @ (posedge wb_clk_i or posedge RESET)
848 
begin
849 
  if(RESET)
850 
    wb_cyc_o <=#Tp 1'b0;
851 
  else
852 
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
853 
    wb_cyc_o <=#Tp 1'b1;
854 
  else
855 
  if(wb_ack_i | wb_err_i)
856 
    wb_cyc_o <=#Tp 1'b0;
857 
end
858 
 
859 
assign wb_stb_o = wb_cyc_o;
860 
 
861 
 
862 
// Latching data read from registers
863 
always @ (posedge risc_clk_i or posedge RESET)
864 
begin
865 
  if(RESET)
866 
    WBReadLatch[31:0]<=#Tp 32'h0;
867 
  else
868 
  if(wb_ack_i)
869 
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
870 
end
871 
 
872 
// Latching WISHBONE error cycle
873 
always @ (posedge wb_clk_i or posedge RESET)
874 
begin
875 
  if(RESET)
876 
    WBErrorLatch<=#Tp 1'b0;
877 
  else
878 
  if(wb_err_i)
879 
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
880 
  if(wb_ack_i)
881 
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
882 
end
883 
 
884 
 
885 9 mohor 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
886 5 mohor 
`ifdef TRACE_ENABLED
887 11 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
888 5 mohor 
`else
889 12 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
890 5 mohor 
`endif
891 
 
892 11 mohor 
assign  reset_o = RiscReset_reg;
893 5 mohor 
 
894 
 
895 12 mohor 
`ifdef TRACE_ENABLED
896 11 mohor 
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
897 12 mohor 
`else
898 
always @ (RiscStall_write_access or RiscStall_read_access)
899 
`endif
900 11 mohor 
begin
901 
  if(RiscStall_write_access)
902 
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
903 
  else
904 
  if(RiscStall_read_access)
905 
    opselect_o = `DEBUG_READ_SPR;   // Read spr
906 
  else
907 12 mohor 
`ifdef TRACE_ENABLED
908 11 mohor 
    opselect_o = opselect_trace;
909 12 mohor 
`else
910 
    opselect_o = 3'h0;
911 
`endif
912 11 mohor 
end
913 9 mohor 
 
914 11 mohor 
 
915 
 
916 2 mohor 
// Latching data read from RISC
917 11 mohor 
always @ (posedge risc_clk_i or posedge RESET)
918 2 mohor 
begin
919 
  if(RESET)
920 
    RISC_DATAINLatch[31:0]<=#Tp 0;
921 
  else
922 
  if(RISCAccess_q & ~RISCAccess_q2)
923 12 mohor 
    RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
924 2 mohor 
end
925 
 
926 12 mohor 
assign risc_addr_o = ADDR;
927 
assign risc_data_o = DataOut;
928 2 mohor 
 
929 
 
930 
 
931 
/**********************************************************************************
932 
*                                                                                 *
933 
*   Read Trace buffer logic                                                       *
934 
*                                                                                 *
935 
**********************************************************************************/
936 
`ifdef TRACE_ENABLED
937 
 
938 9 mohor 
 
939 11 mohor 
// Synchronizing the trace read buffer signal to risc_clk_i clock
940 12 mohor 
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(TCK),           .reset1(RESET),  .reset2(RESET),
941 9 mohor 
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
942 
                        );
943 
 
944 
 
945 
 
946 11 mohor 
  always @(posedge risc_clk_i or posedge RESET)
947 2 mohor 
  begin
948 9 mohor 
    if(RESET)
949 
      ReadTraceBuffer_q <=#Tp 0;
950 2 mohor 
    else
951 9 mohor 
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
952 2 mohor 
  end
953 9 mohor 
 
954 
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
955 
 
956 2 mohor 
`endif
957 
 
958 
/**********************************************************************************
959 
*                                                                                 *
960 
*   End: Read Trace buffer logic                                                  *
961 
*                                                                                 *
962 
**********************************************************************************/
963 
 
964 
 
965 
/**********************************************************************************
966 
*                                                                                 *
967 
*   Bypass logic                                                                  *
968 
*                                                                                 *
969 
**********************************************************************************/
970 
reg BypassRegister;
971 
reg TDOBypassed;
972 
 
973 
always @ (posedge TCK)
974 
begin
975 
  if(ShiftDR)
976 
    BypassRegister<=#Tp TDI;
977 
end
978 
 
979 
always @ (negedge TCK)
980 
begin
981 
    TDOBypassed<=#Tp BypassRegister;
982 
end
983 
/**********************************************************************************
984 
*                                                                                 *
985 
*   End: Bypass logic                                                             *
986 
*                                                                                 *
987 
**********************************************************************************/
988 
 
989 
 
990 
 
991 
 
992 
 
993 
/**********************************************************************************
994 
*                                                                                 *
995 
*   Activating Instructions                                                       *
996 
*                                                                                 *
997 
**********************************************************************************/
998 
 
999 
// Updating JTAG_IR (Instruction Register)
1000 
always @ (posedge TCK or posedge RESET)
1001 
begin
1002 
  if(RESET)
1003 9 mohor 
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
1004 2 mohor 
  else
1005 9 mohor 
  if(UpdateIR)
1006 
    LatchedJTAG_IR <=#Tp JTAG_IR;
1007 2 mohor 
end
1008 
 
1009 
 
1010 9 mohor 
 
1011 
// Updating JTAG_IR (Instruction Register)
1012 
always @ (LatchedJTAG_IR)
1013 
begin
1014 
  EXTESTSelected          = 0;
1015 
  SAMPLE_PRELOADSelected  = 0;
1016 
  IDCODESelected          = 0;
1017 
  CHAIN_SELECTSelected    = 0;
1018 
  INTESTSelected          = 0;
1019 
  CLAMPSelected           = 0;
1020 
  CLAMPZSelected          = 0;
1021 
  HIGHZSelected           = 0;
1022 
  DEBUGSelected           = 0;
1023 
  BYPASSSelected          = 0;
1024 
 
1025 
  case(LatchedJTAG_IR)
1026 
    `EXTEST:            EXTESTSelected          = 1;    // External test
1027 
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
1028 
    `IDCODE:            IDCODESelected          = 1;    // ID Code
1029 
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
1030 
    `INTEST:            INTESTSelected          = 1;    // Internal test
1031 
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
1032 
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
1033 
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
1034 
    `DEBUG:             DEBUGSelected           = 1;    // Debug
1035 
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
1036 
    default:            BYPASSSelected          = 1;    // BYPASS
1037 
  endcase
1038 
end
1039 
 
1040 
 
1041 5 mohor 
/**********************************************************************************
1042 9 mohor 
*                                                                                 *
1043 
*   Multiplexing TDO and Tristate control                                         *
1044 
*                                                                                 *
1045 5 mohor 
**********************************************************************************/
1046 
wire TDOShifted;
1047 
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
1048 
/**********************************************************************************
1049 9 mohor 
*                                                                                 *
1050 
*   End:  Multiplexing TDO and Tristate control                                   *
1051 
*                                                                                 *
1052 5 mohor 
**********************************************************************************/
1053 
 
1054 
 
1055 
 
1056 9 mohor 
// This multiplexer can be expanded with number of user registers
1057 5 mohor 
reg TDOMuxed;
1058 12 mohor 
always @ (JTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
1059 2 mohor 
begin
1060 
  case(JTAG_IR)
1061 
    `IDCODE: // Reading ID code
1062 
      begin
1063 
        TDOMuxed<=#Tp TDOShifted;
1064 
      end
1065 
    `CHAIN_SELECT: // Selecting the chain
1066 
      begin
1067 
        TDOMuxed<=#Tp TDOShifted;
1068 
      end
1069 
    `DEBUG: // Debug
1070 
      begin
1071 
        TDOMuxed<=#Tp TDOShifted;
1072 
      end
1073 12 mohor 
    `SAMPLE_PRELOAD:  // Sampling/Preloading
1074 
      begin
1075 
        TDOMuxed<=#Tp BS_CHAIN_I;
1076 
      end
1077 
    `EXTEST:  // External test
1078 
      begin
1079 
        TDOMuxed<=#Tp BS_CHAIN_I;
1080 
      end
1081 2 mohor 
    default:  // BYPASS instruction
1082 
      begin
1083 
        TDOMuxed<=#Tp TDOBypassed;
1084 
      end
1085 
  endcase
1086 
end
1087 
 
1088 9 mohor 
// Tristate control for tdo_pad_o pin
1089 
assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
1090 2 mohor 
 
1091 
/**********************************************************************************
1092 
*                                                                                 *
1093 
*   End: Activating Instructions                                                  *
1094 
*                                                                                 *
1095 
**********************************************************************************/
1096 
 
1097 
/**********************************************************************************
1098 
*                                                                                 *
1099 
*   Bit counter                                                                   *
1100 
*                                                                                 *
1101 
**********************************************************************************/
1102 
 
1103 
 
1104 
always @ (posedge TCK or posedge RESET)
1105 
begin
1106 
  if(RESET)
1107 
    BitCounter[7:0]<=#Tp 0;
1108 
  else
1109 
  if(ShiftDR)
1110 
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
1111 
  else
1112 
  if(UpdateDR)
1113 
    BitCounter[7:0]<=#Tp 0;
1114 
end
1115 
 
1116 
 
1117 
 
1118 
/**********************************************************************************
1119 
*                                                                                 *
1120 
*   End: Bit counter                                                              *
1121 
*                                                                                 *
1122 
**********************************************************************************/
1123 
 
1124 
 
1125 
 
1126 
/**********************************************************************************
1127 
*                                                                                 *
1128 
*   Connecting Registers                                                          *
1129 
*                                                                                 *
1130 
**********************************************************************************/
1131 
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
1132 11 mohor 
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
1133 12 mohor 
                      .Bp(bp_i), .Reset(wb_rst_i),
1134 2 mohor 
                      `ifdef TRACE_ENABLED
1135 5 mohor 
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
1136 2 mohor 
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
1137 
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
1138 
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
1139 5 mohor 
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
1140 
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
1141 
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
1142 
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
1143 
                      .WpTriggerValid(WpTriggerValid),
1144 2 mohor 
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
1145 
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
1146 
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
1147 
                      .IQualifValid(IQualifValid),
1148 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1149 5 mohor 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1150 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
1151 2 mohor 
                      `endif
1152 5 mohor 
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
1153 
 
1154 2 mohor 
                     );
1155 
 
1156 
/**********************************************************************************
1157 
*                                                                                 *
1158 
*   End: Connecting Registers                                                     *
1159 
*                                                                                 *
1160 
**********************************************************************************/
1161 
 
1162 
 
1163 
/**********************************************************************************
1164 
*                                                                                 *
1165 
*   Connecting CRC module                                                         *
1166 
*                                                                                 *
1167 
**********************************************************************************/
1168 9 mohor 
wire AsyncResetCrc = RESET;
1169 
wire SyncResetCrc = UpdateDR_q;
1170 2 mohor 
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
1171 
 
1172 
wire EnableCrcIn = ShiftDR &
1173 9 mohor 
                  ( (CHAIN_SELECTSelected                 & (BitCounter<4))  |
1174 2 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
1175 12 mohor 
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
1176 
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
1177 9 mohor 
                  );
1178 2 mohor 
 
1179 
wire EnableCrcOut= ShiftDR &
1180 9 mohor 
                   (
1181 2 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
1182 12 mohor 
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
1183 
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
1184 2 mohor 
                    `ifdef TRACE_ENABLED
1185 
                                                                             |
1186 
                    ((DEBUGSelected & TraceTestScanChain) & (BitCounter<40))
1187 
                    `endif
1188 9 mohor 
                   );
1189 2 mohor 
 
1190 
// Calculating crc for input data
1191 9 mohor 
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1192 2 mohor 
                  .CrcOut(CalculatedCrcIn), .Clk(TCK));
1193 
 
1194 
// Calculating crc for output data
1195 9 mohor 
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1196 2 mohor 
                  .CrcOut(CalculatedCrcOut), .Clk(TCK));
1197 
 
1198 
 
1199 
// Generating CrcMatch signal
1200 
always @ (posedge TCK or posedge RESET)
1201 
begin
1202 
  if(RESET)
1203 
    CrcMatch <=#Tp 1'b0;
1204 
  else
1205 
  if(Exit1DR)
1206 
    begin
1207 
      if(CHAIN_SELECTSelected)
1208 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
1209 
      else
1210 
      if(RegisterScanChain & ~CHAIN_SELECTSelected)
1211 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
1212 
      else
1213 
      if(RiscDebugScanChain & ~CHAIN_SELECTSelected)
1214 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1215 12 mohor 
      else
1216 
      if(WishboneScanChain & ~CHAIN_SELECTSelected)
1217 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1218 2 mohor 
    end
1219 
end
1220 
 
1221 
 
1222 
// Active chain
1223 
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
1224 
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
1225 12 mohor 
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
1226 2 mohor 
 
1227 
`ifdef TRACE_ENABLED
1228 
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
1229 
`endif
1230 
 
1231 
/**********************************************************************************
1232 
*                                                                                 *
1233 
*   End: Connecting CRC module                                                    *
1234 
*                                                                                 *
1235 
**********************************************************************************/
1236 
 
1237 
/**********************************************************************************
1238 
*                                                                                 *
1239 
*   Connecting trace module                                                       *
1240 
*                                                                                 *
1241 
**********************************************************************************/
1242 
`ifdef TRACE_ENABLED
1243 11 mohor 
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
1244 9 mohor 
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
1245 11 mohor 
                      .Mclk(risc_clk_i), .Reset(RESET), .TraceChain(TraceChain),
1246 8 mohor 
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
1247 5 mohor 
                      .WpTrigger(WpTrigger),
1248 2 mohor 
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
1249 
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
1250 
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
1251 5 mohor 
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
1252 
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
1253 
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
1254 
                      .RecordINSTR(RecordINSTR),
1255 2 mohor 
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
1256 
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
1257 
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
1258 
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
1259 9 mohor 
                      .ReadBuffer(ReadTraceBufferPulse),
1260 2 mohor 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1261 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1262 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
1263 
                     );
1264 
`endif
1265 
/**********************************************************************************
1266 
*                                                                                 *
1267 
*   End: Connecting trace module                                                  *
1268 
*                                                                                 *
1269 
**********************************************************************************/
1270 
 
1271 
 
1272 
 
1273 9 mohor 
endmodule

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