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1 2 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  dbg_top.v                                                   ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the SoC/OpenRISC Development Interface ////
7 
////  http://www.opencores.org/cores/DebugInterface/              ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is avaliable in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000,2001 Authors                              ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 18 mohor 
// Revision 1.9  2001/10/19 11:40:01  mohor
49 
// dbg_timescale.v changed to timescale.v This is done for the simulation of
50 
// few different cores in a single project.
51 
//
52 17 mohor 
// Revision 1.8  2001/10/17 10:39:03  mohor
53 
// bs_chain_o added.
54 
//
55 15 mohor 
// Revision 1.7  2001/10/16 10:09:56  mohor
56 
// Signal names changed to lowercase.
57 13 mohor 
//
58 15 mohor 
//
59 13 mohor 
// Revision 1.6  2001/10/15 09:55:47  mohor
60 
// Wishbone interface added, few fixes for better performance,
61 
// hooks for boundary scan testing added.
62 
//
63 12 mohor 
// Revision 1.5  2001/09/24 14:06:42  mohor
64 
// Changes connected to the OpenRISC access (SPR read, SPR write).
65 
//
66 11 mohor 
// Revision 1.4  2001/09/20 10:11:25  mohor
67 
// Working version. Few bugs fixed, comments added.
68 
//
69 9 mohor 
// Revision 1.3  2001/09/19 11:55:13  mohor
70 
// Asynchronous set/reset not used in trace any more.
71 
//
72 8 mohor 
// Revision 1.2  2001/09/18 14:13:47  mohor
73 
// Trace fixed. Some registers changed, trace simplified.
74 
//
75 5 mohor 
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
76 
// Initial official release.
77 
//
78 2 mohor 
// Revision 1.3  2001/06/01 22:22:35  mohor
79 
// This is a backup. It is not a fully working version. Not for use, yet.
80 
//
81 
// Revision 1.2  2001/05/18 13:10:00  mohor
82 
// Headers changed. All additional information is now avaliable in the README.txt file.
83 
//
84 
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
85 
// Initial release
86 
//
87 
//
88 
 
89 17 mohor 
`include "timescale.v"
90 2 mohor 
`include "dbg_defines.v"
91 
 
92 
// Top module
93 9 mohor 
module dbg_top(
94 
                // JTAG pins
95 
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
96 12 mohor 
 
97 
                // Boundary Scan signals
98 15 mohor 
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
99 9 mohor 
 
100 
                // RISC signals
101 11 mohor 
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
102 
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
103 9 mohor 
 
104 12 mohor 
                // WISHBONE common signals
105 
                wb_rst_i, wb_clk_i,
106 
 
107 
                // WISHBONE master interface
108 
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
109 
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
110 
 
111 
 
112 2 mohor 
              );
113 
 
114 
parameter Tp = 1;
115 
 
116 9 mohor 
// JTAG pins
117 
input         tms_pad_i;                  // JTAG test mode select pad
118 
input         tck_pad_i;                  // JTAG test clock pad
119 
input         trst_pad_i;                 // JTAG test reset pad
120 
input         tdi_pad_i;                  // JTAG test data input pad
121 
output        tdo_pad_o;                  // JTAG test data output pad
122 2 mohor 
 
123 
 
124 12 mohor 
// Boundary Scan signals
125 13 mohor 
output capture_dr_o;
126 
output shift_dr_o;
127 
output update_dr_o;
128 
output extest_selected_o;
129 
input  bs_chain_i;
130 15 mohor 
output bs_chain_o;
131 12 mohor 
 
132 9 mohor 
// RISC signals
133 11 mohor 
input         risc_clk_i;                 // Master clock (RISC clock)
134 9 mohor 
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
135 
input  [10:0] wp_i;                       // Watchpoint inputs
136 
input         bp_i;                       // Breakpoint input
137 
input  [3:0]  lsstatus_i;                 // Load/store status inputs
138 
input  [1:0]  istatus_i;                  // Instruction status inputs
139 
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
140 
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
141 
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
142 
output                      risc_stall_o; // Stalls the RISC
143 11 mohor 
output                      reset_o;      // Resets the RISC
144 2 mohor 
 
145 
 
146 12 mohor 
// WISHBONE common signals
147 9 mohor 
input         wb_rst_i;                   // WISHBONE reset
148 12 mohor 
input         wb_clk_i;                   // WISHBONE clock
149 9 mohor 
 
150 12 mohor 
// WISHBONE master interface
151 
output [31:0] wb_adr_o;
152 
output [31:0] wb_dat_o;
153 
input  [31:0] wb_dat_i;
154 
output        wb_cyc_o;
155 
output        wb_stb_o;
156 
output  [3:0] wb_sel_o;
157 
output        wb_we_o;
158 
input         wb_ack_i;
159 
output        wb_cab_o;
160 
input         wb_err_i;
161 9 mohor 
 
162 12 mohor 
reg    [31:0] wb_adr_o;
163 
reg    [31:0] wb_dat_o;
164 
reg           wb_we_o;
165 
reg           wb_cyc_o;
166 
 
167 9 mohor 
// TAP states
168 2 mohor 
reg TestLogicReset;
169 
reg RunTestIdle;
170 
reg SelectDRScan;
171 
reg CaptureDR;
172 
reg ShiftDR;
173 
reg Exit1DR;
174 
reg PauseDR;
175 
reg Exit2DR;
176 
reg UpdateDR;
177 
 
178 
reg SelectIRScan;
179 
reg CaptureIR;
180 
reg ShiftIR;
181 
reg Exit1IR;
182 
reg PauseIR;
183 
reg Exit2IR;
184 
reg UpdateIR;
185 
 
186 9 mohor 
 
187 
// Defining which instruction is selected
188 2 mohor 
reg EXTESTSelected;
189 
reg SAMPLE_PRELOADSelected;
190 
reg IDCODESelected;
191 
reg CHAIN_SELECTSelected;
192 
reg INTESTSelected;
193 
reg CLAMPSelected;
194 
reg CLAMPZSelected;
195 
reg HIGHZSelected;
196 
reg DEBUGSelected;
197 
reg BYPASSSelected;
198 
 
199 9 mohor 
reg [31:0]  ADDR;
200 
reg [31:0]  DataOut;
201 
 
202 11 mohor 
reg [`OPSELECTWIDTH-1:0] opselect_o;      // Operation selection (selecting what kind of data is set to the risc_data_i)
203 
 
204 2 mohor 
reg [`CHAIN_ID_LENGTH-1:0] Chain;         // Selected chain
205 11 mohor 
reg [31:0]  RISC_DATAINLatch;             // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is
206 2 mohor 
                                          // accessed for reading
207 9 mohor 
reg [31:0]  RegisterReadLatch;            // Data when reading register is latched one TCK clock after the register is read.
208 
reg         RegAccessTck;                 // Indicates access to the registers (read or write)
209 
reg         RISCAccessTck;                // Indicates access to the RISC (read or write)
210 
reg [7:0]   BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
211 
reg         RW;                           // Read/Write bit
212 
reg         CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
213 2 mohor 
 
214 9 mohor 
reg         RegAccess_q;                  // Delayed signals used for accessing the registers
215 
reg         RegAccess_q2;                 // Delayed signals used for accessing the registers
216 
reg         RISCAccess_q;                 // Delayed signals used for accessing the RISC
217 
reg         RISCAccess_q2;                // Delayed signals used for accessing the RISC
218 2 mohor 
 
219 12 mohor 
reg         wb_AccessTck;                 // Indicates access to the WISHBONE
220 
reg [31:0]  WBReadLatch;                  // Data latched during WISHBONE read
221 
reg         WBErrorLatch;                 // Error latched during WISHBONE read
222 2 mohor 
 
223 9 mohor 
wire TCK = tck_pad_i;
224 
wire TMS = tms_pad_i;
225 
wire TDI = tdi_pad_i;
226 18 mohor 
wire trst = ~trst_pad_i;                  // trst_pad_i is active low
227 2 mohor 
 
228 9 mohor 
wire [31:0]             RegDataIn;        // Data from registers (read data)
229 
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
230 2 mohor 
 
231 9 mohor 
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
232 
wire RiscReset_reg;                       // RISC is reset by setting the register bit
233 
wire RiscStall_trace;                     // RISC is stalled by trace module
234 
 
235 
 
236 
wire RegisterScanChain;                   // Register Scan chain selected
237 
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
238 12 mohor 
wire WishboneScanChain;                   // WISHBONE Scan chain selected
239 11 mohor 
 
240 
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
241 
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
242 
wire RiscStall_access;                    // Stalling RISC because of the read or write access
243 
 
244 9 mohor 
 
245 13 mohor 
assign capture_dr_o       = CaptureDR;
246 
assign shift_dr_o         = ShiftDR;
247 
assign update_dr_o        = UpdateDR;
248 
assign extest_selected_o  = EXTESTSelected;
249 
wire   BS_CHAIN_I         = bs_chain_i;
250 15 mohor 
assign bs_chain_o         = tdi_pad_i;
251 
 
252 
 
253 9 mohor 
// This signals are used only when TRACE is used in the design
254 2 mohor 
`ifdef TRACE_ENABLED
255 9 mohor 
  wire [39:0] TraceChain;                 // Chain that comes from trace module
256 
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with TCK)
257 
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
258 
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
259 
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
260 2 mohor 
 
261 
  // Outputs from registers
262 9 mohor 
  wire ContinMode;                        // Trace working in continous mode
263 
  wire TraceEnable;                       // Trace enabled
264 2 mohor 
 
265 9 mohor 
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
266 
  wire        BpTrigger;                  // Breakpoint starts trigger
267 
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
268 
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
269 
  wire [1:0]  TriggerOper;                // Trigger operation
270 2 mohor 
 
271 9 mohor 
  wire        WpTriggerValid;             // Watchpoint trigger is valid
272 
  wire        BpTriggerValid;             // Breakpoint trigger is valid
273 
  wire        LSSTriggerValid;            // Load/store status trigger is valid
274 
  wire        ITriggerValid;              // Instruction status trigger is valid
275 2 mohor 
 
276 9 mohor 
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
277 
  wire        BpQualif;                   // Breakpoint starts qualifier
278 
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
279 
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
280 
  wire [1:0]  QualifOper;                 // Qualifier operation
281 2 mohor 
 
282 9 mohor 
  wire        WpQualifValid;              // Watchpoint qualifier is valid
283 
  wire        BpQualifValid;              // Breakpoint qualifier is valid
284 
  wire        LSSQualifValid;             // Load/store status qualifier is valid
285 
  wire        IQualifValid;               // Instruction status qualifier is valid
286 2 mohor 
 
287 9 mohor 
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
288 
  wire        BpStop;                     // Breakpoint stops recording of the trace
289 
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
290 
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
291 
  wire [1:0]  StopOper;                   // Stop operation
292 2 mohor 
 
293 9 mohor 
  wire WpStopValid;                       // Watchpoint stop is valid
294 
  wire BpStopValid;                       // Breakpoint stop is valid
295 
  wire LSSStopValid;                      // Load/store status stop is valid
296 
  wire IStopValid;                        // Instruction status stop is valid
297 2 mohor 
 
298 9 mohor 
  wire RecordPC;                          // Recording program counter
299 
  wire RecordLSEA;                        // Recording load/store effective address
300 
  wire RecordLDATA;                       // Recording load data
301 
  wire RecordSDATA;                       // Recording store data
302 
  wire RecordReadSPR;                     // Recording read SPR
303 
  wire RecordWriteSPR;                    // Recording write SPR
304 
  wire RecordINSTR;                       // Recording instruction
305 2 mohor 
 
306 
  // End: Outputs from registers
307 
 
308 9 mohor 
  wire TraceTestScanChain;                // Trace Test Scan chain selected
309 
  wire [47:0] Trace_Data;                 // Trace data
310 2 mohor 
 
311 11 mohor 
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
312 
                                          // data is set to the risc_data_i)
313 
 
314 2 mohor 
`endif
315 
 
316 
 
317 
/**********************************************************************************
318 
*                                                                                 *
319 
*   TAP State Machine: Fully JTAG compliant                                       *
320 
*                                                                                 *
321 
**********************************************************************************/
322 
 
323 
// TestLogicReset state
324 18 mohor 
always @ (posedge TCK or posedge trst)
325 2 mohor 
begin
326 18 mohor 
  if(trst)
327 2 mohor 
    TestLogicReset<=#Tp 1;
328 
  else
329 
    begin
330 
      if(TMS & (TestLogicReset | SelectIRScan))
331 
        TestLogicReset<=#Tp 1;
332 
      else
333 
        TestLogicReset<=#Tp 0;
334 
    end
335 
end
336 
 
337 
// RunTestIdle state
338 18 mohor 
always @ (posedge TCK or posedge trst)
339 2 mohor 
begin
340 18 mohor 
  if(trst)
341 2 mohor 
    RunTestIdle<=#Tp 0;
342 
  else
343 
    begin
344 
      if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
345 
        RunTestIdle<=#Tp 1;
346 
      else
347 
        RunTestIdle<=#Tp 0;
348 
    end
349 
end
350 
 
351 
// SelectDRScan state
352 18 mohor 
always @ (posedge TCK or posedge trst)
353 2 mohor 
begin
354 18 mohor 
  if(trst)
355 2 mohor 
    SelectDRScan<=#Tp 0;
356 
  else
357 
    begin
358 
      if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
359 
        SelectDRScan<=#Tp 1;
360 
      else
361 
        SelectDRScan<=#Tp 0;
362 
    end
363 
end
364 
 
365 
// CaptureDR state
366 18 mohor 
always @ (posedge TCK or posedge trst)
367 2 mohor 
begin
368 18 mohor 
  if(trst)
369 2 mohor 
    CaptureDR<=#Tp 0;
370 
  else
371 
    begin
372 
      if(~TMS & SelectDRScan)
373 
        CaptureDR<=#Tp 1;
374 
      else
375 
        CaptureDR<=#Tp 0;
376 
    end
377 
end
378 
 
379 
// ShiftDR state
380 18 mohor 
always @ (posedge TCK or posedge trst)
381 2 mohor 
begin
382 18 mohor 
  if(trst)
383 2 mohor 
    ShiftDR<=#Tp 0;
384 
  else
385 
    begin
386 
      if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
387 
        ShiftDR<=#Tp 1;
388 
      else
389 
        ShiftDR<=#Tp 0;
390 
    end
391 
end
392 
 
393 
// Exit1DR state
394 18 mohor 
always @ (posedge TCK or posedge trst)
395 2 mohor 
begin
396 18 mohor 
  if(trst)
397 2 mohor 
    Exit1DR<=#Tp 0;
398 
  else
399 
    begin
400 
      if(TMS & (CaptureDR | ShiftDR))
401 
        Exit1DR<=#Tp 1;
402 
      else
403 
        Exit1DR<=#Tp 0;
404 
    end
405 
end
406 
 
407 
// PauseDR state
408 18 mohor 
always @ (posedge TCK or posedge trst)
409 2 mohor 
begin
410 18 mohor 
  if(trst)
411 2 mohor 
    PauseDR<=#Tp 0;
412 
  else
413 
    begin
414 
      if(~TMS & (Exit1DR | PauseDR))
415 
        PauseDR<=#Tp 1;
416 
      else
417 
        PauseDR<=#Tp 0;
418 
    end
419 
end
420 
 
421 
// Exit2DR state
422 18 mohor 
always @ (posedge TCK or posedge trst)
423 2 mohor 
begin
424 18 mohor 
  if(trst)
425 2 mohor 
    Exit2DR<=#Tp 0;
426 
  else
427 
    begin
428 
      if(TMS & PauseDR)
429 
        Exit2DR<=#Tp 1;
430 
      else
431 
        Exit2DR<=#Tp 0;
432 
    end
433 
end
434 
 
435 
// UpdateDR state
436 18 mohor 
always @ (posedge TCK or posedge trst)
437 2 mohor 
begin
438 18 mohor 
  if(trst)
439 2 mohor 
    UpdateDR<=#Tp 0;
440 
  else
441 
    begin
442 
      if(TMS & (Exit1DR | Exit2DR))
443 
        UpdateDR<=#Tp 1;
444 
      else
445 
        UpdateDR<=#Tp 0;
446 
    end
447 
end
448 
 
449 9 mohor 
// Delayed UpdateDR state
450 2 mohor 
reg UpdateDR_q;
451 
always @ (posedge TCK)
452 
begin
453 
  UpdateDR_q<=#Tp UpdateDR;
454 
end
455 
 
456 
 
457 
// SelectIRScan state
458 18 mohor 
always @ (posedge TCK or posedge trst)
459 2 mohor 
begin
460 18 mohor 
  if(trst)
461 2 mohor 
    SelectIRScan<=#Tp 0;
462 
  else
463 
    begin
464 
      if(TMS & SelectDRScan)
465 
        SelectIRScan<=#Tp 1;
466 
      else
467 
        SelectIRScan<=#Tp 0;
468 
    end
469 
end
470 
 
471 
// CaptureIR state
472 18 mohor 
always @ (posedge TCK or posedge trst)
473 2 mohor 
begin
474 18 mohor 
  if(trst)
475 2 mohor 
    CaptureIR<=#Tp 0;
476 
  else
477 
    begin
478 
      if(~TMS & SelectIRScan)
479 
        CaptureIR<=#Tp 1;
480 
      else
481 
        CaptureIR<=#Tp 0;
482 
    end
483 
end
484 
 
485 
// ShiftIR state
486 18 mohor 
always @ (posedge TCK or posedge trst)
487 2 mohor 
begin
488 18 mohor 
  if(trst)
489 2 mohor 
    ShiftIR<=#Tp 0;
490 
  else
491 
    begin
492 
      if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
493 
        ShiftIR<=#Tp 1;
494 
      else
495 
        ShiftIR<=#Tp 0;
496 
    end
497 
end
498 
 
499 
// Exit1IR state
500 18 mohor 
always @ (posedge TCK or posedge trst)
501 2 mohor 
begin
502 18 mohor 
  if(trst)
503 2 mohor 
    Exit1IR<=#Tp 0;
504 
  else
505 
    begin
506 
      if(TMS & (CaptureIR | ShiftIR))
507 
        Exit1IR<=#Tp 1;
508 
      else
509 
        Exit1IR<=#Tp 0;
510 
    end
511 
end
512 
 
513 
// PauseIR state
514 18 mohor 
always @ (posedge TCK or posedge trst)
515 2 mohor 
begin
516 18 mohor 
  if(trst)
517 2 mohor 
    PauseIR<=#Tp 0;
518 
  else
519 
    begin
520 
      if(~TMS & (Exit1IR | PauseIR))
521 
        PauseIR<=#Tp 1;
522 
      else
523 
        PauseIR<=#Tp 0;
524 
    end
525 
end
526 
 
527 
// Exit2IR state
528 18 mohor 
always @ (posedge TCK or posedge trst)
529 2 mohor 
begin
530 18 mohor 
  if(trst)
531 2 mohor 
    Exit2IR<=#Tp 0;
532 
  else
533 
    begin
534 
      if(TMS & PauseIR)
535 
        Exit2IR<=#Tp 1;
536 
      else
537 
        Exit2IR<=#Tp 0;
538 
    end
539 
end
540 
 
541 
// UpdateIR state
542 18 mohor 
always @ (posedge TCK or posedge trst)
543 2 mohor 
begin
544 18 mohor 
  if(trst)
545 2 mohor 
    UpdateIR<=#Tp 0;
546 
  else
547 
    begin
548 
      if(TMS & (Exit1IR | Exit2IR))
549 
        UpdateIR<=#Tp 1;
550 
      else
551 
        UpdateIR<=#Tp 0;
552 
    end
553 
end
554 
 
555 
/**********************************************************************************
556 
*                                                                                 *
557 
*   End: TAP State Machine                                                        *
558 
*                                                                                 *
559 
**********************************************************************************/
560 
 
561 
 
562 
 
563 
/**********************************************************************************
564 
*                                                                                 *
565 
*   JTAG_IR:  JTAG Instruction Register                                           *
566 
*                                                                                 *
567 
**********************************************************************************/
568 9 mohor 
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
569 2 mohor 
 
570 9 mohor 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
571 
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
572 
 
573 2 mohor 
reg TDOInstruction;
574 
 
575 18 mohor 
always @ (posedge TCK or posedge trst)
576 2 mohor 
begin
577 18 mohor 
  if(trst)
578 2 mohor 
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
579 
  else
580 
    begin
581 
      if(CaptureIR)
582 
        begin
583 
          JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
584 
          JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
585 
        end
586 
      else
587 
        begin
588 
          if(ShiftIR)
589 
            begin
590 
              JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
591 
            end
592 
        end
593 
    end
594 
end
595 
 
596 
 
597 
//TDO is changing on the falling edge of TCK
598 
always @ (negedge TCK)
599 
begin
600 
  if(ShiftIR)
601 
    TDOInstruction <= #Tp JTAG_IR[0];
602 
end
603 9 mohor 
 
604 2 mohor 
/**********************************************************************************
605 
*                                                                                 *
606 
*   End: JTAG_IR                                                                  *
607 
*                                                                                 *
608 
**********************************************************************************/
609 
 
610 
 
611 
/**********************************************************************************
612 
*                                                                                 *
613 
*   JTAG_DR:  JTAG Data Register                                                  *
614 
*                                                                                 *
615 
**********************************************************************************/
616 
wire [31:0] IDCodeValue = `IDCODE_VALUE;  // IDCODE value is 32-bit long.
617 
 
618 
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
619 
reg TDOData;
620 
 
621 
 
622 18 mohor 
always @ (posedge TCK or posedge trst)
623 2 mohor 
begin
624 18 mohor 
  if(trst)
625 2 mohor 
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
626 
  else
627 
  if(ShiftDR)
628 
    JTAG_DR_IN[BitCounter]<=#Tp TDI;
629 
end
630 
 
631 
wire [72:0] RISC_Data;
632 
wire [45:0] Register_Data;
633 12 mohor 
wire [72:0] WISHBONE_Data;
634 
wire wb_Access_wbClk;
635 2 mohor 
 
636 
assign RISC_Data      = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
637 
assign Register_Data  = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
638 12 mohor 
assign WISHBONE_Data  = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
639 2 mohor 
 
640 12 mohor 
 
641 2 mohor 
`ifdef TRACE_ENABLED
642 
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
643 
`endif
644 
 
645 
//TDO is changing on the falling edge of TCK
646 18 mohor 
always @ (negedge TCK or posedge trst)
647 2 mohor 
begin
648 18 mohor 
  if(trst)
649 2 mohor 
    begin
650 
      TDOData <= #Tp 0;
651 
      `ifdef TRACE_ENABLED
652 
      ReadBuffer_Tck<=#Tp 0;
653 
      `endif
654 
    end
655 
  else
656 
  if(UpdateDR)
657 
    begin
658 
      TDOData <= #Tp CrcMatch;
659 
      `ifdef TRACE_ENABLED
660 9 mohor 
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
661 
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
662 2 mohor 
      `endif
663 
    end
664 
  else
665 
    begin
666 
      if(ShiftDR)
667 
        begin
668 
          if(IDCODESelected)
669 9 mohor 
            TDOData <= #Tp IDCodeValue[BitCounter];           // IDCODE is shifted out
670 2 mohor 
          else
671 
          if(CHAIN_SELECTSelected)
672 
            TDOData <= #Tp 0;
673 
          else
674 
          if(DEBUGSelected)
675 
            begin
676 
              if(RiscDebugScanChain)
677 9 mohor 
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
678 2 mohor 
              else
679 
              if(RegisterScanChain)
680 9 mohor 
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
681 12 mohor 
              else
682 
              if(WishboneScanChain)
683 
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
684 2 mohor 
              `ifdef TRACE_ENABLED
685 
              else
686 
              if(TraceTestScanChain)
687 9 mohor 
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
688 2 mohor 
              `endif
689 
            end
690 
        end
691 
      else
692 
        begin
693 
          TDOData <= #Tp 0;
694 
          `ifdef TRACE_ENABLED
695 
          ReadBuffer_Tck<=#Tp 0;
696 
          `endif
697 
        end
698 
    end
699 
end
700 
 
701 
/**********************************************************************************
702 
*                                                                                 *
703 
*   End: JTAG_DR                                                                  *
704 
*                                                                                 *
705 
**********************************************************************************/
706 
 
707 
 
708 
 
709 
/**********************************************************************************
710 
*                                                                                 *
711 
*   CHAIN_SELECT logic                                                            *
712 
*                                                                                 *
713 
**********************************************************************************/
714 18 mohor 
always @ (posedge TCK or posedge trst)
715 2 mohor 
begin
716 18 mohor 
  if(trst)
717 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
718 2 mohor 
  else
719 
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
720 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
721 2 mohor 
end
722 
 
723 
 
724 
 
725 
/**********************************************************************************
726 
*                                                                                 *
727 
*   Register read/write logic                                                     *
728 
*   RISC registers read/write logic                                               *
729 
*                                                                                 *
730 
**********************************************************************************/
731 18 mohor 
always @ (posedge TCK or posedge trst)
732 2 mohor 
begin
733 18 mohor 
  if(trst)
734 2 mohor 
    begin
735 
      ADDR[31:0]        <=#Tp 32'h0;
736 
      DataOut[31:0]     <=#Tp 32'h0;
737 
      RW                <=#Tp 1'b0;
738 
      RegAccessTck      <=#Tp 1'b0;
739 
      RISCAccessTck     <=#Tp 1'b0;
740 12 mohor 
      wb_adr_o          <=#Tp 32'h0;
741 
      wb_we_o           <=#Tp 1'h0;
742 
      wb_dat_o          <=#Tp 32'h0;
743 
      wb_AccessTck      <=#Tp 1'h0;
744 2 mohor 
    end
745 
  else
746 
  if(UpdateDR & DEBUGSelected & CrcMatch)
747 
    begin
748 
      if(RegisterScanChain)
749 
        begin
750 
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
751 
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
752 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
753 
          RegAccessTck      <=#Tp 1'b1;
754 
        end
755 
      else
756 
      if(RiscDebugScanChain)
757 
        begin
758 
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
759 
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
760 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
761 
          RISCAccessTck     <=#Tp 1'b1;
762 
        end
763 12 mohor 
      else
764 
      if(WishboneScanChain)
765 
        begin
766 
          wb_adr_o          <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
767 
          wb_we_o           <=#Tp JTAG_DR_IN[32];     // latch R/W bit
768 
          wb_dat_o          <=#Tp JTAG_DR_IN[64:33];  // latch data for write
769 
          wb_AccessTck      <=#Tp 1'b1;               //
770 
        end
771 2 mohor 
    end
772 
  else
773 
    begin
774 
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one TCK clock period only
775 
      RISCAccessTck     <=#Tp 1'b0;
776 12 mohor 
      wb_AccessTck      <=#Tp 1'b0;
777 2 mohor 
    end
778 
end
779 
 
780 12 mohor 
assign wb_sel_o[3:0] = 4'hf;
781 
assign wb_cab_o = 1'b0;
782 9 mohor 
 
783 2 mohor 
 
784 11 mohor 
// Synchronizing the RegAccess signal to risc_clk_i clock
785 18 mohor 
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
786 2 mohor 
                         .set2(RegAccessTck), .sync_out(RegAccess)
787 
                        );
788 
 
789 11 mohor 
// Synchronizing the RISCAccess signal to risc_clk_i clock
790 18 mohor 
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
791 2 mohor 
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
792 
                        );
793 
 
794 
 
795 12 mohor 
// Synchronizing the wb_Access signal to wishbone clock
796 18 mohor 
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),      .clk2(TCK),          .reset1(wb_rst_i),  .reset2(trst),
797 12 mohor 
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
798 
                        );
799 
 
800 
 
801 
 
802 
 
803 
 
804 9 mohor 
// Delayed signals used for accessing registers and RISC
805 18 mohor 
always @ (posedge risc_clk_i or posedge wb_rst_i)
806 2 mohor 
begin
807 18 mohor 
  if(wb_rst_i)
808 2 mohor 
    begin
809 
      RegAccess_q   <=#Tp 1'b0;
810 
      RegAccess_q2  <=#Tp 1'b0;
811 
      RISCAccess_q  <=#Tp 1'b0;
812 
      RISCAccess_q2 <=#Tp 1'b0;
813 
    end
814 
  else
815 
    begin
816 
      RegAccess_q   <=#Tp RegAccess;
817 
      RegAccess_q2  <=#Tp RegAccess_q;
818 
      RISCAccess_q  <=#Tp RISCAccess;
819 
      RISCAccess_q2 <=#Tp RISCAccess_q;
820 
    end
821 
end
822 
 
823 9 mohor 
 
824 2 mohor 
// Latching data read from registers
825 18 mohor 
always @ (posedge risc_clk_i or posedge wb_rst_i)
826 2 mohor 
begin
827 18 mohor 
  if(wb_rst_i)
828 2 mohor 
    RegisterReadLatch[31:0]<=#Tp 0;
829 
  else
830 
  if(RegAccess_q & ~RegAccess_q2)
831 
    RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
832 
end
833 
 
834 
 
835 9 mohor 
// Chip select and read/write signals for accessing RISC
836 11 mohor 
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
837 
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
838 
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
839 2 mohor 
 
840 
 
841 12 mohor 
reg wb_Access_wbClk_q;
842 
// Delayed signals used for accessing WISHBONE
843 18 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
844 12 mohor 
begin
845 18 mohor 
  if(wb_rst_i)
846 12 mohor 
    wb_Access_wbClk_q <=#Tp 1'b0;
847 
  else
848 
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
849 
end
850 
 
851 18 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
852 12 mohor 
begin
853 18 mohor 
  if(wb_rst_i)
854 12 mohor 
    wb_cyc_o <=#Tp 1'b0;
855 
  else
856 
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
857 
    wb_cyc_o <=#Tp 1'b1;
858 
  else
859 
  if(wb_ack_i | wb_err_i)
860 
    wb_cyc_o <=#Tp 1'b0;
861 
end
862 
 
863 
assign wb_stb_o = wb_cyc_o;
864 
 
865 
 
866 
// Latching data read from registers
867 18 mohor 
always @ (posedge risc_clk_i or posedge wb_rst_i)
868 12 mohor 
begin
869 18 mohor 
  if(wb_rst_i)
870 12 mohor 
    WBReadLatch[31:0]<=#Tp 32'h0;
871 
  else
872 
  if(wb_ack_i)
873 
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
874 
end
875 
 
876 
// Latching WISHBONE error cycle
877 18 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
878 12 mohor 
begin
879 18 mohor 
  if(wb_rst_i)
880 12 mohor 
    WBErrorLatch<=#Tp 1'b0;
881 
  else
882 
  if(wb_err_i)
883 
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
884 
  if(wb_ack_i)
885 
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
886 
end
887 
 
888 
 
889 9 mohor 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
890 5 mohor 
`ifdef TRACE_ENABLED
891 11 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
892 5 mohor 
`else
893 12 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
894 5 mohor 
`endif
895 
 
896 11 mohor 
assign  reset_o = RiscReset_reg;
897 5 mohor 
 
898 
 
899 12 mohor 
`ifdef TRACE_ENABLED
900 11 mohor 
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
901 12 mohor 
`else
902 
always @ (RiscStall_write_access or RiscStall_read_access)
903 
`endif
904 11 mohor 
begin
905 
  if(RiscStall_write_access)
906 
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
907 
  else
908 
  if(RiscStall_read_access)
909 
    opselect_o = `DEBUG_READ_SPR;   // Read spr
910 
  else
911 12 mohor 
`ifdef TRACE_ENABLED
912 11 mohor 
    opselect_o = opselect_trace;
913 12 mohor 
`else
914 
    opselect_o = 3'h0;
915 
`endif
916 11 mohor 
end
917 9 mohor 
 
918 11 mohor 
 
919 
 
920 2 mohor 
// Latching data read from RISC
921 18 mohor 
always @ (posedge risc_clk_i or posedge wb_rst_i)
922 2 mohor 
begin
923 18 mohor 
  if(wb_rst_i)
924 2 mohor 
    RISC_DATAINLatch[31:0]<=#Tp 0;
925 
  else
926 
  if(RISCAccess_q & ~RISCAccess_q2)
927 12 mohor 
    RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
928 2 mohor 
end
929 
 
930 12 mohor 
assign risc_addr_o = ADDR;
931 
assign risc_data_o = DataOut;
932 2 mohor 
 
933 
 
934 
 
935 
/**********************************************************************************
936 
*                                                                                 *
937 
*   Read Trace buffer logic                                                       *
938 
*                                                                                 *
939 
**********************************************************************************/
940 
`ifdef TRACE_ENABLED
941 
 
942 9 mohor 
 
943 11 mohor 
// Synchronizing the trace read buffer signal to risc_clk_i clock
944 18 mohor 
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
945 9 mohor 
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
946 
                        );
947 
 
948 
 
949 
 
950 18 mohor 
  always @(posedge risc_clk_i or posedge wb_rst_i)
951 2 mohor 
  begin
952 18 mohor 
    if(wb_rst_i)
953 9 mohor 
      ReadTraceBuffer_q <=#Tp 0;
954 2 mohor 
    else
955 9 mohor 
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
956 2 mohor 
  end
957 9 mohor 
 
958 
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
959 
 
960 2 mohor 
`endif
961 
 
962 
/**********************************************************************************
963 
*                                                                                 *
964 
*   End: Read Trace buffer logic                                                  *
965 
*                                                                                 *
966 
**********************************************************************************/
967 
 
968 
 
969 
/**********************************************************************************
970 
*                                                                                 *
971 
*   Bypass logic                                                                  *
972 
*                                                                                 *
973 
**********************************************************************************/
974 
reg BypassRegister;
975 
reg TDOBypassed;
976 
 
977 
always @ (posedge TCK)
978 
begin
979 
  if(ShiftDR)
980 
    BypassRegister<=#Tp TDI;
981 
end
982 
 
983 
always @ (negedge TCK)
984 
begin
985 
    TDOBypassed<=#Tp BypassRegister;
986 
end
987 
/**********************************************************************************
988 
*                                                                                 *
989 
*   End: Bypass logic                                                             *
990 
*                                                                                 *
991 
**********************************************************************************/
992 
 
993 
 
994 
 
995 
 
996 
 
997 
/**********************************************************************************
998 
*                                                                                 *
999 
*   Activating Instructions                                                       *
1000 
*                                                                                 *
1001 
**********************************************************************************/
1002 
 
1003 
// Updating JTAG_IR (Instruction Register)
1004 18 mohor 
always @ (posedge TCK or posedge trst)
1005 2 mohor 
begin
1006 18 mohor 
  if(trst)
1007 9 mohor 
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
1008 2 mohor 
  else
1009 9 mohor 
  if(UpdateIR)
1010 
    LatchedJTAG_IR <=#Tp JTAG_IR;
1011 2 mohor 
end
1012 
 
1013 
 
1014 9 mohor 
 
1015 
// Updating JTAG_IR (Instruction Register)
1016 
always @ (LatchedJTAG_IR)
1017 
begin
1018 
  EXTESTSelected          = 0;
1019 
  SAMPLE_PRELOADSelected  = 0;
1020 
  IDCODESelected          = 0;
1021 
  CHAIN_SELECTSelected    = 0;
1022 
  INTESTSelected          = 0;
1023 
  CLAMPSelected           = 0;
1024 
  CLAMPZSelected          = 0;
1025 
  HIGHZSelected           = 0;
1026 
  DEBUGSelected           = 0;
1027 
  BYPASSSelected          = 0;
1028 
 
1029 
  case(LatchedJTAG_IR)
1030 
    `EXTEST:            EXTESTSelected          = 1;    // External test
1031 
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
1032 
    `IDCODE:            IDCODESelected          = 1;    // ID Code
1033 
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
1034 
    `INTEST:            INTESTSelected          = 1;    // Internal test
1035 
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
1036 
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
1037 
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
1038 
    `DEBUG:             DEBUGSelected           = 1;    // Debug
1039 
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
1040 
    default:            BYPASSSelected          = 1;    // BYPASS
1041 
  endcase
1042 
end
1043 
 
1044 
 
1045 5 mohor 
/**********************************************************************************
1046 9 mohor 
*                                                                                 *
1047 
*   Multiplexing TDO and Tristate control                                         *
1048 
*                                                                                 *
1049 5 mohor 
**********************************************************************************/
1050 
wire TDOShifted;
1051 
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
1052 
/**********************************************************************************
1053 9 mohor 
*                                                                                 *
1054 
*   End:  Multiplexing TDO and Tristate control                                   *
1055 
*                                                                                 *
1056 5 mohor 
**********************************************************************************/
1057 
 
1058 
 
1059 
 
1060 9 mohor 
// This multiplexer can be expanded with number of user registers
1061 5 mohor 
reg TDOMuxed;
1062 12 mohor 
always @ (JTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
1063 2 mohor 
begin
1064 
  case(JTAG_IR)
1065 
    `IDCODE: // Reading ID code
1066 
      begin
1067 
        TDOMuxed<=#Tp TDOShifted;
1068 
      end
1069 
    `CHAIN_SELECT: // Selecting the chain
1070 
      begin
1071 
        TDOMuxed<=#Tp TDOShifted;
1072 
      end
1073 
    `DEBUG: // Debug
1074 
      begin
1075 
        TDOMuxed<=#Tp TDOShifted;
1076 
      end
1077 12 mohor 
    `SAMPLE_PRELOAD:  // Sampling/Preloading
1078 
      begin
1079 
        TDOMuxed<=#Tp BS_CHAIN_I;
1080 
      end
1081 
    `EXTEST:  // External test
1082 
      begin
1083 
        TDOMuxed<=#Tp BS_CHAIN_I;
1084 
      end
1085 2 mohor 
    default:  // BYPASS instruction
1086 
      begin
1087 
        TDOMuxed<=#Tp TDOBypassed;
1088 
      end
1089 
  endcase
1090 
end
1091 
 
1092 9 mohor 
// Tristate control for tdo_pad_o pin
1093 
assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
1094 2 mohor 
 
1095 
/**********************************************************************************
1096 
*                                                                                 *
1097 
*   End: Activating Instructions                                                  *
1098 
*                                                                                 *
1099 
**********************************************************************************/
1100 
 
1101 
/**********************************************************************************
1102 
*                                                                                 *
1103 
*   Bit counter                                                                   *
1104 
*                                                                                 *
1105 
**********************************************************************************/
1106 
 
1107 
 
1108 18 mohor 
always @ (posedge TCK or posedge trst)
1109 2 mohor 
begin
1110 18 mohor 
  if(trst)
1111 2 mohor 
    BitCounter[7:0]<=#Tp 0;
1112 
  else
1113 
  if(ShiftDR)
1114 
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
1115 
  else
1116 
  if(UpdateDR)
1117 
    BitCounter[7:0]<=#Tp 0;
1118 
end
1119 
 
1120 
 
1121 
 
1122 
/**********************************************************************************
1123 
*                                                                                 *
1124 
*   End: Bit counter                                                              *
1125 
*                                                                                 *
1126 
**********************************************************************************/
1127 
 
1128 
 
1129 
 
1130 
/**********************************************************************************
1131 
*                                                                                 *
1132 
*   Connecting Registers                                                          *
1133 
*                                                                                 *
1134 
**********************************************************************************/
1135 
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
1136 11 mohor 
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
1137 12 mohor 
                      .Bp(bp_i), .Reset(wb_rst_i),
1138 2 mohor 
                      `ifdef TRACE_ENABLED
1139 5 mohor 
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
1140 2 mohor 
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
1141 
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
1142 
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
1143 5 mohor 
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
1144 
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
1145 
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
1146 
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
1147 
                      .WpTriggerValid(WpTriggerValid),
1148 2 mohor 
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
1149 
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
1150 
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
1151 
                      .IQualifValid(IQualifValid),
1152 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1153 5 mohor 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1154 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
1155 2 mohor 
                      `endif
1156 5 mohor 
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
1157 
 
1158 2 mohor 
                     );
1159 
 
1160 
/**********************************************************************************
1161 
*                                                                                 *
1162 
*   End: Connecting Registers                                                     *
1163 
*                                                                                 *
1164 
**********************************************************************************/
1165 
 
1166 
 
1167 
/**********************************************************************************
1168 
*                                                                                 *
1169 
*   Connecting CRC module                                                         *
1170 
*                                                                                 *
1171 
**********************************************************************************/
1172 18 mohor 
wire AsyncResetCrc = trst;
1173 9 mohor 
wire SyncResetCrc = UpdateDR_q;
1174 2 mohor 
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
1175 
 
1176 
wire EnableCrcIn = ShiftDR &
1177 9 mohor 
                  ( (CHAIN_SELECTSelected                 & (BitCounter<4))  |
1178 2 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
1179 12 mohor 
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
1180 
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
1181 9 mohor 
                  );
1182 2 mohor 
 
1183 
wire EnableCrcOut= ShiftDR &
1184 9 mohor 
                   (
1185 2 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
1186 12 mohor 
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
1187 
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
1188 2 mohor 
                    `ifdef TRACE_ENABLED
1189 
                                                                             |
1190 
                    ((DEBUGSelected & TraceTestScanChain) & (BitCounter<40))
1191 
                    `endif
1192 9 mohor 
                   );
1193 2 mohor 
 
1194 
// Calculating crc for input data
1195 9 mohor 
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1196 2 mohor 
                  .CrcOut(CalculatedCrcIn), .Clk(TCK));
1197 
 
1198 
// Calculating crc for output data
1199 9 mohor 
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1200 2 mohor 
                  .CrcOut(CalculatedCrcOut), .Clk(TCK));
1201 
 
1202 
 
1203 
// Generating CrcMatch signal
1204 18 mohor 
always @ (posedge TCK or posedge trst)
1205 2 mohor 
begin
1206 18 mohor 
  if(trst)
1207 2 mohor 
    CrcMatch <=#Tp 1'b0;
1208 
  else
1209 
  if(Exit1DR)
1210 
    begin
1211 
      if(CHAIN_SELECTSelected)
1212 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
1213 
      else
1214 
      if(RegisterScanChain & ~CHAIN_SELECTSelected)
1215 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
1216 
      else
1217 
      if(RiscDebugScanChain & ~CHAIN_SELECTSelected)
1218 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1219 12 mohor 
      else
1220 
      if(WishboneScanChain & ~CHAIN_SELECTSelected)
1221 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1222 2 mohor 
    end
1223 
end
1224 
 
1225 
 
1226 
// Active chain
1227 
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
1228 
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
1229 12 mohor 
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
1230 2 mohor 
 
1231 
`ifdef TRACE_ENABLED
1232 
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
1233 
`endif
1234 
 
1235 
/**********************************************************************************
1236 
*                                                                                 *
1237 
*   End: Connecting CRC module                                                    *
1238 
*                                                                                 *
1239 
**********************************************************************************/
1240 
 
1241 
/**********************************************************************************
1242 
*                                                                                 *
1243 
*   Connecting trace module                                                       *
1244 
*                                                                                 *
1245 
**********************************************************************************/
1246 
`ifdef TRACE_ENABLED
1247 11 mohor 
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
1248 9 mohor 
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
1249 18 mohor 
                      .Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
1250 8 mohor 
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
1251 5 mohor 
                      .WpTrigger(WpTrigger),
1252 2 mohor 
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
1253 
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
1254 
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
1255 5 mohor 
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
1256 
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
1257 
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
1258 
                      .RecordINSTR(RecordINSTR),
1259 2 mohor 
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
1260 
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
1261 
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
1262 
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
1263 9 mohor 
                      .ReadBuffer(ReadTraceBufferPulse),
1264 2 mohor 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1265 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1266 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
1267 
                     );
1268 
`endif
1269 
/**********************************************************************************
1270 
*                                                                                 *
1271 
*   End: Connecting trace module                                                  *
1272 
*                                                                                 *
1273 
**********************************************************************************/
1274 
 
1275 
 
1276 
 
1277 9 mohor 
endmodule

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