URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Blame information for rev 19

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/11/12 01:11:27  mohor
// Reset signals are not combined any more.
//
// Revision 1.9  2001/10/19 11:40:01  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8  2001/10/17 10:39:03  mohor
// bs_chain_o added.
//
// Revision 1.7  2001/10/16 10:09:56  mohor
// Signal names changed to lowercase.
//
//
// Revision 1.6  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:55:13  mohor
// Asynchronous set/reset not used in trace any more.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
// Initial release
//
//
 
`include "timescale.v"
`include "dbg_defines.v"
 
// Top module
module dbg_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
 
                // Boundary Scan signals
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
 
                // RISC signals
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
 
 
              );
 
parameter Tp = 1;
 
// JTAG pins
input         tms_pad_i;                  // JTAG test mode select pad
input         tck_pad_i;                  // JTAG test clock pad
input         trst_pad_i;                 // JTAG test reset pad
input         tdi_pad_i;                  // JTAG test data input pad
output        tdo_pad_o;                  // JTAG test data output pad
 
 
// Boundary Scan signals
output capture_dr_o;
output shift_dr_o;
output update_dr_o;
output extest_selected_o;
input  bs_chain_i;
output bs_chain_o;
 
// RISC signals
input         risc_clk_i;                 // Master clock (RISC clock)
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
input  [10:0] wp_i;                       // Watchpoint inputs
input         bp_i;                       // Breakpoint input
input  [3:0]  lsstatus_i;                 // Load/store status inputs
input  [1:0]  istatus_i;                  // Instruction status inputs
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
output                      risc_stall_o; // Stalls the RISC
output                      reset_o;      // Resets the RISC
 
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
 
reg    [31:0] wb_adr_o;
reg    [31:0] wb_dat_o;
reg           wb_we_o;
reg           wb_cyc_o;
 
// TAP states
reg TestLogicReset;
reg RunTestIdle;
reg SelectDRScan;
reg CaptureDR;
reg ShiftDR;
reg Exit1DR;
reg PauseDR;
reg Exit2DR;
reg UpdateDR;
 
reg SelectIRScan;
reg CaptureIR;
reg ShiftIR;
reg Exit1IR;
reg PauseIR;
reg Exit2IR;
reg UpdateIR;
 
 
// Defining which instruction is selected
reg EXTESTSelected;
reg SAMPLE_PRELOADSelected;
reg IDCODESelected;
reg CHAIN_SELECTSelected;
reg INTESTSelected;
reg CLAMPSelected;
reg CLAMPZSelected;
reg HIGHZSelected;
reg DEBUGSelected;
reg BYPASSSelected;
 
reg [31:0]  ADDR;
reg [31:0]  DataOut;
 
reg [`OPSELECTWIDTH-1:0] opselect_o;      // Operation selection (selecting what kind of data is set to the risc_data_i)
 
reg [`CHAIN_ID_LENGTH-1:0] Chain;         // Selected chain
reg [31:0]  RISC_DATAINLatch;             // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is
                                          // accessed for reading
reg [31:0]  RegisterReadLatch;            // Data when reading register is latched one TCK clock after the register is read.
reg         RegAccessTck;                 // Indicates access to the registers (read or write)
reg         RISCAccessTck;                // Indicates access to the RISC (read or write)
reg [7:0]   BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
reg         RW;                           // Read/Write bit
reg         CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
 
reg         RegAccess_q;                  // Delayed signals used for accessing the registers
reg         RegAccess_q2;                 // Delayed signals used for accessing the registers
reg         RISCAccess_q;                 // Delayed signals used for accessing the RISC
reg         RISCAccess_q2;                // Delayed signals used for accessing the RISC
 
reg         wb_AccessTck;                 // Indicates access to the WISHBONE
reg [31:0]  WBReadLatch;                  // Data latched during WISHBONE read
reg         WBErrorLatch;                 // Error latched during WISHBONE read
 
wire TCK = tck_pad_i;
wire TMS = tms_pad_i;
wire TDI = tdi_pad_i;
wire trst = ~trst_pad_i;                  // trst_pad_i is active low
 
wire [31:0]             RegDataIn;        // Data from registers (read data)
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
 
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
wire RiscReset_reg;                       // RISC is reset by setting the register bit
wire RiscStall_trace;                     // RISC is stalled by trace module
 
 
wire RegisterScanChain;                   // Register Scan chain selected
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
wire WishboneScanChain;                   // WISHBONE Scan chain selected
 
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
wire RiscStall_access;                    // Stalling RISC because of the read or write access
 
 
assign capture_dr_o       = CaptureDR;
assign shift_dr_o         = ShiftDR;
assign update_dr_o        = UpdateDR;
assign extest_selected_o  = EXTESTSelected;
wire   BS_CHAIN_I         = bs_chain_i;
assign bs_chain_o         = tdi_pad_i;
 
 
// This signals are used only when TRACE is used in the design
`ifdef TRACE_ENABLED
  wire [39:0] TraceChain;                 // Chain that comes from trace module
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with TCK)
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
 
  // Outputs from registers
  wire ContinMode;                        // Trace working in continous mode
  wire TraceEnable;                       // Trace enabled
 
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
  wire        BpTrigger;                  // Breakpoint starts trigger
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
  wire [1:0]  TriggerOper;                // Trigger operation
 
  wire        WpTriggerValid;             // Watchpoint trigger is valid
  wire        BpTriggerValid;             // Breakpoint trigger is valid
  wire        LSSTriggerValid;            // Load/store status trigger is valid
  wire        ITriggerValid;              // Instruction status trigger is valid
 
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
  wire        BpQualif;                   // Breakpoint starts qualifier
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
  wire [1:0]  QualifOper;                 // Qualifier operation
 
  wire        WpQualifValid;              // Watchpoint qualifier is valid
  wire        BpQualifValid;              // Breakpoint qualifier is valid
  wire        LSSQualifValid;             // Load/store status qualifier is valid
  wire        IQualifValid;               // Instruction status qualifier is valid
 
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
  wire        BpStop;                     // Breakpoint stops recording of the trace
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
  wire [1:0]  StopOper;                   // Stop operation
 
  wire WpStopValid;                       // Watchpoint stop is valid
  wire BpStopValid;                       // Breakpoint stop is valid
  wire LSSStopValid;                      // Load/store status stop is valid
  wire IStopValid;                        // Instruction status stop is valid
 
  wire RecordPC;                          // Recording program counter
  wire RecordLSEA;                        // Recording load/store effective address
  wire RecordLDATA;                       // Recording load data
  wire RecordSDATA;                       // Recording store data
  wire RecordReadSPR;                     // Recording read SPR
  wire RecordWriteSPR;                    // Recording write SPR
  wire RecordINSTR;                       // Recording instruction
 
  // End: Outputs from registers
 
  wire TraceTestScanChain;                // Trace Test Scan chain selected
  wire [47:0] Trace_Data;                 // Trace data
 
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
                                          // data is set to the risc_data_i)
 
`endif
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
    begin
      if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
        RunTestIdle<=#Tp 1;
      else
        RunTestIdle<=#Tp 0;
    end
end
 
// SelectDRScan state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
    begin
      if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
        SelectDRScan<=#Tp 1;
      else
        SelectDRScan<=#Tp 0;
    end
end
 
// CaptureDR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
    begin
      if(~TMS & SelectDRScan)
        CaptureDR<=#Tp 1;
      else
        CaptureDR<=#Tp 0;
    end
end
 
// ShiftDR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
    begin
      if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
        ShiftDR<=#Tp 1;
      else
        ShiftDR<=#Tp 0;
    end
end
 
// Exit1DR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
    begin
      if(TMS & (CaptureDR | ShiftDR))
        Exit1DR<=#Tp 1;
      else
        Exit1DR<=#Tp 0;
    end
end
 
// PauseDR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
    begin
      if(~TMS & (Exit1DR | PauseDR))
        PauseDR<=#Tp 1;
      else
        PauseDR<=#Tp 0;
    end
end
 
// Exit2DR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
    begin
      if(TMS & PauseDR)
        Exit2DR<=#Tp 1;
      else
        Exit2DR<=#Tp 0;
    end
end
 
// UpdateDR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
    begin
      if(TMS & (Exit1DR | Exit2DR))
        UpdateDR<=#Tp 1;
      else
        UpdateDR<=#Tp 0;
    end
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge TCK)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
 
// SelectIRScan state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
    begin
      if(TMS & SelectDRScan)
        SelectIRScan<=#Tp 1;
      else
        SelectIRScan<=#Tp 0;
    end
end
 
// CaptureIR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
    begin
      if(~TMS & SelectIRScan)
        CaptureIR<=#Tp 1;
      else
        CaptureIR<=#Tp 0;
    end
end
 
// ShiftIR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
    begin
      if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
        ShiftIR<=#Tp 1;
      else
        ShiftIR<=#Tp 0;
    end
end
 
// Exit1IR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
    begin
      if(TMS & (CaptureIR | ShiftIR))
        Exit1IR<=#Tp 1;
      else
        Exit1IR<=#Tp 0;
    end
end
 
// PauseIR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
    begin
      if(~TMS & (Exit1IR | PauseIR))
        PauseIR<=#Tp 1;
      else
        PauseIR<=#Tp 0;
    end
end
 
// Exit2IR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
    begin
      if(TMS & PauseIR)
        Exit2IR<=#Tp 1;
      else
        Exit2IR<=#Tp 0;
    end
end
 
// UpdateIR state
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
    begin
      if(TMS & (Exit1IR | Exit2IR))
        UpdateIR<=#Tp 1;
      else
        UpdateIR<=#Tp 0;
    end
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
    begin
      if(CaptureIR)
        begin
          JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
          JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
        end
      else
        begin
          if(ShiftIR)
            begin
              JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
            end
        end
    end
end
 
 
//TDO is changing on the falling edge of TCK
always @ (negedge TCK)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
wire [31:0] IDCodeValue = `IDCODE_VALUE;  // IDCODE value is 32-bit long.
 
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
reg TDOData;
 
 
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(ShiftDR)
    JTAG_DR_IN[BitCounter]<=#Tp TDI;
end
 
wire [72:0] RISC_Data;
wire [45:0] Register_Data;
wire [72:0] WISHBONE_Data;
wire wb_Access_wbClk;
 
assign RISC_Data      = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
assign Register_Data  = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
assign WISHBONE_Data  = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
 
 
`ifdef TRACE_ENABLED
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
`endif
 
//TDO is changing on the falling edge of TCK
always @ (negedge TCK or posedge trst)
begin
  if(trst)
    begin
      TDOData <= #Tp 0;
      `ifdef TRACE_ENABLED
      ReadBuffer_Tck<=#Tp 0;
      `endif
    end
  else
  if(UpdateDR)
    begin
      TDOData <= #Tp CrcMatch;
      `ifdef TRACE_ENABLED
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
      `endif
    end
  else
    begin
      if(ShiftDR)
        begin
          if(IDCODESelected)
            TDOData <= #Tp IDCodeValue[BitCounter];           // IDCODE is shifted out
          else
          if(CHAIN_SELECTSelected)
            TDOData <= #Tp 0;
          else
          if(DEBUGSelected)
            begin
              if(RiscDebugScanChain)
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
              else
              if(RegisterScanChain)
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
              else
              if(WishboneScanChain)
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
              `ifdef TRACE_ENABLED
              else
              if(TraceTestScanChain)
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
              `endif
            end
        end
      else
        begin
          TDOData <= #Tp 0;
          `ifdef TRACE_ENABLED
          ReadBuffer_Tck<=#Tp 0;
          `endif
        end
    end
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   CHAIN_SELECT logic                                                            *
*                                                                                 *
**********************************************************************************/
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
  else
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Register read/write logic                                                     *
*   RISC registers read/write logic                                               *
*                                                                                 *
**********************************************************************************/
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    begin
      ADDR[31:0]        <=#Tp 32'h0;
      DataOut[31:0]     <=#Tp 32'h0;
      RW                <=#Tp 1'b0;
      RegAccessTck      <=#Tp 1'b0;
      RISCAccessTck     <=#Tp 1'b0;
      wb_adr_o          <=#Tp 32'h0;
      wb_we_o           <=#Tp 1'h0;
      wb_dat_o          <=#Tp 32'h0;
      wb_AccessTck      <=#Tp 1'h0;
    end
  else
  if(UpdateDR & DEBUGSelected & CrcMatch)
    begin
      if(RegisterScanChain)
        begin
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
          RegAccessTck      <=#Tp 1'b1;
        end
      else
      if(RiscDebugScanChain)
        begin
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
          RISCAccessTck     <=#Tp 1'b1;
        end
      else
      if(WishboneScanChain)
        begin
          wb_adr_o          <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
          wb_we_o           <=#Tp JTAG_DR_IN[32];     // latch R/W bit
          wb_dat_o          <=#Tp JTAG_DR_IN[64:33];  // latch data for write
          wb_AccessTck      <=#Tp 1'b1;               // 
        end
    end
  else
    begin
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one TCK clock period only
      RISCAccessTck     <=#Tp 1'b0;
      wb_AccessTck      <=#Tp 1'b0;
    end
end
 
assign wb_sel_o[3:0] = 4'hf;
assign wb_cab_o = 1'b0;
 
 
// Synchronizing the RegAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
                         .set2(RegAccessTck), .sync_out(RegAccess)
                        );
 
// Synchronizing the RISCAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
                        );
 
 
// Synchronizing the wb_Access signal to wishbone clock
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),      .clk2(TCK),          .reset1(wb_rst_i),  .reset2(trst),
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
                        );
 
 
 
 
 
// Delayed signals used for accessing registers and RISC
always @ (posedge risc_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      RegAccess_q   <=#Tp 1'b0;
      RegAccess_q2  <=#Tp 1'b0;
      RISCAccess_q  <=#Tp 1'b0;
      RISCAccess_q2 <=#Tp 1'b0;
    end
  else
    begin
      RegAccess_q   <=#Tp RegAccess;
      RegAccess_q2  <=#Tp RegAccess_q;
      RISCAccess_q  <=#Tp RISCAccess;
      RISCAccess_q2 <=#Tp RISCAccess_q;
    end
end
 
 
// Latching data read from registers
always @ (posedge risc_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    RegisterReadLatch[31:0]<=#Tp 0;
  else
  if(RegAccess_q & ~RegAccess_q2)
    RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
end
 
 
// Chip select and read/write signals for accessing RISC
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
 
 
reg wb_Access_wbClk_q;
// Delayed signals used for accessing WISHBONE
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    wb_Access_wbClk_q <=#Tp 1'b0;
  else
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    wb_cyc_o <=#Tp 1'b0;
  else
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
    wb_cyc_o <=#Tp 1'b1;
  else
  if(wb_ack_i | wb_err_i)
    wb_cyc_o <=#Tp 1'b0;
end
 
assign wb_stb_o = wb_cyc_o;
 
 
// Latching data read from registers
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    WBReadLatch[31:0]<=#Tp 32'h0;
  else
  if(wb_ack_i)
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
end
 
// Latching WISHBONE error cycle
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    WBErrorLatch<=#Tp 1'b0;
  else
  if(wb_err_i)
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
  if(wb_ack_i)
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
end
 
 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
`ifdef TRACE_ENABLED
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
`else
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
`endif
 
assign  reset_o = RiscReset_reg;
 
 
`ifdef TRACE_ENABLED
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
`else
always @ (RiscStall_write_access or RiscStall_read_access)
`endif
begin
  if(RiscStall_write_access)
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
  else
  if(RiscStall_read_access)
    opselect_o = `DEBUG_READ_SPR;   // Read spr
  else
`ifdef TRACE_ENABLED
    opselect_o = opselect_trace;
`else
    opselect_o = 3'h0;
`endif
end
 
 
 
// Latching data read from RISC
always @ (posedge risc_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    RISC_DATAINLatch[31:0]<=#Tp 0;
  else
  if(RISCAccess_q & ~RISCAccess_q2)
    RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
end
 
assign risc_addr_o = ADDR;
assign risc_data_o = DataOut;
 
 
 
/**********************************************************************************
*                                                                                 *
*   Read Trace buffer logic                                                       *
*                                                                                 *
**********************************************************************************/
`ifdef TRACE_ENABLED
 
 
// Synchronizing the trace read buffer signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
                        );
 
 
 
  always @(posedge risc_clk_i or posedge wb_rst_i)
  begin
    if(wb_rst_i)
      ReadTraceBuffer_q <=#Tp 0;
    else
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
  end
 
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
 
`endif
 
/**********************************************************************************
*                                                                                 *
*   End: Read Trace buffer logic                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg BypassRegister;
reg TDOBypassed;
 
always @ (posedge TCK)
begin
  if(ShiftDR)
    BypassRegister<=#Tp TDI;
end
 
always @ (negedge TCK)
begin
    TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO and Tristate control                                         *
*                                                                                 *
**********************************************************************************/
wire TDOShifted;
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
/**********************************************************************************
*                                                                                 *
*   End:  Multiplexing TDO and Tristate control                                   *
*                                                                                 *
**********************************************************************************/
 
 
 
// This multiplexer can be expanded with number of user registers
reg TDOMuxed;
always @ (JTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
begin
  case(JTAG_IR)
    `IDCODE: // Reading ID code
      begin
        TDOMuxed<=#Tp TDOShifted;
      end
    `CHAIN_SELECT: // Selecting the chain
      begin
        TDOMuxed<=#Tp TDOShifted;
      end
    `DEBUG: // Debug
      begin
        TDOMuxed<=#Tp TDOShifted;
      end
    `SAMPLE_PRELOAD:  // Sampling/Preloading
      begin
        TDOMuxed<=#Tp BS_CHAIN_I;
      end
    `EXTEST:  // External test
      begin
        TDOMuxed<=#Tp BS_CHAIN_I;
      end
    default:  // BYPASS instruction
      begin
        TDOMuxed<=#Tp TDOBypassed;
      end
  endcase
end
 
// Tristate control for tdo_pad_o pin
assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
/**********************************************************************************
*                                                                                 *
*   Bit counter                                                                   *
*                                                                                 *
**********************************************************************************/
 
 
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    BitCounter[7:0]<=#Tp 0;
  else
  if(ShiftDR)
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
  else
  if(UpdateDR)
    BitCounter[7:0]<=#Tp 0;
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: Bit counter                                                              *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   Connecting Registers                                                          *
*                                                                                 *
**********************************************************************************/
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
                      .Bp(bp_i), .Reset(wb_rst_i),
                      `ifdef TRACE_ENABLED
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
                      .WpTriggerValid(WpTriggerValid),
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
                      .IQualifValid(IQualifValid),
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
                      `endif
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
 
                     );
 
/**********************************************************************************
*                                                                                 *
*   End: Connecting Registers                                                     *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Connecting CRC module                                                         *
*                                                                                 *
**********************************************************************************/
wire AsyncResetCrc = trst;
wire SyncResetCrc = UpdateDR_q;
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
 
wire EnableCrcIn = ShiftDR &
                  ( (CHAIN_SELECTSelected                 & (BitCounter<4))  |
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
                  );
 
wire EnableCrcOut= ShiftDR &
                   (
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
                    `ifdef TRACE_ENABLED
                                                                             |
                    ((DEBUGSelected & TraceTestScanChain) & (BitCounter<40))
                    `endif
                   );
 
// Calculating crc for input data
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
                  .CrcOut(CalculatedCrcIn), .Clk(TCK));
 
// Calculating crc for output data
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
                  .CrcOut(CalculatedCrcOut), .Clk(TCK));
 
 
// Generating CrcMatch signal
always @ (posedge TCK or posedge trst)
begin
  if(trst)
    CrcMatch <=#Tp 1'b0;
  else
  if(Exit1DR)
    begin
      if(CHAIN_SELECTSelected)
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
      else
      if(RegisterScanChain & ~CHAIN_SELECTSelected)
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
      else
      if(RiscDebugScanChain & ~CHAIN_SELECTSelected)
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
      else
      if(WishboneScanChain & ~CHAIN_SELECTSelected)
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
    end
end
 
 
// Active chain
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
 
`ifdef TRACE_ENABLED
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
`endif
 
/**********************************************************************************
*                                                                                 *
*   End: Connecting CRC module                                                    *
*                                                                                 *
**********************************************************************************/
 
/**********************************************************************************
*                                                                                 *
*   Connecting trace module                                                       *
*                                                                                 *
**********************************************************************************/
`ifdef TRACE_ENABLED
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
                      .Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
                      .WpTrigger(WpTrigger),
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
                      .RecordINSTR(RecordINSTR),
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
                      .ReadBuffer(ReadTraceBufferPulse),
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
                     );
`endif
/**********************************************************************************
*                                                                                 *
*   End: Connecting trace module                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	19	mohor	`// Revision 1.10 2001/11/12 01:11:27 mohor`
49			`// Reset signals are not combined any more.`
50			`//`
51	18	mohor	`// Revision 1.9 2001/10/19 11:40:01 mohor`
52			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
53			`// few different cores in a single project.`
54			`//`
55	17	mohor	`// Revision 1.8 2001/10/17 10:39:03 mohor`
56			`// bs_chain_o added.`
57			`//`
58	15	mohor	`// Revision 1.7 2001/10/16 10:09:56 mohor`
59			`// Signal names changed to lowercase.`
60	13	mohor	`//`
61	15	mohor	`//`
62	13	mohor	`// Revision 1.6 2001/10/15 09:55:47 mohor`
63			`// Wishbone interface added, few fixes for better performance,`
64			`// hooks for boundary scan testing added.`
65			`//`
66	12	mohor	`// Revision 1.5 2001/09/24 14:06:42 mohor`
67			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
68			`//`
69	11	mohor	`// Revision 1.4 2001/09/20 10:11:25 mohor`
70			`// Working version. Few bugs fixed, comments added.`
71			`//`
72	9	mohor	`// Revision 1.3 2001/09/19 11:55:13 mohor`
73			`// Asynchronous set/reset not used in trace any more.`
74			`//`
75	8	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
76			`// Trace fixed. Some registers changed, trace simplified.`
77			`//`
78	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
79			`// Initial official release.`
80			`//`
81	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
82			`// This is a backup. It is not a fully working version. Not for use, yet.`
83			`//`
84			`// Revision 1.2 2001/05/18 13:10:00 mohor`
85			`// Headers changed. All additional information is now avaliable in the README.txt file.`
86			`//`
87			`// Revision 1.1.1.1 2001/05/18 06:35:02 mohor`
88			`// Initial release`
89			`//`
90			`//`
91
92	17	mohor	`include "timescale.v"
93	2	mohor	`include "dbg_defines.v"
94
95			`// Top module`
96	9	mohor	`module dbg_top(`
97			`// JTAG pins`
98			`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,`
99	12	mohor
100			`// Boundary Scan signals`
101	15	mohor	`capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,`
102	9	mohor
103			`// RISC signals`
104	11	mohor	`risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,`
105			`bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,`
106	9	mohor
107	12	mohor	`// WISHBONE common signals`
108			`wb_rst_i, wb_clk_i,`
109
110			`// WISHBONE master interface`
111			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
112			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i`
113
114
115	2	mohor	`);`
116
117			`parameter Tp = 1;`
118
119	9	mohor	`// JTAG pins`
120			`input tms_pad_i; // JTAG test mode select pad`
121			`input tck_pad_i; // JTAG test clock pad`
122			`input trst_pad_i; // JTAG test reset pad`
123			`input tdi_pad_i; // JTAG test data input pad`
124			`output tdo_pad_o; // JTAG test data output pad`
125	2	mohor
126
127	12	mohor	`// Boundary Scan signals`
128	13	mohor	`output capture_dr_o;`
129			`output shift_dr_o;`
130			`output update_dr_o;`
131			`output extest_selected_o;`
132			`input bs_chain_i;`
133	15	mohor	`output bs_chain_o;`
134	12	mohor
135	9	mohor	`// RISC signals`
136	11	mohor	`input risc_clk_i; // Master clock (RISC clock)`
137	9	mohor	`input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)`
138			`input [10:0] wp_i; // Watchpoint inputs`
139			`input bp_i; // Breakpoint input`
140			`input [3:0] lsstatus_i; // Load/store status inputs`
141			`input [1:0] istatus_i; // Instruction status inputs`
142			`output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)`
143			`output [31:0] risc_data_o; // RISC data output (data read from risc registers)`
144			output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
145			`output risc_stall_o; // Stalls the RISC`
146	11	mohor	`output reset_o; // Resets the RISC`
147	2	mohor
148
149	12	mohor	`// WISHBONE common signals`
150	9	mohor	`input wb_rst_i; // WISHBONE reset`
151	12	mohor	`input wb_clk_i; // WISHBONE clock`
152	9	mohor
153	12	mohor	`// WISHBONE master interface`
154			`output [31:0] wb_adr_o;`
155			`output [31:0] wb_dat_o;`
156			`input [31:0] wb_dat_i;`
157			`output wb_cyc_o;`
158			`output wb_stb_o;`
159			`output [3:0] wb_sel_o;`
160			`output wb_we_o;`
161			`input wb_ack_i;`
162			`output wb_cab_o;`
163			`input wb_err_i;`
164	9	mohor
165	12	mohor	`reg [31:0] wb_adr_o;`
166			`reg [31:0] wb_dat_o;`
167			`reg wb_we_o;`
168			`reg wb_cyc_o;`
169
170	9	mohor	`// TAP states`
171	2	mohor	`reg TestLogicReset;`
172			`reg RunTestIdle;`
173			`reg SelectDRScan;`
174			`reg CaptureDR;`
175			`reg ShiftDR;`
176			`reg Exit1DR;`
177			`reg PauseDR;`
178			`reg Exit2DR;`
179			`reg UpdateDR;`
180
181			`reg SelectIRScan;`
182			`reg CaptureIR;`
183			`reg ShiftIR;`
184			`reg Exit1IR;`
185			`reg PauseIR;`
186			`reg Exit2IR;`
187			`reg UpdateIR;`
188
189	9	mohor
190			`// Defining which instruction is selected`
191	2	mohor	`reg EXTESTSelected;`
192			`reg SAMPLE_PRELOADSelected;`
193			`reg IDCODESelected;`
194			`reg CHAIN_SELECTSelected;`
195			`reg INTESTSelected;`
196			`reg CLAMPSelected;`
197			`reg CLAMPZSelected;`
198			`reg HIGHZSelected;`
199			`reg DEBUGSelected;`
200			`reg BYPASSSelected;`
201
202	9	mohor	`reg [31:0] ADDR;`
203			`reg [31:0] DataOut;`
204
205	11	mohor	reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
206
207	2	mohor	reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
208	11	mohor	`reg [31:0] RISC_DATAINLatch; // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is`
209	2	mohor	`// accessed for reading`
210	9	mohor	`reg [31:0] RegisterReadLatch; // Data when reading register is latched one TCK clock after the register is read.`
211			`reg RegAccessTck; // Indicates access to the registers (read or write)`
212			`reg RISCAccessTck; // Indicates access to the RISC (read or write)`
213			`reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages`
214			`reg RW; // Read/Write bit`
215			`reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal`
216	2	mohor
217	9	mohor	`reg RegAccess_q; // Delayed signals used for accessing the registers`
218			`reg RegAccess_q2; // Delayed signals used for accessing the registers`
219			`reg RISCAccess_q; // Delayed signals used for accessing the RISC`
220			`reg RISCAccess_q2; // Delayed signals used for accessing the RISC`
221	2	mohor
222	12	mohor	`reg wb_AccessTck; // Indicates access to the WISHBONE`
223			`reg [31:0] WBReadLatch; // Data latched during WISHBONE read`
224			`reg WBErrorLatch; // Error latched during WISHBONE read`
225	2	mohor
226	9	mohor	`wire TCK = tck_pad_i;`
227			`wire TMS = tms_pad_i;`
228			`wire TDI = tdi_pad_i;`
229	18	mohor	`wire trst = ~trst_pad_i; // trst_pad_i is active low`
230	2	mohor
231	9	mohor	`wire [31:0] RegDataIn; // Data from registers (read data)`
232			wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
233	2	mohor
234	9	mohor	`wire RiscStall_reg; // RISC is stalled by setting the register bit`
235			`wire RiscReset_reg; // RISC is reset by setting the register bit`
236			`wire RiscStall_trace; // RISC is stalled by trace module`
237
238
239			`wire RegisterScanChain; // Register Scan chain selected`
240			`wire RiscDebugScanChain; // Risc Debug Scan chain selected`
241	12	mohor	`wire WishboneScanChain; // WISHBONE Scan chain selected`
242	11	mohor
243			`wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)`
244			`wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)`
245			`wire RiscStall_access; // Stalling RISC because of the read or write access`
246
247	9	mohor
248	13	mohor	`assign capture_dr_o = CaptureDR;`
249			`assign shift_dr_o = ShiftDR;`
250			`assign update_dr_o = UpdateDR;`
251			`assign extest_selected_o = EXTESTSelected;`
252			`wire BS_CHAIN_I = bs_chain_i;`
253	15	mohor	`assign bs_chain_o = tdi_pad_i;`
254
255
256	9	mohor	`// This signals are used only when TRACE is used in the design`
257	2	mohor	`ifdef TRACE_ENABLED
258	9	mohor	`wire [39:0] TraceChain; // Chain that comes from trace module`
259			`reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with TCK)`
260			`wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)`
261			`reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)`
262			`wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)`
263	2	mohor
264			`// Outputs from registers`
265	9	mohor	`wire ContinMode; // Trace working in continous mode`
266			`wire TraceEnable; // Trace enabled`
267	2	mohor
268	9	mohor	`wire [10:0] WpTrigger; // Watchpoint starts trigger`
269			`wire BpTrigger; // Breakpoint starts trigger`
270			`wire [3:0] LSSTrigger; // Load/store status starts trigger`
271			`wire [1:0] ITrigger; // Instruction status starts trigger`
272			`wire [1:0] TriggerOper; // Trigger operation`
273	2	mohor
274	9	mohor	`wire WpTriggerValid; // Watchpoint trigger is valid`
275			`wire BpTriggerValid; // Breakpoint trigger is valid`
276			`wire LSSTriggerValid; // Load/store status trigger is valid`
277			`wire ITriggerValid; // Instruction status trigger is valid`
278	2	mohor
279	9	mohor	`wire [10:0] WpQualif; // Watchpoint starts qualifier`
280			`wire BpQualif; // Breakpoint starts qualifier`
281			`wire [3:0] LSSQualif; // Load/store status starts qualifier`
282			`wire [1:0] IQualif; // Instruction status starts qualifier`
283			`wire [1:0] QualifOper; // Qualifier operation`
284	2	mohor
285	9	mohor	`wire WpQualifValid; // Watchpoint qualifier is valid`
286			`wire BpQualifValid; // Breakpoint qualifier is valid`
287			`wire LSSQualifValid; // Load/store status qualifier is valid`
288			`wire IQualifValid; // Instruction status qualifier is valid`
289	2	mohor
290	9	mohor	`wire [10:0] WpStop; // Watchpoint stops recording of the trace`
291			`wire BpStop; // Breakpoint stops recording of the trace`
292			`wire [3:0] LSSStop; // Load/store status stops recording of the trace`
293			`wire [1:0] IStop; // Instruction status stops recording of the trace`
294			`wire [1:0] StopOper; // Stop operation`
295	2	mohor
296	9	mohor	`wire WpStopValid; // Watchpoint stop is valid`
297			`wire BpStopValid; // Breakpoint stop is valid`
298			`wire LSSStopValid; // Load/store status stop is valid`
299			`wire IStopValid; // Instruction status stop is valid`
300	2	mohor
301	9	mohor	`wire RecordPC; // Recording program counter`
302			`wire RecordLSEA; // Recording load/store effective address`
303			`wire RecordLDATA; // Recording load data`
304			`wire RecordSDATA; // Recording store data`
305			`wire RecordReadSPR; // Recording read SPR`
306			`wire RecordWriteSPR; // Recording write SPR`
307			`wire RecordINSTR; // Recording instruction`
308	2	mohor
309			`// End: Outputs from registers`
310
311	9	mohor	`wire TraceTestScanChain; // Trace Test Scan chain selected`
312			`wire [47:0] Trace_Data; // Trace data`
313	2	mohor
314	11	mohor	wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
315			`// data is set to the risc_data_i)`
316
317	2	mohor	`endif
318
319
320			`/**********************************************************************************`
321			`* *`
322			`* TAP State Machine: Fully JTAG compliant *`
323			`* *`
324			`**********************************************************************************/`
325
326			`// TestLogicReset state`
327	18	mohor	`always @ (posedge TCK or posedge trst)`
328	2	mohor	`begin`
329	18	mohor	`if(trst)`
330	2	mohor	`TestLogicReset<=#Tp 1;`
331			`else`
332			`begin`
333			`if(TMS & (TestLogicReset \| SelectIRScan))`
334			`TestLogicReset<=#Tp 1;`
335			`else`
336			`TestLogicReset<=#Tp 0;`
337			`end`
338			`end`
339
340			`// RunTestIdle state`
341	18	mohor	`always @ (posedge TCK or posedge trst)`
342	2	mohor	`begin`
343	18	mohor	`if(trst)`
344	2	mohor	`RunTestIdle<=#Tp 0;`
345			`else`
346			`begin`
347			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
348			`RunTestIdle<=#Tp 1;`
349			`else`
350			`RunTestIdle<=#Tp 0;`
351			`end`
352			`end`
353
354			`// SelectDRScan state`
355	18	mohor	`always @ (posedge TCK or posedge trst)`
356	2	mohor	`begin`
357	18	mohor	`if(trst)`
358	2	mohor	`SelectDRScan<=#Tp 0;`
359			`else`
360			`begin`
361			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
362			`SelectDRScan<=#Tp 1;`
363			`else`
364			`SelectDRScan<=#Tp 0;`
365			`end`
366			`end`
367
368			`// CaptureDR state`
369	18	mohor	`always @ (posedge TCK or posedge trst)`
370	2	mohor	`begin`
371	18	mohor	`if(trst)`
372	2	mohor	`CaptureDR<=#Tp 0;`
373			`else`
374			`begin`
375			`if(~TMS & SelectDRScan)`
376			`CaptureDR<=#Tp 1;`
377			`else`
378			`CaptureDR<=#Tp 0;`
379			`end`
380			`end`
381
382			`// ShiftDR state`
383	18	mohor	`always @ (posedge TCK or posedge trst)`
384	2	mohor	`begin`
385	18	mohor	`if(trst)`
386	2	mohor	`ShiftDR<=#Tp 0;`
387			`else`
388			`begin`
389			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
390			`ShiftDR<=#Tp 1;`
391			`else`
392			`ShiftDR<=#Tp 0;`
393			`end`
394			`end`
395
396			`// Exit1DR state`
397	18	mohor	`always @ (posedge TCK or posedge trst)`
398	2	mohor	`begin`
399	18	mohor	`if(trst)`
400	2	mohor	`Exit1DR<=#Tp 0;`
401			`else`
402			`begin`
403			`if(TMS & (CaptureDR \| ShiftDR))`
404			`Exit1DR<=#Tp 1;`
405			`else`
406			`Exit1DR<=#Tp 0;`
407			`end`
408			`end`
409
410			`// PauseDR state`
411	18	mohor	`always @ (posedge TCK or posedge trst)`
412	2	mohor	`begin`
413	18	mohor	`if(trst)`
414	2	mohor	`PauseDR<=#Tp 0;`
415			`else`
416			`begin`
417			`if(~TMS & (Exit1DR \| PauseDR))`
418			`PauseDR<=#Tp 1;`
419			`else`
420			`PauseDR<=#Tp 0;`
421			`end`
422			`end`
423
424			`// Exit2DR state`
425	18	mohor	`always @ (posedge TCK or posedge trst)`
426	2	mohor	`begin`
427	18	mohor	`if(trst)`
428	2	mohor	`Exit2DR<=#Tp 0;`
429			`else`
430			`begin`
431			`if(TMS & PauseDR)`
432			`Exit2DR<=#Tp 1;`
433			`else`
434			`Exit2DR<=#Tp 0;`
435			`end`
436			`end`
437
438			`// UpdateDR state`
439	18	mohor	`always @ (posedge TCK or posedge trst)`
440	2	mohor	`begin`
441	18	mohor	`if(trst)`
442	2	mohor	`UpdateDR<=#Tp 0;`
443			`else`
444			`begin`
445			`if(TMS & (Exit1DR \| Exit2DR))`
446			`UpdateDR<=#Tp 1;`
447			`else`
448			`UpdateDR<=#Tp 0;`
449			`end`
450			`end`
451
452	9	mohor	`// Delayed UpdateDR state`
453	2	mohor	`reg UpdateDR_q;`
454			`always @ (posedge TCK)`
455			`begin`
456			`UpdateDR_q<=#Tp UpdateDR;`
457			`end`
458
459
460			`// SelectIRScan state`
461	18	mohor	`always @ (posedge TCK or posedge trst)`
462	2	mohor	`begin`
463	18	mohor	`if(trst)`
464	2	mohor	`SelectIRScan<=#Tp 0;`
465			`else`
466			`begin`
467			`if(TMS & SelectDRScan)`
468			`SelectIRScan<=#Tp 1;`
469			`else`
470			`SelectIRScan<=#Tp 0;`
471			`end`
472			`end`
473
474			`// CaptureIR state`
475	18	mohor	`always @ (posedge TCK or posedge trst)`
476	2	mohor	`begin`
477	18	mohor	`if(trst)`
478	2	mohor	`CaptureIR<=#Tp 0;`
479			`else`
480			`begin`
481			`if(~TMS & SelectIRScan)`
482			`CaptureIR<=#Tp 1;`
483			`else`
484			`CaptureIR<=#Tp 0;`
485			`end`
486			`end`
487
488			`// ShiftIR state`
489	18	mohor	`always @ (posedge TCK or posedge trst)`
490	2	mohor	`begin`
491	18	mohor	`if(trst)`
492	2	mohor	`ShiftIR<=#Tp 0;`
493			`else`
494			`begin`
495			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
496			`ShiftIR<=#Tp 1;`
497			`else`
498			`ShiftIR<=#Tp 0;`
499			`end`
500			`end`

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Blame information for rev 19