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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  dbg_top.v                                                   ////

////                                                              ////

////                                                              ////

////  This file is part of the SoC/OpenRISC Development Interface ////

////  http://www.opencores.org/cores/DebugInterface/              ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////       Igor Mohor                                             ////

////       igorm@opencores.org                                    ////

////                                                              ////

////                                                              ////

////  All additional information is avaliable in the README.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000,2001 Authors                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.12  2001/11/26 10:47:09  mohor

// Crc generation is different for read or write commands. Small synthesys fixes.

//

// Revision 1.11  2001/11/14 10:10:41  mohor

// Wishbone data latched on wb_clk_i instead of risc_clk.

//

// Revision 1.10  2001/11/12 01:11:27  mohor

// Reset signals are not combined any more.

//

// Revision 1.9  2001/10/19 11:40:01  mohor

// dbg_timescale.v changed to timescale.v This is done for the simulation of

// few different cores in a single project.

//

// Revision 1.8  2001/10/17 10:39:03  mohor

// bs_chain_o added.

//

// Revision 1.7  2001/10/16 10:09:56  mohor

// Signal names changed to lowercase.

//

//

// Revision 1.6  2001/10/15 09:55:47  mohor

// Wishbone interface added, few fixes for better performance,

// hooks for boundary scan testing added.

//

// Revision 1.5  2001/09/24 14:06:42  mohor

// Changes connected to the OpenRISC access (SPR read, SPR write).

//

// Revision 1.4  2001/09/20 10:11:25  mohor

// Working version. Few bugs fixed, comments added.

//

// Revision 1.3  2001/09/19 11:55:13  mohor

// Asynchronous set/reset not used in trace any more.

//

// Revision 1.2  2001/09/18 14:13:47  mohor

// Trace fixed. Some registers changed, trace simplified.

//

// Revision 1.1.1.1  2001/09/13 13:49:19  mohor

// Initial official release.

//

// Revision 1.3  2001/06/01 22:22:35  mohor

// This is a backup. It is not a fully working version. Not for use, yet.

//

// Revision 1.2  2001/05/18 13:10:00  mohor

// Headers changed. All additional information is now avaliable in the README.txt file.

//

// Revision 1.1.1.1  2001/05/18 06:35:02  mohor

// Initial release

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "dbg_defines.v"

// Top module

module dbg_top(

                // JTAG pins

                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,

                // Boundary Scan signals

                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,

                // RISC signals

                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,

                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,

                // WISHBONE common signals

                wb_rst_i, wb_clk_i,

                // WISHBONE master interface

                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,

                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i

              );

parameter Tp = 1;

// JTAG pins

input         tms_pad_i;                  // JTAG test mode select pad

input         tck_pad_i;                  // JTAG test clock pad

input         trst_pad_i;                 // JTAG test reset pad

input         tdi_pad_i;                  // JTAG test data input pad

output        tdo_pad_o;                  // JTAG test data output pad

// Boundary Scan signals

output capture_dr_o;

output shift_dr_o;

output update_dr_o;

output extest_selected_o;

input  bs_chain_i;

output bs_chain_o;

// RISC signals

input         risc_clk_i;                 // Master clock (RISC clock)

input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)

input  [10:0] wp_i;                       // Watchpoint inputs

input         bp_i;                       // Breakpoint input

input  [3:0]  lsstatus_i;                 // Load/store status inputs

input  [1:0]  istatus_i;                  // Instruction status inputs

output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)

output [31:0] risc_data_o;                // RISC data output (data read from risc registers)

output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)

output                      risc_stall_o; // Stalls the RISC

output                      reset_o;      // Resets the RISC

// WISHBONE common signals

input         wb_rst_i;                   // WISHBONE reset

input         wb_clk_i;                   // WISHBONE clock

// WISHBONE master interface

output [31:0] wb_adr_o;

output [31:0] wb_dat_o;

input  [31:0] wb_dat_i;

output        wb_cyc_o;

output        wb_stb_o;

output  [3:0] wb_sel_o;

output        wb_we_o;

input         wb_ack_i;

output        wb_cab_o;

input         wb_err_i;

reg           wb_cyc_o;

// TAP states

reg TestLogicReset;

reg RunTestIdle;

reg SelectDRScan;

reg CaptureDR;

reg ShiftDR;

reg Exit1DR;

reg PauseDR;

reg Exit2DR;

reg UpdateDR;

reg SelectIRScan;

reg CaptureIR;

reg ShiftIR;

reg Exit1IR;

reg PauseIR;

reg Exit2IR;

reg UpdateIR;

// Defining which instruction is selected

reg EXTESTSelected;

reg SAMPLE_PRELOADSelected;

reg IDCODESelected;

reg CHAIN_SELECTSelected;

reg INTESTSelected;

reg CLAMPSelected;

reg CLAMPZSelected;

reg HIGHZSelected;

reg DEBUGSelected;

reg BYPASSSelected;

reg [31:0]  ADDR;

reg [31:0]  DataOut;

reg [`OPSELECTWIDTH-1:0] opselect_o;      // Operation selection (selecting what kind of data is set to the risc_data_i)

reg [`CHAIN_ID_LENGTH-1:0] Chain;         // Selected chain

reg [31:0]  RISC_DATAINLatch;             // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is

                                          // accessed for reading

reg [31:0]  RegisterReadLatch;            // Data when reading register is latched one TCK clock after the register is read.

reg         RegAccessTck;                 // Indicates access to the registers (read or write)

reg         RISCAccessTck;                // Indicates access to the RISC (read or write)

reg [7:0]   BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages

reg         RW;                           // Read/Write bit

reg         CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal

reg         RegAccess_q;                  // Delayed signals used for accessing the registers

reg         RegAccess_q2;                 // Delayed signals used for accessing the registers

reg         RISCAccess_q;                 // Delayed signals used for accessing the RISC

reg         RISCAccess_q2;                // Delayed signals used for accessing the RISC

reg         wb_AccessTck;                 // Indicates access to the WISHBONE

reg [31:0]  WBReadLatch;                  // Data latched during WISHBONE read

reg         WBErrorLatch;                 // Error latched during WISHBONE read

wire TCK = tck_pad_i;

wire TMS = tms_pad_i;

wire TDI = tdi_pad_i;

wire trst = ~trst_pad_i;                  // trst_pad_i is active low

wire [31:0]             RegDataIn;        // Data from registers (read data)

wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.

wire RiscStall_reg;                       // RISC is stalled by setting the register bit

wire RiscReset_reg;                       // RISC is reset by setting the register bit

wire RiscStall_trace;                     // RISC is stalled by trace module

wire RegisterScanChain;                   // Register Scan chain selected

wire RiscDebugScanChain;                  // Risc Debug Scan chain selected

wire WishboneScanChain;                   // WISHBONE Scan chain selected

wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)

wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)

wire RiscStall_access;                    // Stalling RISC because of the read or write access

assign capture_dr_o       = CaptureDR;

assign shift_dr_o         = ShiftDR;

assign update_dr_o        = UpdateDR;

assign extest_selected_o  = EXTESTSelected;

wire   BS_CHAIN_I         = bs_chain_i;

assign bs_chain_o         = tdi_pad_i;

// This signals are used only when TRACE is used in the design

`ifdef TRACE_ENABLED

  wire [39:0] TraceChain;                 // Chain that comes from trace module

  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with TCK)

  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)

  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)

  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)

  // Outputs from registers

  wire ContinMode;                        // Trace working in continous mode

  wire TraceEnable;                       // Trace enabled

  wire [10:0] WpTrigger;                  // Watchpoint starts trigger

  wire        BpTrigger;                  // Breakpoint starts trigger

  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger

  wire [1:0]  ITrigger;                   // Instruction status starts trigger

  wire [1:0]  TriggerOper;                // Trigger operation

  wire        WpTriggerValid;             // Watchpoint trigger is valid

  wire        BpTriggerValid;             // Breakpoint trigger is valid

  wire        LSSTriggerValid;            // Load/store status trigger is valid

  wire        ITriggerValid;              // Instruction status trigger is valid

  wire [10:0] WpQualif;                   // Watchpoint starts qualifier

  wire        BpQualif;                   // Breakpoint starts qualifier

  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier

  wire [1:0]  IQualif;                    // Instruction status starts qualifier

  wire [1:0]  QualifOper;                 // Qualifier operation

  wire        WpQualifValid;              // Watchpoint qualifier is valid

  wire        BpQualifValid;              // Breakpoint qualifier is valid

  wire        LSSQualifValid;             // Load/store status qualifier is valid

  wire        IQualifValid;               // Instruction status qualifier is valid

  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace

  wire        BpStop;                     // Breakpoint stops recording of the trace

  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace

  wire [1:0]  IStop;                      // Instruction status stops recording of the trace

  wire [1:0]  StopOper;                   // Stop operation

  wire WpStopValid;                       // Watchpoint stop is valid

  wire BpStopValid;                       // Breakpoint stop is valid

  wire LSSStopValid;                      // Load/store status stop is valid

  wire IStopValid;                        // Instruction status stop is valid

  wire RecordPC;                          // Recording program counter

  wire RecordLSEA;                        // Recording load/store effective address

  wire RecordLDATA;                       // Recording load data

  wire RecordSDATA;                       // Recording store data

  wire RecordReadSPR;                     // Recording read SPR

  wire RecordWriteSPR;                    // Recording write SPR

  wire RecordINSTR;                       // Recording instruction

  // End: Outputs from registers

  wire TraceTestScanChain;                // Trace Test Scan chain selected

  wire [47:0] Trace_Data;                 // Trace data

  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of

                                          // data is set to the risc_data_i)

`endif

/**********************************************************************************

*                                                                                 *

*   TAP State Machine: Fully JTAG compliant                                       *

*                                                                                 *

**********************************************************************************/

// TestLogicReset state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    TestLogicReset<=#Tp 1;

  else

    begin

      if(TMS & (TestLogicReset | SelectIRScan))

        TestLogicReset<=#Tp 1;

      else

        TestLogicReset<=#Tp 0;

    end

end

// RunTestIdle state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    RunTestIdle<=#Tp 0;

  else

    begin

      if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))

        RunTestIdle<=#Tp 1;

      else

        RunTestIdle<=#Tp 0;

    end

end

// SelectDRScan state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    SelectDRScan<=#Tp 0;

  else

    begin

      if(TMS & (RunTestIdle | UpdateDR | UpdateIR))

        SelectDRScan<=#Tp 1;

      else

        SelectDRScan<=#Tp 0;

    end

end

// CaptureDR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    CaptureDR<=#Tp 0;

  else

    begin

      if(~TMS & SelectDRScan)

        CaptureDR<=#Tp 1;

      else

        CaptureDR<=#Tp 0;

    end

end

// ShiftDR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    ShiftDR<=#Tp 0;

  else

    begin

      if(~TMS & (CaptureDR | ShiftDR | Exit2DR))

        ShiftDR<=#Tp 1;

      else

        ShiftDR<=#Tp 0;

    end

end

// Exit1DR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    Exit1DR<=#Tp 0;

  else

    begin

      if(TMS & (CaptureDR | ShiftDR))

        Exit1DR<=#Tp 1;

      else

        Exit1DR<=#Tp 0;

    end

end

// PauseDR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    PauseDR<=#Tp 0;

  else

    begin

      if(~TMS & (Exit1DR | PauseDR))

        PauseDR<=#Tp 1;

      else

        PauseDR<=#Tp 0;

    end

end

// Exit2DR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    Exit2DR<=#Tp 0;

  else

    begin

      if(TMS & PauseDR)

        Exit2DR<=#Tp 1;

      else

        Exit2DR<=#Tp 0;

    end

end

// UpdateDR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    UpdateDR<=#Tp 0;

  else

    begin

      if(TMS & (Exit1DR | Exit2DR))

        UpdateDR<=#Tp 1;

      else

        UpdateDR<=#Tp 0;

    end

end

// Delayed UpdateDR state

reg UpdateDR_q;

always @ (posedge TCK)

begin

  UpdateDR_q<=#Tp UpdateDR;

end

// SelectIRScan state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    SelectIRScan<=#Tp 0;

  else

    begin

      if(TMS & SelectDRScan)

        SelectIRScan<=#Tp 1;

      else

        SelectIRScan<=#Tp 0;

    end

end

// CaptureIR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    CaptureIR<=#Tp 0;

  else

    begin

      if(~TMS & SelectIRScan)

        CaptureIR<=#Tp 1;

      else

        CaptureIR<=#Tp 0;

    end

end

// ShiftIR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    ShiftIR<=#Tp 0;

  else

    begin

      if(~TMS & (CaptureIR | ShiftIR | Exit2IR))

        ShiftIR<=#Tp 1;

      else

        ShiftIR<=#Tp 0;

    end

end

// Exit1IR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    Exit1IR<=#Tp 0;

  else

    begin

      if(TMS & (CaptureIR | ShiftIR))

        Exit1IR<=#Tp 1;

      else

        Exit1IR<=#Tp 0;

    end

end

// PauseIR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    PauseIR<=#Tp 0;

  else

    begin

      if(~TMS & (Exit1IR | PauseIR))

        PauseIR<=#Tp 1;

      else

        PauseIR<=#Tp 0;

    end

end

// Exit2IR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    Exit2IR<=#Tp 0;

  else

    begin

      if(TMS & PauseIR)

        Exit2IR<=#Tp 1;

      else

        Exit2IR<=#Tp 0;

    end

end

// UpdateIR state

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    UpdateIR<=#Tp 0;

  else

    begin

      if(TMS & (Exit1IR | Exit2IR))

        UpdateIR<=#Tp 1;

      else

        UpdateIR<=#Tp 0;

    end

end

/**********************************************************************************

*                                                                                 *

*   End: TAP State Machine                                                        *

*                                                                                 *

**********************************************************************************/

/**********************************************************************************

*                                                                                 *

*   JTAG_IR:  JTAG Instruction Register                                           *

*                                                                                 *

**********************************************************************************/

wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.

reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register

reg [`IR_LENGTH-1:0]LatchedJTAG_IR;

reg TDOInstruction;

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;

  else

    begin

      if(CaptureIR)

        begin

          JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection

          JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip

        end

      else

        begin

          if(ShiftIR)

            begin

              JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};

            end

        end

    end

end

//TDO is changing on the falling edge of TCK

always @ (negedge TCK)

begin

  if(ShiftIR)

    TDOInstruction <= #Tp JTAG_IR[0];

end

/**********************************************************************************

*                                                                                 *

*   End: JTAG_IR                                                                  *

*                                                                                 *

**********************************************************************************/

/**********************************************************************************

*                                                                                 *

*   JTAG_DR:  JTAG Data Register                                                  *

*                                                                                 *

**********************************************************************************/

wire [31:0] IDCodeValue = `IDCODE_VALUE;  // IDCODE value is 32-bit long.

reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register

reg TDOData;

always @ (posedge TCK or posedge trst)

begin

  if(trst)

    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;

  else

  if(ShiftDR)

    JTAG_DR_IN[BitCounter]<=#Tp TDI;

end

wire [72:0] RISC_Data;

wire [45:0] Register_Data;

wire [72:0] WISHBONE_Data;

wire [12:0] chain_sel_data;

wire wb_Access_wbClk;

// assign RISC_Data      = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};

// assign Register_Data  = {CalculatedCrcOut, RegisterReadLatch, 6'h0};

// assign WISHBONE_Data  = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};

wire select_crc_out;

assign select_crc_out = RegisterScanChain     & JTAG_DR_IN[5]   |     // Calculated CRC is returned when read operation is

                        RiscDebugScanChain    & JTAG_DR_IN[32]  |     // performed, else received crc is returned (loopback).

                        WishboneScanChain     & JTAG_DR_IN[32]  |

                        CHAIN_SELECTSelected;                         // When chain is selected, received crc is returned

wire [8:0] send_crc;

assign send_crc = select_crc_out? {9{JTAG_DR_IN[BitCounter-1]}}   : // Calculated CRC is returned when read operation is

                                  {1'b0, CalculatedCrcOut}        ; // performed, else received crc is returned (loopback).

assign RISC_Data      = {send_crc, RISC_DATAINLatch, 33'h0};

assign Register_Data  = {send_crc, RegisterReadLatch, 6'h0};

assign WISHBONE_Data  = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};

assign chain_sel_data = {send_crc, 4'h0};

`ifdef TRACE_ENABLED

  assign Trace_Data     = {CalculatedCrcOut, TraceChain};

`endif

//TDO is changing on the falling edge of TCK

always @ (negedge TCK or posedge trst)

begin

  if(trst)

    begin

      TDOData <= #Tp 0;

      `ifdef TRACE_ENABLED

      ReadBuffer_Tck<=#Tp 0;

      `endif

    end

  else

  if(UpdateDR)

    begin