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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Blame information for rev 33

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1 2 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  dbg_top.v                                                   ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the SoC/OpenRISC Development Interface ////
7 
////  http://www.opencores.org/cores/DebugInterface/              ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is avaliable in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000,2001 Authors                              ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 33 mohor 
// Revision 1.19  2002/02/05 13:34:51  mohor
49 
// Stupid bug that was entered by previous update fixed.
50 
//
51 32 mohor 
// Revision 1.18  2002/02/05 12:41:01  mohor
52 
// trst synchronization is not needed and was removed.
53 
//
54 31 mohor 
// Revision 1.17  2002/01/25 07:58:35  mohor
55 
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
56 
// not filled-in. Tested in hw.
57 
//
58 30 mohor 
// Revision 1.16  2001/12/20 11:17:26  mohor
59 
// TDO and TDO Enable signal are separated into two signals.
60 
//
61 28 mohor 
// Revision 1.15  2001/12/05 13:28:21  mohor
62 
// trst signal is synchronized to wb_clk_i.
63 
//
64 25 mohor 
// Revision 1.14  2001/11/28 09:36:15  mohor
65 
// Register length fixed.
66 
//
67 22 mohor 
// Revision 1.13  2001/11/27 13:37:43  mohor
68 
// CRC is returned when chain selection data is transmitted.
69 
//
70 21 mohor 
// Revision 1.12  2001/11/26 10:47:09  mohor
71 
// Crc generation is different for read or write commands. Small synthesys fixes.
72 
//
73 20 mohor 
// Revision 1.11  2001/11/14 10:10:41  mohor
74 
// Wishbone data latched on wb_clk_i instead of risc_clk.
75 
//
76 19 mohor 
// Revision 1.10  2001/11/12 01:11:27  mohor
77 
// Reset signals are not combined any more.
78 
//
79 18 mohor 
// Revision 1.9  2001/10/19 11:40:01  mohor
80 
// dbg_timescale.v changed to timescale.v This is done for the simulation of
81 
// few different cores in a single project.
82 
//
83 17 mohor 
// Revision 1.8  2001/10/17 10:39:03  mohor
84 
// bs_chain_o added.
85 
//
86 15 mohor 
// Revision 1.7  2001/10/16 10:09:56  mohor
87 
// Signal names changed to lowercase.
88 13 mohor 
//
89 15 mohor 
//
90 13 mohor 
// Revision 1.6  2001/10/15 09:55:47  mohor
91 
// Wishbone interface added, few fixes for better performance,
92 
// hooks for boundary scan testing added.
93 
//
94 12 mohor 
// Revision 1.5  2001/09/24 14:06:42  mohor
95 
// Changes connected to the OpenRISC access (SPR read, SPR write).
96 
//
97 11 mohor 
// Revision 1.4  2001/09/20 10:11:25  mohor
98 
// Working version. Few bugs fixed, comments added.
99 
//
100 9 mohor 
// Revision 1.3  2001/09/19 11:55:13  mohor
101 
// Asynchronous set/reset not used in trace any more.
102 
//
103 8 mohor 
// Revision 1.2  2001/09/18 14:13:47  mohor
104 
// Trace fixed. Some registers changed, trace simplified.
105 
//
106 5 mohor 
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
107 
// Initial official release.
108 
//
109 2 mohor 
// Revision 1.3  2001/06/01 22:22:35  mohor
110 
// This is a backup. It is not a fully working version. Not for use, yet.
111 
//
112 
// Revision 1.2  2001/05/18 13:10:00  mohor
113 
// Headers changed. All additional information is now avaliable in the README.txt file.
114 
//
115 
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
116 
// Initial release
117 
//
118 
//
119 
 
120 20 mohor 
// synopsys translate_off
121 17 mohor 
`include "timescale.v"
122 20 mohor 
// synopsys translate_on
123 2 mohor 
`include "dbg_defines.v"
124 
 
125 
// Top module
126 9 mohor 
module dbg_top(
127 
                // JTAG pins
128 28 mohor 
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
129 12 mohor 
 
130 
                // Boundary Scan signals
131 15 mohor 
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
132 9 mohor 
 
133 
                // RISC signals
134 11 mohor 
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
135 
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
136 9 mohor 
 
137 12 mohor 
                // WISHBONE common signals
138 
                wb_rst_i, wb_clk_i,
139 
 
140 
                // WISHBONE master interface
141 
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
142 
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
143 
 
144 
 
145 2 mohor 
              );
146 
 
147 
parameter Tp = 1;
148 
 
149 9 mohor 
// JTAG pins
150 
input         tms_pad_i;                  // JTAG test mode select pad
151 
input         tck_pad_i;                  // JTAG test clock pad
152 
input         trst_pad_i;                 // JTAG test reset pad
153 
input         tdi_pad_i;                  // JTAG test data input pad
154 
output        tdo_pad_o;                  // JTAG test data output pad
155 28 mohor 
output        tdo_padoen_o;               // Output enable for JTAG test data output pad
156 2 mohor 
 
157 
 
158 12 mohor 
// Boundary Scan signals
159 13 mohor 
output capture_dr_o;
160 
output shift_dr_o;
161 
output update_dr_o;
162 
output extest_selected_o;
163 
input  bs_chain_i;
164 15 mohor 
output bs_chain_o;
165 12 mohor 
 
166 9 mohor 
// RISC signals
167 11 mohor 
input         risc_clk_i;                 // Master clock (RISC clock)
168 9 mohor 
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
169 
input  [10:0] wp_i;                       // Watchpoint inputs
170 
input         bp_i;                       // Breakpoint input
171 
input  [3:0]  lsstatus_i;                 // Load/store status inputs
172 
input  [1:0]  istatus_i;                  // Instruction status inputs
173 
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
174 
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
175 
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
176 
output                      risc_stall_o; // Stalls the RISC
177 11 mohor 
output                      reset_o;      // Resets the RISC
178 2 mohor 
 
179 
 
180 12 mohor 
// WISHBONE common signals
181 9 mohor 
input         wb_rst_i;                   // WISHBONE reset
182 12 mohor 
input         wb_clk_i;                   // WISHBONE clock
183 9 mohor 
 
184 12 mohor 
// WISHBONE master interface
185 
output [31:0] wb_adr_o;
186 
output [31:0] wb_dat_o;
187 
input  [31:0] wb_dat_i;
188 
output        wb_cyc_o;
189 
output        wb_stb_o;
190 
output  [3:0] wb_sel_o;
191 
output        wb_we_o;
192 
input         wb_ack_i;
193 
output        wb_cab_o;
194 
input         wb_err_i;
195 9 mohor 
 
196 12 mohor 
reg           wb_cyc_o;
197 
 
198 9 mohor 
// TAP states
199 2 mohor 
reg TestLogicReset;
200 
reg RunTestIdle;
201 
reg SelectDRScan;
202 
reg CaptureDR;
203 
reg ShiftDR;
204 
reg Exit1DR;
205 
reg PauseDR;
206 
reg Exit2DR;
207 
reg UpdateDR;
208 
 
209 
reg SelectIRScan;
210 
reg CaptureIR;
211 
reg ShiftIR;
212 
reg Exit1IR;
213 
reg PauseIR;
214 
reg Exit2IR;
215 
reg UpdateIR;
216 
 
217 9 mohor 
 
218 
// Defining which instruction is selected
219 2 mohor 
reg EXTESTSelected;
220 
reg SAMPLE_PRELOADSelected;
221 
reg IDCODESelected;
222 
reg CHAIN_SELECTSelected;
223 
reg INTESTSelected;
224 
reg CLAMPSelected;
225 
reg CLAMPZSelected;
226 
reg HIGHZSelected;
227 
reg DEBUGSelected;
228 
reg BYPASSSelected;
229 
 
230 9 mohor 
reg [31:0]  ADDR;
231 
reg [31:0]  DataOut;
232 
 
233 11 mohor 
reg [`OPSELECTWIDTH-1:0] opselect_o;      // Operation selection (selecting what kind of data is set to the risc_data_i)
234 
 
235 2 mohor 
reg [`CHAIN_ID_LENGTH-1:0] Chain;         // Selected chain
236 30 mohor 
reg [31:0]  DataReadLatch;                // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
237 9 mohor 
reg         RegAccessTck;                 // Indicates access to the registers (read or write)
238 
reg         RISCAccessTck;                // Indicates access to the RISC (read or write)
239 
reg [7:0]   BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
240 
reg         RW;                           // Read/Write bit
241 
reg         CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
242 2 mohor 
 
243 9 mohor 
reg         RegAccess_q;                  // Delayed signals used for accessing the registers
244 
reg         RegAccess_q2;                 // Delayed signals used for accessing the registers
245 
reg         RISCAccess_q;                 // Delayed signals used for accessing the RISC
246 
reg         RISCAccess_q2;                // Delayed signals used for accessing the RISC
247 2 mohor 
 
248 12 mohor 
reg         wb_AccessTck;                 // Indicates access to the WISHBONE
249 
reg [31:0]  WBReadLatch;                  // Data latched during WISHBONE read
250 
reg         WBErrorLatch;                 // Error latched during WISHBONE read
251 31 mohor 
wire        trst;                         // trst is active high while trst_pad_i is active low
252 2 mohor 
 
253 30 mohor 
reg         BypassRegister;               // Bypass register
254 
 
255 
 
256 9 mohor 
wire TCK = tck_pad_i;
257 
wire TMS = tms_pad_i;
258 
wire TDI = tdi_pad_i;
259 2 mohor 
 
260 9 mohor 
wire [31:0]             RegDataIn;        // Data from registers (read data)
261 
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
262 2 mohor 
 
263 9 mohor 
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
264 
wire RiscReset_reg;                       // RISC is reset by setting the register bit
265 
wire RiscStall_trace;                     // RISC is stalled by trace module
266 
 
267 
 
268 
wire RegisterScanChain;                   // Register Scan chain selected
269 
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
270 12 mohor 
wire WishboneScanChain;                   // WISHBONE Scan chain selected
271 11 mohor 
 
272 
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
273 
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
274 
wire RiscStall_access;                    // Stalling RISC because of the read or write access
275 
 
276 30 mohor 
wire BitCounter_Lt4;
277 
wire BitCounter_Eq5;
278 
wire BitCounter_Eq32;
279 
wire BitCounter_Lt38;
280 
wire BitCounter_Lt65;
281 
 
282 13 mohor 
assign capture_dr_o       = CaptureDR;
283 
assign shift_dr_o         = ShiftDR;
284 
assign update_dr_o        = UpdateDR;
285 
assign extest_selected_o  = EXTESTSelected;
286 
wire   BS_CHAIN_I         = bs_chain_i;
287 15 mohor 
assign bs_chain_o         = tdi_pad_i;
288 
 
289 
 
290 9 mohor 
// This signals are used only when TRACE is used in the design
291 2 mohor 
`ifdef TRACE_ENABLED
292 9 mohor 
  wire [39:0] TraceChain;                 // Chain that comes from trace module
293 
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with TCK)
294 
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
295 
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
296 
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
297 2 mohor 
 
298 
  // Outputs from registers
299 9 mohor 
  wire ContinMode;                        // Trace working in continous mode
300 
  wire TraceEnable;                       // Trace enabled
301 2 mohor 
 
302 9 mohor 
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
303 
  wire        BpTrigger;                  // Breakpoint starts trigger
304 
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
305 
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
306 
  wire [1:0]  TriggerOper;                // Trigger operation
307 2 mohor 
 
308 9 mohor 
  wire        WpTriggerValid;             // Watchpoint trigger is valid
309 
  wire        BpTriggerValid;             // Breakpoint trigger is valid
310 
  wire        LSSTriggerValid;            // Load/store status trigger is valid
311 
  wire        ITriggerValid;              // Instruction status trigger is valid
312 2 mohor 
 
313 9 mohor 
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
314 
  wire        BpQualif;                   // Breakpoint starts qualifier
315 
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
316 
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
317 
  wire [1:0]  QualifOper;                 // Qualifier operation
318 2 mohor 
 
319 9 mohor 
  wire        WpQualifValid;              // Watchpoint qualifier is valid
320 
  wire        BpQualifValid;              // Breakpoint qualifier is valid
321 
  wire        LSSQualifValid;             // Load/store status qualifier is valid
322 
  wire        IQualifValid;               // Instruction status qualifier is valid
323 2 mohor 
 
324 9 mohor 
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
325 
  wire        BpStop;                     // Breakpoint stops recording of the trace
326 
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
327 
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
328 
  wire [1:0]  StopOper;                   // Stop operation
329 2 mohor 
 
330 9 mohor 
  wire WpStopValid;                       // Watchpoint stop is valid
331 
  wire BpStopValid;                       // Breakpoint stop is valid
332 
  wire LSSStopValid;                      // Load/store status stop is valid
333 
  wire IStopValid;                        // Instruction status stop is valid
334 2 mohor 
 
335 9 mohor 
  wire RecordPC;                          // Recording program counter
336 
  wire RecordLSEA;                        // Recording load/store effective address
337 
  wire RecordLDATA;                       // Recording load data
338 
  wire RecordSDATA;                       // Recording store data
339 
  wire RecordReadSPR;                     // Recording read SPR
340 
  wire RecordWriteSPR;                    // Recording write SPR
341 
  wire RecordINSTR;                       // Recording instruction
342 2 mohor 
 
343 
  // End: Outputs from registers
344 
 
345 9 mohor 
  wire TraceTestScanChain;                // Trace Test Scan chain selected
346 
  wire [47:0] Trace_Data;                 // Trace data
347 2 mohor 
 
348 11 mohor 
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
349 
                                          // data is set to the risc_data_i)
350 30 mohor 
  wire BitCounter_Lt40;
351 11 mohor 
 
352 2 mohor 
`endif
353 
 
354 
 
355 
/**********************************************************************************
356 
*                                                                                 *
357 25 mohor 
*   Synchronizing TRST to clock signal                                            *
358 
*                                                                                 *
359 
**********************************************************************************/
360 32 mohor 
assign trst = ~trst_pad_i;                // trst_pad_i is active low
361 25 mohor 
 
362 
 
363 
/**********************************************************************************
364 
*                                                                                 *
365 2 mohor 
*   TAP State Machine: Fully JTAG compliant                                       *
366 
*                                                                                 *
367 
**********************************************************************************/
368 
 
369 
// TestLogicReset state
370 18 mohor 
always @ (posedge TCK or posedge trst)
371 2 mohor 
begin
372 18 mohor 
  if(trst)
373 2 mohor 
    TestLogicReset<=#Tp 1;
374 
  else
375 
    begin
376 
      if(TMS & (TestLogicReset | SelectIRScan))
377 
        TestLogicReset<=#Tp 1;
378 
      else
379 
        TestLogicReset<=#Tp 0;
380 
    end
381 
end
382 
 
383 
// RunTestIdle state
384 18 mohor 
always @ (posedge TCK or posedge trst)
385 2 mohor 
begin
386 18 mohor 
  if(trst)
387 2 mohor 
    RunTestIdle<=#Tp 0;
388 
  else
389 
    begin
390 
      if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
391 
        RunTestIdle<=#Tp 1;
392 
      else
393 
        RunTestIdle<=#Tp 0;
394 
    end
395 
end
396 
 
397 
// SelectDRScan state
398 18 mohor 
always @ (posedge TCK or posedge trst)
399 2 mohor 
begin
400 18 mohor 
  if(trst)
401 2 mohor 
    SelectDRScan<=#Tp 0;
402 
  else
403 
    begin
404 
      if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
405 
        SelectDRScan<=#Tp 1;
406 
      else
407 
        SelectDRScan<=#Tp 0;
408 
    end
409 
end
410 
 
411 
// CaptureDR state
412 18 mohor 
always @ (posedge TCK or posedge trst)
413 2 mohor 
begin
414 18 mohor 
  if(trst)
415 2 mohor 
    CaptureDR<=#Tp 0;
416 
  else
417 
    begin
418 
      if(~TMS & SelectDRScan)
419 
        CaptureDR<=#Tp 1;
420 
      else
421 
        CaptureDR<=#Tp 0;
422 
    end
423 
end
424 
 
425 
// ShiftDR state
426 18 mohor 
always @ (posedge TCK or posedge trst)
427 2 mohor 
begin
428 18 mohor 
  if(trst)
429 2 mohor 
    ShiftDR<=#Tp 0;
430 
  else
431 
    begin
432 
      if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
433 
        ShiftDR<=#Tp 1;
434 
      else
435 
        ShiftDR<=#Tp 0;
436 
    end
437 
end
438 
 
439 
// Exit1DR state
440 18 mohor 
always @ (posedge TCK or posedge trst)
441 2 mohor 
begin
442 18 mohor 
  if(trst)
443 2 mohor 
    Exit1DR<=#Tp 0;
444 
  else
445 
    begin
446 
      if(TMS & (CaptureDR | ShiftDR))
447 
        Exit1DR<=#Tp 1;
448 
      else
449 
        Exit1DR<=#Tp 0;
450 
    end
451 
end
452 
 
453 
// PauseDR state
454 18 mohor 
always @ (posedge TCK or posedge trst)
455 2 mohor 
begin
456 18 mohor 
  if(trst)
457 2 mohor 
    PauseDR<=#Tp 0;
458 
  else
459 
    begin
460 
      if(~TMS & (Exit1DR | PauseDR))
461 
        PauseDR<=#Tp 1;
462 
      else
463 
        PauseDR<=#Tp 0;
464 
    end
465 
end
466 
 
467 
// Exit2DR state
468 18 mohor 
always @ (posedge TCK or posedge trst)
469 2 mohor 
begin
470 18 mohor 
  if(trst)
471 2 mohor 
    Exit2DR<=#Tp 0;
472 
  else
473 
    begin
474 
      if(TMS & PauseDR)
475 
        Exit2DR<=#Tp 1;
476 
      else
477 
        Exit2DR<=#Tp 0;
478 
    end
479 
end
480 
 
481 
// UpdateDR state
482 18 mohor 
always @ (posedge TCK or posedge trst)
483 2 mohor 
begin
484 18 mohor 
  if(trst)
485 2 mohor 
    UpdateDR<=#Tp 0;
486 
  else
487 
    begin
488 
      if(TMS & (Exit1DR | Exit2DR))
489 
        UpdateDR<=#Tp 1;
490 
      else
491 
        UpdateDR<=#Tp 0;
492 
    end
493 
end
494 
 
495 9 mohor 
// Delayed UpdateDR state
496 2 mohor 
reg UpdateDR_q;
497 
always @ (posedge TCK)
498 
begin
499 
  UpdateDR_q<=#Tp UpdateDR;
500 
end
501 
 
502 
 
503 
// SelectIRScan state
504 18 mohor 
always @ (posedge TCK or posedge trst)
505 2 mohor 
begin
506 18 mohor 
  if(trst)
507 2 mohor 
    SelectIRScan<=#Tp 0;
508 
  else
509 
    begin
510 
      if(TMS & SelectDRScan)
511 
        SelectIRScan<=#Tp 1;
512 
      else
513 
        SelectIRScan<=#Tp 0;
514 
    end
515 
end
516 
 
517 
// CaptureIR state
518 18 mohor 
always @ (posedge TCK or posedge trst)
519 2 mohor 
begin
520 18 mohor 
  if(trst)
521 2 mohor 
    CaptureIR<=#Tp 0;
522 
  else
523 
    begin
524 
      if(~TMS & SelectIRScan)
525 
        CaptureIR<=#Tp 1;
526 
      else
527 
        CaptureIR<=#Tp 0;
528 
    end
529 
end
530 
 
531 
// ShiftIR state
532 18 mohor 
always @ (posedge TCK or posedge trst)
533 2 mohor 
begin
534 18 mohor 
  if(trst)
535 2 mohor 
    ShiftIR<=#Tp 0;
536 
  else
537 
    begin
538 
      if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
539 
        ShiftIR<=#Tp 1;
540 
      else
541 
        ShiftIR<=#Tp 0;
542 
    end
543 
end
544 
 
545 
// Exit1IR state
546 18 mohor 
always @ (posedge TCK or posedge trst)
547 2 mohor 
begin
548 18 mohor 
  if(trst)
549 2 mohor 
    Exit1IR<=#Tp 0;
550 
  else
551 
    begin
552 
      if(TMS & (CaptureIR | ShiftIR))
553 
        Exit1IR<=#Tp 1;
554 
      else
555 
        Exit1IR<=#Tp 0;
556 
    end
557 
end
558 
 
559 
// PauseIR state
560 18 mohor 
always @ (posedge TCK or posedge trst)
561 2 mohor 
begin
562 18 mohor 
  if(trst)
563 2 mohor 
    PauseIR<=#Tp 0;
564 
  else
565 
    begin
566 
      if(~TMS & (Exit1IR | PauseIR))
567 
        PauseIR<=#Tp 1;
568 
      else
569 
        PauseIR<=#Tp 0;
570 
    end
571 
end
572 
 
573 
// Exit2IR state
574 18 mohor 
always @ (posedge TCK or posedge trst)
575 2 mohor 
begin
576 18 mohor 
  if(trst)
577 2 mohor 
    Exit2IR<=#Tp 0;
578 
  else
579 
    begin
580 
      if(TMS & PauseIR)
581 
        Exit2IR<=#Tp 1;
582 
      else
583 
        Exit2IR<=#Tp 0;
584 
    end
585 
end
586 
 
587 
// UpdateIR state
588 18 mohor 
always @ (posedge TCK or posedge trst)
589 2 mohor 
begin
590 18 mohor 
  if(trst)
591 2 mohor 
    UpdateIR<=#Tp 0;
592 
  else
593 
    begin
594 
      if(TMS & (Exit1IR | Exit2IR))
595 
        UpdateIR<=#Tp 1;
596 
      else
597 
        UpdateIR<=#Tp 0;
598 
    end
599 
end
600 
 
601 
/**********************************************************************************
602 
*                                                                                 *
603 
*   End: TAP State Machine                                                        *
604 
*                                                                                 *
605 
**********************************************************************************/
606 
 
607 
 
608 
 
609 
/**********************************************************************************
610 
*                                                                                 *
611 
*   JTAG_IR:  JTAG Instruction Register                                           *
612 
*                                                                                 *
613 
**********************************************************************************/
614 9 mohor 
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
615 2 mohor 
 
616 9 mohor 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
617 
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
618 
 
619 2 mohor 
reg TDOInstruction;
620 
 
621 18 mohor 
always @ (posedge TCK or posedge trst)
622 2 mohor 
begin
623 18 mohor 
  if(trst)
624 2 mohor 
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
625 
  else
626 
    begin
627 
      if(CaptureIR)
628 
        begin
629 
          JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
630 
          JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
631 
        end
632 
      else
633 
        begin
634 
          if(ShiftIR)
635 
            begin
636 
              JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
637 
            end
638 
        end
639 
    end
640 
end
641 
 
642 
 
643 
//TDO is changing on the falling edge of TCK
644 
always @ (negedge TCK)
645 
begin
646 
  if(ShiftIR)
647 
    TDOInstruction <= #Tp JTAG_IR[0];
648 
end
649 9 mohor 
 
650 2 mohor 
/**********************************************************************************
651 
*                                                                                 *
652 
*   End: JTAG_IR                                                                  *
653 
*                                                                                 *
654 
**********************************************************************************/
655 
 
656 
 
657 
/**********************************************************************************
658 
*                                                                                 *
659 
*   JTAG_DR:  JTAG Data Register                                                  *
660 
*                                                                                 *
661 
**********************************************************************************/
662 
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
663 
reg TDOData;
664 
 
665 
 
666 18 mohor 
always @ (posedge TCK or posedge trst)
667 2 mohor 
begin
668 18 mohor 
  if(trst)
669 2 mohor 
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
670 
  else
671 30 mohor 
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
672 
    begin
673 
      if(ShiftDR)
674 
        JTAG_DR_IN[31:0] <= #Tp {TDI, JTAG_DR_IN[31:1]};
675 
      else
676 
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
677 
    end
678 
  else
679 
  if(CHAIN_SELECTSelected & ShiftDR)
680 
    JTAG_DR_IN[12:0] <= #Tp {TDI, JTAG_DR_IN[12:1]};
681 
  else
682 
  if(DEBUGSelected & ShiftDR)
683 
    begin
684 
      if(RiscDebugScanChain | WishboneScanChain)
685 
        JTAG_DR_IN[73:0] <= #Tp {TDI, JTAG_DR_IN[73:1]};
686 
      else
687 
      if(RegisterScanChain)
688 
        JTAG_DR_IN[46:0] <= #Tp {TDI, JTAG_DR_IN[46:1]};
689 
    end
690 2 mohor 
end
691 30 mohor 
 
692 22 mohor 
wire [73:0] RISC_Data;
693 
wire [46:0] Register_Data;
694 
wire [73:0] WISHBONE_Data;
695 21 mohor 
wire [12:0] chain_sel_data;
696 12 mohor 
wire wb_Access_wbClk;
697 2 mohor 
 
698 
 
699 30 mohor 
reg select_crc_out;
700 
always @ (posedge TCK or posedge trst)
701 
begin
702 
  if(trst)
703 
    select_crc_out <= 0;
704 
  else
705 
  if( RegisterScanChain  & BitCounter_Eq5  |
706 
      RiscDebugScanChain & BitCounter_Eq32 |
707 
      WishboneScanChain  & BitCounter_Eq32 )
708 
    select_crc_out <=#Tp TDI;
709 
  else
710 
  if(CHAIN_SELECTSelected)
711 
    select_crc_out <=#Tp 1;
712 
  else
713 
  if(UpdateDR)
714 
    select_crc_out <=#Tp 0;
715 
end
716 12 mohor 
 
717 20 mohor 
wire [8:0] send_crc;
718 
 
719 30 mohor 
assign send_crc = select_crc_out? {9{BypassRegister}}    :    // Calculated CRC is returned when read operation is
720 
                                  {CalculatedCrcOut, 1'b0} ;  // performed, else received crc is returned (loopback).
721 20 mohor 
 
722 30 mohor 
assign RISC_Data      = {send_crc, DataReadLatch, 33'h0};
723 
assign Register_Data  = {send_crc, DataReadLatch, 6'h0};
724 20 mohor 
assign WISHBONE_Data  = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
725 21 mohor 
assign chain_sel_data = {send_crc, 4'h0};
726 20 mohor 
 
727 
 
728 
`ifdef TRACE_ENABLED
729 2 mohor 
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
730 
`endif
731 
 
732 
//TDO is changing on the falling edge of TCK
733 18 mohor 
always @ (negedge TCK or posedge trst)
734 2 mohor 
begin
735 18 mohor 
  if(trst)
736 2 mohor 
    begin
737 
      TDOData <= #Tp 0;
738 
      `ifdef TRACE_ENABLED
739 
      ReadBuffer_Tck<=#Tp 0;
740 
      `endif
741 
    end
742 
  else
743 
  if(UpdateDR)
744 
    begin
745 
      TDOData <= #Tp CrcMatch;
746 
      `ifdef TRACE_ENABLED
747 9 mohor 
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
748 
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
749 2 mohor 
      `endif
750 
    end
751 
  else
752 
    begin
753 
      if(ShiftDR)
754 
        begin
755 
          if(IDCODESelected)
756 30 mohor 
            TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then TDI is bypassed
757 2 mohor 
          else
758 
          if(CHAIN_SELECTSelected)
759 21 mohor 
            TDOData <= #Tp chain_sel_data[BitCounter];        // Received crc is sent back
760 2 mohor 
          else
761 
          if(DEBUGSelected)
762 
            begin
763 
              if(RiscDebugScanChain)
764 9 mohor 
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
765 2 mohor 
              else
766 
              if(RegisterScanChain)
767 9 mohor 
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
768 12 mohor 
              else
769 
              if(WishboneScanChain)
770 
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
771 2 mohor 
              `ifdef TRACE_ENABLED
772 
              else
773 
              if(TraceTestScanChain)
774 9 mohor 
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
775 2 mohor 
              `endif
776 
            end
777 
        end
778 
      else
779 
        begin
780 
          TDOData <= #Tp 0;
781 
          `ifdef TRACE_ENABLED
782 
          ReadBuffer_Tck<=#Tp 0;
783 
          `endif
784 
        end
785 
    end
786 
end
787 
 
788 
/**********************************************************************************
789 
*                                                                                 *
790 
*   End: JTAG_DR                                                                  *
791 
*                                                                                 *
792 
**********************************************************************************/
793 
 
794 
 
795 
 
796 
/**********************************************************************************
797 
*                                                                                 *
798 
*   CHAIN_SELECT logic                                                            *
799 
*                                                                                 *
800 
**********************************************************************************/
801 18 mohor 
always @ (posedge TCK or posedge trst)
802 2 mohor 
begin
803 18 mohor 
  if(trst)
804 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
805 2 mohor 
  else
806 
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
807 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
808 2 mohor 
end
809 
 
810 
 
811 
 
812 
/**********************************************************************************
813 
*                                                                                 *
814 
*   Register read/write logic                                                     *
815 
*   RISC registers read/write logic                                               *
816 
*                                                                                 *
817 
**********************************************************************************/
818 18 mohor 
always @ (posedge TCK or posedge trst)
819 2 mohor 
begin
820 18 mohor 
  if(trst)
821 2 mohor 
    begin
822 
      ADDR[31:0]        <=#Tp 32'h0;
823 
      DataOut[31:0]     <=#Tp 32'h0;
824 
      RW                <=#Tp 1'b0;
825 
      RegAccessTck      <=#Tp 1'b0;
826 
      RISCAccessTck     <=#Tp 1'b0;
827 12 mohor 
      wb_AccessTck      <=#Tp 1'h0;
828 2 mohor 
    end
829 
  else
830 
  if(UpdateDR & DEBUGSelected & CrcMatch)
831 
    begin
832 
      if(RegisterScanChain)
833 
        begin
834 
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
835 
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
836 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
837 
          RegAccessTck      <=#Tp 1'b1;
838 
        end
839 
      else
840 
      if(RiscDebugScanChain)
841 
        begin
842 
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
843 
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
844 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
845 
          RISCAccessTck     <=#Tp 1'b1;
846 
        end
847 12 mohor 
      else
848 
      if(WishboneScanChain)
849 
        begin
850 20 mohor 
          ADDR              <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
851 
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
852 
          DataOut           <=#Tp JTAG_DR_IN[64:33];  // latch data for write
853 12 mohor 
          wb_AccessTck      <=#Tp 1'b1;               //
854 
        end
855 2 mohor 
    end
856 
  else
857 
    begin
858 
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one TCK clock period only
859 
      RISCAccessTck     <=#Tp 1'b0;
860 12 mohor 
      wb_AccessTck      <=#Tp 1'b0;
861 2 mohor 
    end
862 
end
863 
 
864 20 mohor 
 
865 
assign wb_adr_o = ADDR;
866 
assign wb_we_o  = RW;
867 
assign wb_dat_o = DataOut;
868 12 mohor 
assign wb_sel_o[3:0] = 4'hf;
869 
assign wb_cab_o = 1'b0;
870 20 mohor 
 
871 
 
872 11 mohor 
// Synchronizing the RegAccess signal to risc_clk_i clock
873 18 mohor 
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
874 2 mohor 
                         .set2(RegAccessTck), .sync_out(RegAccess)
875 
                        );
876 
 
877 11 mohor 
// Synchronizing the RISCAccess signal to risc_clk_i clock
878 30 mohor 
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(TCK),          .reset1(wb_rst_i),  .reset2(trst),
879 2 mohor 
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
880 
                        );
881 
 
882 
 
883 12 mohor 
// Synchronizing the wb_Access signal to wishbone clock
884 30 mohor 
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),     .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
885 12 mohor 
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
886 
                        );
887 
 
888 
 
889 
 
890 
 
891 
 
892 9 mohor 
// Delayed signals used for accessing registers and RISC
893 18 mohor 
always @ (posedge risc_clk_i or posedge wb_rst_i)
894 2 mohor 
begin
895 18 mohor 
  if(wb_rst_i)
896 2 mohor 
    begin
897 
      RegAccess_q   <=#Tp 1'b0;
898 
      RegAccess_q2  <=#Tp 1'b0;
899 
      RISCAccess_q  <=#Tp 1'b0;
900 
      RISCAccess_q2 <=#Tp 1'b0;
901 
    end
902 
  else
903 
    begin
904 
      RegAccess_q   <=#Tp RegAccess;
905 
      RegAccess_q2  <=#Tp RegAccess_q;
906 
      RISCAccess_q  <=#Tp RISCAccess;
907 
      RISCAccess_q2 <=#Tp RISCAccess_q;
908 
    end
909 
end
910 
 
911 9 mohor 
// Chip select and read/write signals for accessing RISC
912 11 mohor 
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
913 
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
914 
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
915 2 mohor 
 
916 
 
917 12 mohor 
reg wb_Access_wbClk_q;
918 
// Delayed signals used for accessing WISHBONE
919 18 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
920 12 mohor 
begin
921 18 mohor 
  if(wb_rst_i)
922 12 mohor 
    wb_Access_wbClk_q <=#Tp 1'b0;
923 
  else
924 
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
925 
end
926 
 
927 18 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
928 12 mohor 
begin
929 18 mohor 
  if(wb_rst_i)
930 12 mohor 
    wb_cyc_o <=#Tp 1'b0;
931 
  else
932 
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
933 
    wb_cyc_o <=#Tp 1'b1;
934 
  else
935 
  if(wb_ack_i | wb_err_i)
936 
    wb_cyc_o <=#Tp 1'b0;
937 
end
938 
 
939 
assign wb_stb_o = wb_cyc_o;
940 
 
941 
 
942 
// Latching data read from registers
943 19 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
944 12 mohor 
begin
945 18 mohor 
  if(wb_rst_i)
946 12 mohor 
    WBReadLatch[31:0]<=#Tp 32'h0;
947 
  else
948 
  if(wb_ack_i)
949 
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
950 
end
951 
 
952 
// Latching WISHBONE error cycle
953 18 mohor 
always @ (posedge wb_clk_i or posedge wb_rst_i)
954 12 mohor 
begin
955 18 mohor 
  if(wb_rst_i)
956 12 mohor 
    WBErrorLatch<=#Tp 1'b0;
957 
  else
958 
  if(wb_err_i)
959 
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
960 20 mohor 
  else
961 12 mohor 
  if(wb_ack_i)
962 
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
963 
end
964 
 
965 
 
966 9 mohor 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
967 5 mohor 
`ifdef TRACE_ENABLED
968 11 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
969 5 mohor 
`else
970 12 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
971 5 mohor 
`endif
972 
 
973 11 mohor 
assign  reset_o = RiscReset_reg;
974 5 mohor 
 
975 
 
976 12 mohor 
`ifdef TRACE_ENABLED
977 11 mohor 
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
978 12 mohor 
`else
979 
always @ (RiscStall_write_access or RiscStall_read_access)
980 
`endif
981 11 mohor 
begin
982 
  if(RiscStall_write_access)
983 
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
984 
  else
985 
  if(RiscStall_read_access)
986 
    opselect_o = `DEBUG_READ_SPR;   // Read spr
987 
  else
988 12 mohor 
`ifdef TRACE_ENABLED
989 11 mohor 
    opselect_o = opselect_trace;
990 12 mohor 
`else
991 
    opselect_o = 3'h0;
992 
`endif
993 11 mohor 
end
994 9 mohor 
 
995 11 mohor 
 
996 30 mohor 
// Latching data read from RISC or registers
997 18 mohor 
always @ (posedge risc_clk_i or posedge wb_rst_i)
998 2 mohor 
begin
999 18 mohor 
  if(wb_rst_i)
1000 30 mohor 
    DataReadLatch[31:0]<=#Tp 0;
1001 2 mohor 
  else
1002 
  if(RISCAccess_q & ~RISCAccess_q2)
1003 30 mohor 
    DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
1004 
  else
1005 
  if(RegAccess_q & ~RegAccess_q2)
1006 
    DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
1007 2 mohor 
end
1008 
 
1009 12 mohor 
assign risc_addr_o = ADDR;
1010 
assign risc_data_o = DataOut;
1011 2 mohor 
 
1012 
 
1013 
 
1014 
/**********************************************************************************
1015 
*                                                                                 *
1016 
*   Read Trace buffer logic                                                       *
1017 
*                                                                                 *
1018 
**********************************************************************************/
1019 
`ifdef TRACE_ENABLED
1020 
 
1021 9 mohor 
 
1022 11 mohor 
// Synchronizing the trace read buffer signal to risc_clk_i clock
1023 18 mohor 
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(TCK),           .reset1(wb_rst_i),  .reset2(trst),
1024 9 mohor 
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
1025 
                        );
1026 
 
1027 
 
1028 
 
1029 18 mohor 
  always @(posedge risc_clk_i or posedge wb_rst_i)
1030 2 mohor 
  begin
1031 18 mohor 
    if(wb_rst_i)
1032 9 mohor 
      ReadTraceBuffer_q <=#Tp 0;
1033 2 mohor 
    else
1034 9 mohor 
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
1035 2 mohor 
  end
1036 9 mohor 
 
1037 
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
1038 
 
1039 2 mohor 
`endif
1040 
 
1041 
/**********************************************************************************
1042 
*                                                                                 *
1043 
*   End: Read Trace buffer logic                                                  *
1044 
*                                                                                 *
1045 
**********************************************************************************/
1046 
 
1047 
 
1048 
/**********************************************************************************
1049 
*                                                                                 *
1050 
*   Bypass logic                                                                  *
1051 
*                                                                                 *
1052 
**********************************************************************************/
1053 
reg TDOBypassed;
1054 
 
1055 
always @ (posedge TCK)
1056 
begin
1057 
  if(ShiftDR)
1058 
    BypassRegister<=#Tp TDI;
1059 
end
1060 
 
1061 
always @ (negedge TCK)
1062 
begin
1063 
    TDOBypassed<=#Tp BypassRegister;
1064 
end
1065 
/**********************************************************************************
1066 
*                                                                                 *
1067 
*   End: Bypass logic                                                             *
1068 
*                                                                                 *
1069 
**********************************************************************************/
1070 
 
1071 
 
1072 
 
1073 
 
1074 
 
1075 
/**********************************************************************************
1076 
*                                                                                 *
1077 
*   Activating Instructions                                                       *
1078 
*                                                                                 *
1079 
**********************************************************************************/
1080 
 
1081 
// Updating JTAG_IR (Instruction Register)
1082 18 mohor 
always @ (posedge TCK or posedge trst)
1083 2 mohor 
begin
1084 18 mohor 
  if(trst)
1085 9 mohor 
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
1086 2 mohor 
  else
1087 9 mohor 
  if(UpdateIR)
1088 
    LatchedJTAG_IR <=#Tp JTAG_IR;
1089 2 mohor 
end
1090 
 
1091 
 
1092 9 mohor 
 
1093 
// Updating JTAG_IR (Instruction Register)
1094 
always @ (LatchedJTAG_IR)
1095 
begin
1096 
  EXTESTSelected          = 0;
1097 
  SAMPLE_PRELOADSelected  = 0;
1098 
  IDCODESelected          = 0;
1099 
  CHAIN_SELECTSelected    = 0;
1100 
  INTESTSelected          = 0;
1101 
  CLAMPSelected           = 0;
1102 
  CLAMPZSelected          = 0;
1103 
  HIGHZSelected           = 0;
1104 
  DEBUGSelected           = 0;
1105 
  BYPASSSelected          = 0;
1106 
 
1107 
  case(LatchedJTAG_IR)
1108 
    `EXTEST:            EXTESTSelected          = 1;    // External test
1109 
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
1110 
    `IDCODE:            IDCODESelected          = 1;    // ID Code
1111 
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
1112 
    `INTEST:            INTESTSelected          = 1;    // Internal test
1113 
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
1114 
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
1115 
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
1116 
    `DEBUG:             DEBUGSelected           = 1;    // Debug
1117 
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
1118 
    default:            BYPASSSelected          = 1;    // BYPASS
1119 
  endcase
1120 
end
1121 
 
1122 
 
1123 5 mohor 
/**********************************************************************************
1124 9 mohor 
*                                                                                 *
1125 
*   Multiplexing TDO and Tristate control                                         *
1126 
*                                                                                 *
1127 5 mohor 
**********************************************************************************/
1128 
wire TDOShifted;
1129 
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
1130 
/**********************************************************************************
1131 9 mohor 
*                                                                                 *
1132 
*   End:  Multiplexing TDO and Tristate control                                   *
1133 
*                                                                                 *
1134 5 mohor 
**********************************************************************************/
1135 
 
1136 
 
1137 
 
1138 9 mohor 
// This multiplexer can be expanded with number of user registers
1139 5 mohor 
reg TDOMuxed;
1140 33 mohor 
//always @ (JTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
1141 
always @ (LatchedJTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
1142 2 mohor 
begin
1143 
  case(JTAG_IR)
1144 
    `IDCODE: // Reading ID code
1145 
      begin
1146 
        TDOMuxed<=#Tp TDOShifted;
1147 
      end
1148 
    `CHAIN_SELECT: // Selecting the chain
1149 
      begin
1150 
        TDOMuxed<=#Tp TDOShifted;
1151 
      end
1152 
    `DEBUG: // Debug
1153 
      begin
1154 
        TDOMuxed<=#Tp TDOShifted;
1155 
      end
1156 12 mohor 
    `SAMPLE_PRELOAD:  // Sampling/Preloading
1157 
      begin
1158 
        TDOMuxed<=#Tp BS_CHAIN_I;
1159 
      end
1160 
    `EXTEST:  // External test
1161 
      begin
1162 
        TDOMuxed<=#Tp BS_CHAIN_I;
1163 
      end
1164 2 mohor 
    default:  // BYPASS instruction
1165 
      begin
1166 
        TDOMuxed<=#Tp TDOBypassed;
1167 
      end
1168 
  endcase
1169 
end
1170 
 
1171 9 mohor 
// Tristate control for tdo_pad_o pin
1172 28 mohor 
//assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
1173 
assign tdo_pad_o = TDOMuxed;
1174 
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
1175 2 mohor 
 
1176 
/**********************************************************************************
1177 
*                                                                                 *
1178 
*   End: Activating Instructions                                                  *
1179 
*                                                                                 *
1180 
**********************************************************************************/
1181 
 
1182 
/**********************************************************************************
1183 
*                                                                                 *
1184 
*   Bit counter                                                                   *
1185 
*                                                                                 *
1186 
**********************************************************************************/
1187 
 
1188 
 
1189 18 mohor 
always @ (posedge TCK or posedge trst)
1190 2 mohor 
begin
1191 18 mohor 
  if(trst)
1192 2 mohor 
    BitCounter[7:0]<=#Tp 0;
1193 
  else
1194 
  if(ShiftDR)
1195 
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
1196 
  else
1197 
  if(UpdateDR)
1198 
    BitCounter[7:0]<=#Tp 0;
1199 
end
1200 
 
1201 
 
1202 
 
1203 
/**********************************************************************************
1204 
*                                                                                 *
1205 
*   End: Bit counter                                                              *
1206 
*                                                                                 *
1207 
**********************************************************************************/
1208 
 
1209 
 
1210 
 
1211 
/**********************************************************************************
1212 
*                                                                                 *
1213 
*   Connecting Registers                                                          *
1214 
*                                                                                 *
1215 
**********************************************************************************/
1216 
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
1217 11 mohor 
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
1218 12 mohor 
                      .Bp(bp_i), .Reset(wb_rst_i),
1219 2 mohor 
                      `ifdef TRACE_ENABLED
1220 5 mohor 
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
1221 2 mohor 
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
1222 
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
1223 
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
1224 5 mohor 
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
1225 
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
1226 
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
1227 
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
1228 
                      .WpTriggerValid(WpTriggerValid),
1229 2 mohor 
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
1230 
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
1231 
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
1232 
                      .IQualifValid(IQualifValid),
1233 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1234 5 mohor 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1235 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
1236 2 mohor 
                      `endif
1237 5 mohor 
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
1238 
 
1239 2 mohor 
                     );
1240 
 
1241 
/**********************************************************************************
1242 
*                                                                                 *
1243 
*   End: Connecting Registers                                                     *
1244 
*                                                                                 *
1245 
**********************************************************************************/
1246 
 
1247 
 
1248 
/**********************************************************************************
1249 
*                                                                                 *
1250 
*   Connecting CRC module                                                         *
1251 
*                                                                                 *
1252 
**********************************************************************************/
1253 18 mohor 
wire AsyncResetCrc = trst;
1254 9 mohor 
wire SyncResetCrc = UpdateDR_q;
1255 2 mohor 
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
1256 
 
1257 30 mohor 
assign BitCounter_Lt4   = BitCounter<4;
1258 
assign BitCounter_Eq5   = BitCounter==5;
1259 
assign BitCounter_Eq32  = BitCounter==32;
1260 
assign BitCounter_Lt38  = BitCounter<38;
1261 
assign BitCounter_Lt65  = BitCounter<65;
1262 
 
1263 
`ifdef TRACE_ENABLED
1264 
  assign BitCounter_Lt40 = BitCounter<40;
1265 
`endif
1266 
 
1267 
 
1268 2 mohor 
wire EnableCrcIn = ShiftDR &
1269 30 mohor 
                  ( (CHAIN_SELECTSelected                 & BitCounter_Lt4) |
1270 
                    ((DEBUGSelected & RegisterScanChain)  & BitCounter_Lt38)|
1271 
                    ((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
1272 
                    ((DEBUGSelected & WishboneScanChain)  & BitCounter_Lt65)
1273 9 mohor 
                  );
1274 2 mohor 
 
1275 
wire EnableCrcOut= ShiftDR &
1276 9 mohor 
                   (
1277 30 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & BitCounter_Lt38)|
1278 
                    ((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
1279 
                    ((DEBUGSelected & WishboneScanChain)  & BitCounter_Lt65)
1280 2 mohor 
                    `ifdef TRACE_ENABLED
1281 30 mohor 
                                                                            |
1282 
                    ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
1283 2 mohor 
                    `endif
1284 9 mohor 
                   );
1285 2 mohor 
 
1286 
// Calculating crc for input data
1287 9 mohor 
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1288 2 mohor 
                  .CrcOut(CalculatedCrcIn), .Clk(TCK));
1289 
 
1290 
// Calculating crc for output data
1291 9 mohor 
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1292 2 mohor 
                  .CrcOut(CalculatedCrcOut), .Clk(TCK));
1293 
 
1294 
 
1295 
// Generating CrcMatch signal
1296 18 mohor 
always @ (posedge TCK or posedge trst)
1297 2 mohor 
begin
1298 18 mohor 
  if(trst)
1299 2 mohor 
    CrcMatch <=#Tp 1'b0;
1300 
  else
1301 
  if(Exit1DR)
1302 
    begin
1303 
      if(CHAIN_SELECTSelected)
1304 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
1305 
      else
1306 30 mohor 
        begin
1307 
          if(RegisterScanChain)
1308 
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
1309 
          else
1310 
          if(RiscDebugScanChain)
1311 
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1312 
          else
1313 
          if(WishboneScanChain)
1314 
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1315 
        end
1316 2 mohor 
    end
1317 
end
1318 
 
1319 
 
1320 
// Active chain
1321 
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
1322 
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
1323 12 mohor 
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
1324 2 mohor 
 
1325 
`ifdef TRACE_ENABLED
1326 
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
1327 
`endif
1328 
 
1329 
/**********************************************************************************
1330 
*                                                                                 *
1331 
*   End: Connecting CRC module                                                    *
1332 
*                                                                                 *
1333 
**********************************************************************************/
1334 
 
1335 
/**********************************************************************************
1336 
*                                                                                 *
1337 
*   Connecting trace module                                                       *
1338 
*                                                                                 *
1339 
**********************************************************************************/
1340 
`ifdef TRACE_ENABLED
1341 11 mohor 
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
1342 9 mohor 
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
1343 18 mohor 
                      .Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
1344 8 mohor 
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
1345 5 mohor 
                      .WpTrigger(WpTrigger),
1346 2 mohor 
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
1347 
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
1348 
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
1349 5 mohor 
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
1350 
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
1351 
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
1352 
                      .RecordINSTR(RecordINSTR),
1353 2 mohor 
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
1354 
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
1355 
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
1356 
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
1357 9 mohor 
                      .ReadBuffer(ReadTraceBufferPulse),
1358 2 mohor 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1359 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1360 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
1361 
                     );
1362 
`endif
1363 
/**********************************************************************************
1364 
*                                                                                 *
1365 
*   End: Connecting trace module                                                  *
1366 
*                                                                                 *
1367 
**********************************************************************************/
1368 
 
1369 
 
1370 
 
1371 9 mohor 
endmodule

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