OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Blame information for rev 37

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  dbg_top.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the SoC/OpenRISC Development Interface ////
7 36 mohor
////  http://www.opencores.org/projects/DebugInterface/           ////
8 2 mohor
////                                                              ////
9
////                                                              ////
10
////  Author(s):                                                  ////
11
////       Igor Mohor                                             ////
12
////       igorm@opencores.org                                    ////
13
////                                                              ////
14
////                                                              ////
15
////  All additional information is avaliable in the README.txt   ////
16
////  file.                                                       ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000,2001 Authors                              ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48 37 mohor
// Revision 1.21  2002/03/08 15:28:16  mohor
49
// Structure changed. Hooks for jtag chain added.
50
//
51 36 mohor
// Revision 1.20  2002/02/06 12:23:09  mohor
52
// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
53
//
54 33 mohor
// Revision 1.19  2002/02/05 13:34:51  mohor
55
// Stupid bug that was entered by previous update fixed.
56
//
57 32 mohor
// Revision 1.18  2002/02/05 12:41:01  mohor
58
// trst synchronization is not needed and was removed.
59
//
60 31 mohor
// Revision 1.17  2002/01/25 07:58:35  mohor
61
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
62
// not filled-in. Tested in hw.
63
//
64 30 mohor
// Revision 1.16  2001/12/20 11:17:26  mohor
65
// TDO and TDO Enable signal are separated into two signals.
66
//
67 28 mohor
// Revision 1.15  2001/12/05 13:28:21  mohor
68
// trst signal is synchronized to wb_clk_i.
69
//
70 25 mohor
// Revision 1.14  2001/11/28 09:36:15  mohor
71
// Register length fixed.
72
//
73 22 mohor
// Revision 1.13  2001/11/27 13:37:43  mohor
74
// CRC is returned when chain selection data is transmitted.
75
//
76 21 mohor
// Revision 1.12  2001/11/26 10:47:09  mohor
77
// Crc generation is different for read or write commands. Small synthesys fixes.
78
//
79 20 mohor
// Revision 1.11  2001/11/14 10:10:41  mohor
80
// Wishbone data latched on wb_clk_i instead of risc_clk.
81
//
82 19 mohor
// Revision 1.10  2001/11/12 01:11:27  mohor
83
// Reset signals are not combined any more.
84
//
85 18 mohor
// Revision 1.9  2001/10/19 11:40:01  mohor
86
// dbg_timescale.v changed to timescale.v This is done for the simulation of
87
// few different cores in a single project.
88
//
89 17 mohor
// Revision 1.8  2001/10/17 10:39:03  mohor
90
// bs_chain_o added.
91
//
92 15 mohor
// Revision 1.7  2001/10/16 10:09:56  mohor
93
// Signal names changed to lowercase.
94 13 mohor
//
95 15 mohor
//
96 13 mohor
// Revision 1.6  2001/10/15 09:55:47  mohor
97
// Wishbone interface added, few fixes for better performance,
98
// hooks for boundary scan testing added.
99
//
100 12 mohor
// Revision 1.5  2001/09/24 14:06:42  mohor
101
// Changes connected to the OpenRISC access (SPR read, SPR write).
102
//
103 11 mohor
// Revision 1.4  2001/09/20 10:11:25  mohor
104
// Working version. Few bugs fixed, comments added.
105
//
106 9 mohor
// Revision 1.3  2001/09/19 11:55:13  mohor
107
// Asynchronous set/reset not used in trace any more.
108
//
109 8 mohor
// Revision 1.2  2001/09/18 14:13:47  mohor
110
// Trace fixed. Some registers changed, trace simplified.
111
//
112 5 mohor
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
113
// Initial official release.
114
//
115 2 mohor
// Revision 1.3  2001/06/01 22:22:35  mohor
116
// This is a backup. It is not a fully working version. Not for use, yet.
117
//
118
// Revision 1.2  2001/05/18 13:10:00  mohor
119
// Headers changed. All additional information is now avaliable in the README.txt file.
120
//
121
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
122
// Initial release
123
//
124
//
125
 
126 20 mohor
// synopsys translate_off
127 17 mohor
`include "timescale.v"
128 20 mohor
// synopsys translate_on
129 2 mohor
`include "dbg_defines.v"
130
 
131
// Top module
132 9 mohor
module dbg_top(
133
 
134
                // RISC signals
135 11 mohor
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
136
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
137 9 mohor
 
138 12 mohor
                // WISHBONE common signals
139
                wb_rst_i, wb_clk_i,
140
 
141
                // WISHBONE master interface
142
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
143 36 mohor
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
144 12 mohor
 
145 36 mohor
                // TAP states
146
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
147
 
148
                // Instructions
149
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
150
 
151
                // TAP signals
152 37 mohor
                trst_in, tck, tdi, TDOData,
153 36 mohor
 
154
                BypassRegister
155 37 mohor
 
156 2 mohor
              );
157
 
158
parameter Tp = 1;
159
 
160
 
161 9 mohor
// RISC signals
162 11 mohor
input         risc_clk_i;                 // Master clock (RISC clock)
163 9 mohor
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
164
input  [10:0] wp_i;                       // Watchpoint inputs
165
input         bp_i;                       // Breakpoint input
166
input  [3:0]  lsstatus_i;                 // Load/store status inputs
167
input  [1:0]  istatus_i;                  // Instruction status inputs
168
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
169
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
170
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
171
output                      risc_stall_o; // Stalls the RISC
172 11 mohor
output                      reset_o;      // Resets the RISC
173 2 mohor
 
174
 
175 12 mohor
// WISHBONE common signals
176 9 mohor
input         wb_rst_i;                   // WISHBONE reset
177 12 mohor
input         wb_clk_i;                   // WISHBONE clock
178 9 mohor
 
179 12 mohor
// WISHBONE master interface
180
output [31:0] wb_adr_o;
181
output [31:0] wb_dat_o;
182
input  [31:0] wb_dat_i;
183
output        wb_cyc_o;
184
output        wb_stb_o;
185
output  [3:0] wb_sel_o;
186
output        wb_we_o;
187
input         wb_ack_i;
188
output        wb_cab_o;
189
input         wb_err_i;
190 9 mohor
 
191
// TAP states
192 36 mohor
input         ShiftDR;
193
input         Exit1DR;
194
input         UpdateDR;
195
input         UpdateDR_q;
196 2 mohor
 
197 37 mohor
input trst_in;
198 36 mohor
input tck;
199
input tdi;
200 2 mohor
 
201 36 mohor
input BypassRegister;
202 9 mohor
 
203 36 mohor
output TDOData;
204
 
205
 
206 9 mohor
// Defining which instruction is selected
207 36 mohor
input         IDCODESelected;
208
input         CHAIN_SELECTSelected;
209
input         DEBUGSelected;
210 2 mohor
 
211 36 mohor
reg           wb_cyc_o;
212 9 mohor
 
213 36 mohor
reg [31:0]    ADDR;
214
reg [31:0]    DataOut;
215 11 mohor
 
216 36 mohor
reg [`OPSELECTWIDTH-1:0] opselect_o;        // Operation selection (selecting what kind of data is set to the risc_data_i)
217 2 mohor
 
218 36 mohor
reg [`CHAIN_ID_LENGTH-1:0] Chain;           // Selected chain
219
reg [31:0]    DataReadLatch;                // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
220
reg           RegAccessTck;                 // Indicates access to the registers (read or write)
221
reg           RISCAccessTck;                // Indicates access to the RISC (read or write)
222
reg [7:0]     BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
223
reg           RW;                           // Read/Write bit
224
reg           CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
225 2 mohor
 
226 36 mohor
reg           RegAccess_q;                  // Delayed signals used for accessing the registers
227
reg           RegAccess_q2;                 // Delayed signals used for accessing the registers
228
reg           RISCAccess_q;                 // Delayed signals used for accessing the RISC
229
reg           RISCAccess_q2;                // Delayed signals used for accessing the RISC
230 2 mohor
 
231 36 mohor
reg           wb_AccessTck;                 // Indicates access to the WISHBONE
232
reg [31:0]    WBReadLatch;                  // Data latched during WISHBONE read
233
reg           WBErrorLatch;                 // Error latched during WISHBONE read
234 30 mohor
 
235 37 mohor
wire trst;
236 30 mohor
 
237 37 mohor
 
238 9 mohor
wire [31:0]             RegDataIn;        // Data from registers (read data)
239
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
240 2 mohor
 
241 9 mohor
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
242
wire RiscReset_reg;                       // RISC is reset by setting the register bit
243
wire RiscStall_trace;                     // RISC is stalled by trace module
244
 
245
 
246
wire RegisterScanChain;                   // Register Scan chain selected
247
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
248 12 mohor
wire WishboneScanChain;                   // WISHBONE Scan chain selected
249 11 mohor
 
250
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
251
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
252
wire RiscStall_access;                    // Stalling RISC because of the read or write access
253
 
254 30 mohor
wire BitCounter_Lt4;
255
wire BitCounter_Eq5;
256
wire BitCounter_Eq32;
257
wire BitCounter_Lt38;
258
wire BitCounter_Lt65;
259
 
260 15 mohor
 
261
 
262 9 mohor
// This signals are used only when TRACE is used in the design
263 2 mohor
`ifdef TRACE_ENABLED
264 9 mohor
  wire [39:0] TraceChain;                 // Chain that comes from trace module
265 36 mohor
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with tck)
266 9 mohor
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
267
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
268
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
269 2 mohor
 
270
  // Outputs from registers
271 9 mohor
  wire ContinMode;                        // Trace working in continous mode
272
  wire TraceEnable;                       // Trace enabled
273 2 mohor
 
274 9 mohor
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
275
  wire        BpTrigger;                  // Breakpoint starts trigger
276
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
277
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
278
  wire [1:0]  TriggerOper;                // Trigger operation
279 2 mohor
 
280 9 mohor
  wire        WpTriggerValid;             // Watchpoint trigger is valid
281
  wire        BpTriggerValid;             // Breakpoint trigger is valid
282
  wire        LSSTriggerValid;            // Load/store status trigger is valid
283
  wire        ITriggerValid;              // Instruction status trigger is valid
284 2 mohor
 
285 9 mohor
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
286
  wire        BpQualif;                   // Breakpoint starts qualifier
287
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
288
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
289
  wire [1:0]  QualifOper;                 // Qualifier operation
290 2 mohor
 
291 9 mohor
  wire        WpQualifValid;              // Watchpoint qualifier is valid
292
  wire        BpQualifValid;              // Breakpoint qualifier is valid
293
  wire        LSSQualifValid;             // Load/store status qualifier is valid
294
  wire        IQualifValid;               // Instruction status qualifier is valid
295 2 mohor
 
296 9 mohor
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
297
  wire        BpStop;                     // Breakpoint stops recording of the trace
298
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
299
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
300
  wire [1:0]  StopOper;                   // Stop operation
301 2 mohor
 
302 9 mohor
  wire WpStopValid;                       // Watchpoint stop is valid
303
  wire BpStopValid;                       // Breakpoint stop is valid
304
  wire LSSStopValid;                      // Load/store status stop is valid
305
  wire IStopValid;                        // Instruction status stop is valid
306 2 mohor
 
307 9 mohor
  wire RecordPC;                          // Recording program counter
308
  wire RecordLSEA;                        // Recording load/store effective address
309
  wire RecordLDATA;                       // Recording load data
310
  wire RecordSDATA;                       // Recording store data
311
  wire RecordReadSPR;                     // Recording read SPR
312
  wire RecordWriteSPR;                    // Recording write SPR
313
  wire RecordINSTR;                       // Recording instruction
314 2 mohor
 
315
  // End: Outputs from registers
316
 
317 9 mohor
  wire TraceTestScanChain;                // Trace Test Scan chain selected
318
  wire [47:0] Trace_Data;                 // Trace data
319 2 mohor
 
320 11 mohor
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
321
                                          // data is set to the risc_data_i)
322 30 mohor
  wire BitCounter_Lt40;
323 11 mohor
 
324 2 mohor
`endif
325
 
326
 
327 37 mohor
assign trst = ~trst_in;                   // trst_pad_i is active low
328 25 mohor
 
329
 
330 2 mohor
/**********************************************************************************
331
*                                                                                 *
332
*   JTAG_DR:  JTAG Data Register                                                  *
333
*                                                                                 *
334
**********************************************************************************/
335
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
336
reg TDOData;
337
 
338
 
339 36 mohor
always @ (posedge tck or posedge trst)
340 2 mohor
begin
341 18 mohor
  if(trst)
342 2 mohor
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
343
  else
344 30 mohor
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
345
    begin
346
      if(ShiftDR)
347 36 mohor
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
348 30 mohor
      else
349
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
350
    end
351
  else
352
  if(CHAIN_SELECTSelected & ShiftDR)
353 36 mohor
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
354 30 mohor
  else
355
  if(DEBUGSelected & ShiftDR)
356
    begin
357
      if(RiscDebugScanChain | WishboneScanChain)
358 36 mohor
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
359 30 mohor
      else
360
      if(RegisterScanChain)
361 36 mohor
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
362 30 mohor
    end
363 2 mohor
end
364 30 mohor
 
365 22 mohor
wire [73:0] RISC_Data;
366
wire [46:0] Register_Data;
367
wire [73:0] WISHBONE_Data;
368 21 mohor
wire [12:0] chain_sel_data;
369 12 mohor
wire wb_Access_wbClk;
370 2 mohor
 
371
 
372 30 mohor
reg select_crc_out;
373 36 mohor
always @ (posedge tck or posedge trst)
374 30 mohor
begin
375
  if(trst)
376
    select_crc_out <= 0;
377
  else
378
  if( RegisterScanChain  & BitCounter_Eq5  |
379
      RiscDebugScanChain & BitCounter_Eq32 |
380
      WishboneScanChain  & BitCounter_Eq32 )
381 36 mohor
    select_crc_out <=#Tp tdi;
382 30 mohor
  else
383
  if(CHAIN_SELECTSelected)
384
    select_crc_out <=#Tp 1;
385
  else
386
  if(UpdateDR)
387
    select_crc_out <=#Tp 0;
388
end
389 12 mohor
 
390 20 mohor
wire [8:0] send_crc;
391
 
392 30 mohor
assign send_crc = select_crc_out? {9{BypassRegister}}    :    // Calculated CRC is returned when read operation is
393
                                  {CalculatedCrcOut, 1'b0} ;  // performed, else received crc is returned (loopback).
394 20 mohor
 
395 30 mohor
assign RISC_Data      = {send_crc, DataReadLatch, 33'h0};
396
assign Register_Data  = {send_crc, DataReadLatch, 6'h0};
397 20 mohor
assign WISHBONE_Data  = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
398 21 mohor
assign chain_sel_data = {send_crc, 4'h0};
399 20 mohor
 
400
 
401
`ifdef TRACE_ENABLED
402 2 mohor
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
403
`endif
404
 
405 36 mohor
//TDO is changing on the falling edge of tck
406
always @ (negedge tck or posedge trst)
407 2 mohor
begin
408 18 mohor
  if(trst)
409 2 mohor
    begin
410
      TDOData <= #Tp 0;
411
      `ifdef TRACE_ENABLED
412
      ReadBuffer_Tck<=#Tp 0;
413
      `endif
414
    end
415
  else
416
  if(UpdateDR)
417
    begin
418
      TDOData <= #Tp CrcMatch;
419
      `ifdef TRACE_ENABLED
420 9 mohor
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
421
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
422 2 mohor
      `endif
423
    end
424
  else
425
    begin
426
      if(ShiftDR)
427
        begin
428
          if(IDCODESelected)
429 36 mohor
            TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
430 2 mohor
          else
431
          if(CHAIN_SELECTSelected)
432 21 mohor
            TDOData <= #Tp chain_sel_data[BitCounter];        // Received crc is sent back
433 2 mohor
          else
434
          if(DEBUGSelected)
435
            begin
436
              if(RiscDebugScanChain)
437 9 mohor
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
438 2 mohor
              else
439
              if(RegisterScanChain)
440 9 mohor
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
441 12 mohor
              else
442
              if(WishboneScanChain)
443
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
444 2 mohor
              `ifdef TRACE_ENABLED
445
              else
446
              if(TraceTestScanChain)
447 9 mohor
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
448 2 mohor
              `endif
449
            end
450
        end
451
      else
452
        begin
453
          TDOData <= #Tp 0;
454
          `ifdef TRACE_ENABLED
455
          ReadBuffer_Tck<=#Tp 0;
456
          `endif
457
        end
458
    end
459
end
460
 
461
/**********************************************************************************
462
*                                                                                 *
463
*   End: JTAG_DR                                                                  *
464
*                                                                                 *
465
**********************************************************************************/
466
 
467
 
468
 
469
/**********************************************************************************
470
*                                                                                 *
471
*   CHAIN_SELECT logic                                                            *
472
*                                                                                 *
473
**********************************************************************************/
474 36 mohor
always @ (posedge tck or posedge trst)
475 2 mohor
begin
476 18 mohor
  if(trst)
477 9 mohor
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
478 2 mohor
  else
479
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
480 9 mohor
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
481 2 mohor
end
482
 
483
 
484
 
485
/**********************************************************************************
486
*                                                                                 *
487
*   Register read/write logic                                                     *
488
*   RISC registers read/write logic                                               *
489
*                                                                                 *
490
**********************************************************************************/
491 36 mohor
always @ (posedge tck or posedge trst)
492 2 mohor
begin
493 18 mohor
  if(trst)
494 2 mohor
    begin
495
      ADDR[31:0]        <=#Tp 32'h0;
496
      DataOut[31:0]     <=#Tp 32'h0;
497
      RW                <=#Tp 1'b0;
498
      RegAccessTck      <=#Tp 1'b0;
499
      RISCAccessTck     <=#Tp 1'b0;
500 12 mohor
      wb_AccessTck      <=#Tp 1'h0;
501 2 mohor
    end
502
  else
503
  if(UpdateDR & DEBUGSelected & CrcMatch)
504
    begin
505
      if(RegisterScanChain)
506
        begin
507
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
508
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
509
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
510
          RegAccessTck      <=#Tp 1'b1;
511
        end
512
      else
513
      if(RiscDebugScanChain)
514
        begin
515
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
516
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
517
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
518
          RISCAccessTck     <=#Tp 1'b1;
519
        end
520 12 mohor
      else
521
      if(WishboneScanChain)
522
        begin
523 20 mohor
          ADDR              <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
524
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
525
          DataOut           <=#Tp JTAG_DR_IN[64:33];  // latch data for write
526 12 mohor
          wb_AccessTck      <=#Tp 1'b1;               // 
527
        end
528 2 mohor
    end
529
  else
530
    begin
531 36 mohor
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one tck clock period only
532 2 mohor
      RISCAccessTck     <=#Tp 1'b0;
533 12 mohor
      wb_AccessTck      <=#Tp 1'b0;
534 2 mohor
    end
535
end
536
 
537 20 mohor
 
538
assign wb_adr_o = ADDR;
539
assign wb_we_o  = RW;
540
assign wb_dat_o = DataOut;
541 12 mohor
assign wb_sel_o[3:0] = 4'hf;
542
assign wb_cab_o = 1'b0;
543 20 mohor
 
544
 
545 11 mohor
// Synchronizing the RegAccess signal to risc_clk_i clock
546 36 mohor
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(tck),           .reset1(wb_rst_i),  .reset2(trst),
547 2 mohor
                         .set2(RegAccessTck), .sync_out(RegAccess)
548
                        );
549
 
550 11 mohor
// Synchronizing the RISCAccess signal to risc_clk_i clock
551 36 mohor
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(tck),          .reset1(wb_rst_i),  .reset2(trst),
552 2 mohor
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
553
                        );
554
 
555
 
556 12 mohor
// Synchronizing the wb_Access signal to wishbone clock
557 36 mohor
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),     .clk2(tck),           .reset1(wb_rst_i),  .reset2(trst),
558 12 mohor
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
559
                        );
560
 
561
 
562
 
563
 
564
 
565 9 mohor
// Delayed signals used for accessing registers and RISC
566 18 mohor
always @ (posedge risc_clk_i or posedge wb_rst_i)
567 2 mohor
begin
568 18 mohor
  if(wb_rst_i)
569 2 mohor
    begin
570
      RegAccess_q   <=#Tp 1'b0;
571
      RegAccess_q2  <=#Tp 1'b0;
572
      RISCAccess_q  <=#Tp 1'b0;
573
      RISCAccess_q2 <=#Tp 1'b0;
574
    end
575
  else
576
    begin
577
      RegAccess_q   <=#Tp RegAccess;
578
      RegAccess_q2  <=#Tp RegAccess_q;
579
      RISCAccess_q  <=#Tp RISCAccess;
580
      RISCAccess_q2 <=#Tp RISCAccess_q;
581
    end
582
end
583
 
584 9 mohor
// Chip select and read/write signals for accessing RISC
585 11 mohor
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
586
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
587
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
588 2 mohor
 
589
 
590 12 mohor
reg wb_Access_wbClk_q;
591
// Delayed signals used for accessing WISHBONE
592 18 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
593 12 mohor
begin
594 18 mohor
  if(wb_rst_i)
595 12 mohor
    wb_Access_wbClk_q <=#Tp 1'b0;
596
  else
597
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
598
end
599
 
600 18 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
601 12 mohor
begin
602 18 mohor
  if(wb_rst_i)
603 12 mohor
    wb_cyc_o <=#Tp 1'b0;
604
  else
605
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
606
    wb_cyc_o <=#Tp 1'b1;
607
  else
608
  if(wb_ack_i | wb_err_i)
609
    wb_cyc_o <=#Tp 1'b0;
610
end
611
 
612
assign wb_stb_o = wb_cyc_o;
613
 
614
 
615
// Latching data read from registers
616 19 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
617 12 mohor
begin
618 18 mohor
  if(wb_rst_i)
619 12 mohor
    WBReadLatch[31:0]<=#Tp 32'h0;
620
  else
621
  if(wb_ack_i)
622
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
623
end
624
 
625
// Latching WISHBONE error cycle
626 18 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
627 12 mohor
begin
628 18 mohor
  if(wb_rst_i)
629 12 mohor
    WBErrorLatch<=#Tp 1'b0;
630
  else
631
  if(wb_err_i)
632
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
633 20 mohor
  else
634 12 mohor
  if(wb_ack_i)
635
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
636
end
637
 
638
 
639 9 mohor
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
640 5 mohor
`ifdef TRACE_ENABLED
641 11 mohor
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
642 5 mohor
`else
643 12 mohor
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
644 5 mohor
`endif
645
 
646 11 mohor
assign  reset_o = RiscReset_reg;
647 5 mohor
 
648
 
649 12 mohor
`ifdef TRACE_ENABLED
650 11 mohor
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
651 12 mohor
`else
652
always @ (RiscStall_write_access or RiscStall_read_access)
653
`endif
654 11 mohor
begin
655
  if(RiscStall_write_access)
656
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
657
  else
658
  if(RiscStall_read_access)
659
    opselect_o = `DEBUG_READ_SPR;   // Read spr
660
  else
661 12 mohor
`ifdef TRACE_ENABLED
662 11 mohor
    opselect_o = opselect_trace;
663 12 mohor
`else
664
    opselect_o = 3'h0;
665
`endif
666 11 mohor
end
667 9 mohor
 
668 11 mohor
 
669 30 mohor
// Latching data read from RISC or registers
670 18 mohor
always @ (posedge risc_clk_i or posedge wb_rst_i)
671 2 mohor
begin
672 18 mohor
  if(wb_rst_i)
673 30 mohor
    DataReadLatch[31:0]<=#Tp 0;
674 2 mohor
  else
675
  if(RISCAccess_q & ~RISCAccess_q2)
676 30 mohor
    DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
677
  else
678
  if(RegAccess_q & ~RegAccess_q2)
679
    DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
680 2 mohor
end
681
 
682 12 mohor
assign risc_addr_o = ADDR;
683
assign risc_data_o = DataOut;
684 2 mohor
 
685
 
686
 
687
/**********************************************************************************
688
*                                                                                 *
689
*   Read Trace buffer logic                                                       *
690
*                                                                                 *
691
**********************************************************************************/
692
`ifdef TRACE_ENABLED
693
 
694 9 mohor
 
695 11 mohor
// Synchronizing the trace read buffer signal to risc_clk_i clock
696 36 mohor
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(tck),           .reset1(wb_rst_i),  .reset2(trst),
697 9 mohor
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
698
                        );
699
 
700
 
701
 
702 18 mohor
  always @(posedge risc_clk_i or posedge wb_rst_i)
703 2 mohor
  begin
704 18 mohor
    if(wb_rst_i)
705 9 mohor
      ReadTraceBuffer_q <=#Tp 0;
706 2 mohor
    else
707 9 mohor
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
708 2 mohor
  end
709 9 mohor
 
710
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
711
 
712 2 mohor
`endif
713
 
714
/**********************************************************************************
715
*                                                                                 *
716
*   End: Read Trace buffer logic                                                  *
717
*                                                                                 *
718
**********************************************************************************/
719
 
720
 
721
 
722
 
723
 
724
/**********************************************************************************
725
*                                                                                 *
726
*   Bit counter                                                                   *
727
*                                                                                 *
728
**********************************************************************************/
729
 
730
 
731 36 mohor
always @ (posedge tck or posedge trst)
732 2 mohor
begin
733 18 mohor
  if(trst)
734 2 mohor
    BitCounter[7:0]<=#Tp 0;
735
  else
736
  if(ShiftDR)
737
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
738
  else
739
  if(UpdateDR)
740
    BitCounter[7:0]<=#Tp 0;
741
end
742
 
743
 
744
 
745
/**********************************************************************************
746
*                                                                                 *
747
*   End: Bit counter                                                              *
748
*                                                                                 *
749
**********************************************************************************/
750
 
751
 
752
 
753
/**********************************************************************************
754
*                                                                                 *
755
*   Connecting Registers                                                          *
756
*                                                                                 *
757
**********************************************************************************/
758
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
759 11 mohor
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
760 12 mohor
                      .Bp(bp_i), .Reset(wb_rst_i),
761 2 mohor
                      `ifdef TRACE_ENABLED
762 5 mohor
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
763 2 mohor
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
764
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
765
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
766 5 mohor
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
767
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
768
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
769
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
770
                      .WpTriggerValid(WpTriggerValid),
771 2 mohor
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
772
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
773
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
774
                      .IQualifValid(IQualifValid),
775
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
776 5 mohor
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
777
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
778 2 mohor
                      `endif
779 5 mohor
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
780
 
781 2 mohor
                     );
782
 
783
/**********************************************************************************
784
*                                                                                 *
785
*   End: Connecting Registers                                                     *
786
*                                                                                 *
787
**********************************************************************************/
788
 
789
 
790
/**********************************************************************************
791
*                                                                                 *
792
*   Connecting CRC module                                                         *
793
*                                                                                 *
794
**********************************************************************************/
795 18 mohor
wire AsyncResetCrc = trst;
796 9 mohor
wire SyncResetCrc = UpdateDR_q;
797 2 mohor
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
798
 
799 30 mohor
assign BitCounter_Lt4   = BitCounter<4;
800
assign BitCounter_Eq5   = BitCounter==5;
801
assign BitCounter_Eq32  = BitCounter==32;
802
assign BitCounter_Lt38  = BitCounter<38;
803
assign BitCounter_Lt65  = BitCounter<65;
804
 
805
`ifdef TRACE_ENABLED
806
  assign BitCounter_Lt40 = BitCounter<40;
807
`endif
808
 
809
 
810 2 mohor
wire EnableCrcIn = ShiftDR &
811 30 mohor
                  ( (CHAIN_SELECTSelected                 & BitCounter_Lt4) |
812
                    ((DEBUGSelected & RegisterScanChain)  & BitCounter_Lt38)|
813
                    ((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
814
                    ((DEBUGSelected & WishboneScanChain)  & BitCounter_Lt65)
815 9 mohor
                  );
816 2 mohor
 
817
wire EnableCrcOut= ShiftDR &
818 9 mohor
                   (
819 30 mohor
                    ((DEBUGSelected & RegisterScanChain)  & BitCounter_Lt38)|
820
                    ((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
821
                    ((DEBUGSelected & WishboneScanChain)  & BitCounter_Lt65)
822 2 mohor
                    `ifdef TRACE_ENABLED
823 30 mohor
                                                                            |
824
                    ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
825 2 mohor
                    `endif
826 9 mohor
                   );
827 2 mohor
 
828
// Calculating crc for input data
829 36 mohor
dbg_crc8_d1 crc1 (.Data(tdi), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
830
                  .CrcOut(CalculatedCrcIn), .Clk(tck));
831 2 mohor
 
832
// Calculating crc for output data
833 9 mohor
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
834 36 mohor
                  .CrcOut(CalculatedCrcOut), .Clk(tck));
835 2 mohor
 
836
 
837
// Generating CrcMatch signal
838 36 mohor
always @ (posedge tck or posedge trst)
839 2 mohor
begin
840 18 mohor
  if(trst)
841 2 mohor
    CrcMatch <=#Tp 1'b0;
842
  else
843
  if(Exit1DR)
844
    begin
845
      if(CHAIN_SELECTSelected)
846
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
847
      else
848 30 mohor
        begin
849
          if(RegisterScanChain)
850
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
851
          else
852
          if(RiscDebugScanChain)
853
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
854
          else
855
          if(WishboneScanChain)
856
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
857
        end
858 2 mohor
    end
859
end
860
 
861
 
862
// Active chain
863
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
864
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
865 12 mohor
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
866 2 mohor
 
867
`ifdef TRACE_ENABLED
868
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
869
`endif
870
 
871
/**********************************************************************************
872
*                                                                                 *
873
*   End: Connecting CRC module                                                    *
874
*                                                                                 *
875
**********************************************************************************/
876
 
877
/**********************************************************************************
878
*                                                                                 *
879
*   Connecting trace module                                                       *
880
*                                                                                 *
881
**********************************************************************************/
882
`ifdef TRACE_ENABLED
883 11 mohor
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
884 9 mohor
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
885 18 mohor
                      .Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
886 8 mohor
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
887 5 mohor
                      .WpTrigger(WpTrigger),
888 2 mohor
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
889
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
890
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
891 5 mohor
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
892
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
893
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
894
                      .RecordINSTR(RecordINSTR),
895 2 mohor
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
896
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
897
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
898
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
899 9 mohor
                      .ReadBuffer(ReadTraceBufferPulse),
900 2 mohor
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
901
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
902
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
903
                     );
904
`endif
905
/**********************************************************************************
906
*                                                                                 *
907
*   End: Connecting trace module                                                  *
908
*                                                                                 *
909
**********************************************************************************/
910
 
911
 
912
 
913 9 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.