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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Blame information for rev 42

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1 2 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  dbg_top.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the SoC/OpenRISC Development Interface ////
7 36 mohor
////  http://www.opencores.org/projects/DebugInterface/           ////
8 2 mohor
////                                                              ////
9
////                                                              ////
10
////  Author(s):                                                  ////
11
////       Igor Mohor                                             ////
12
////       igorm@opencores.org                                    ////
13
////                                                              ////
14
////                                                              ////
15
////  All additional information is avaliable in the README.txt   ////
16
////  file.                                                       ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000,2001 Authors                              ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48 42 mohor
// Revision 1.22  2002/03/12 10:31:53  mohor
49
// tap_top and dbg_top modules are put into two separate modules. tap_top
50
// contains only tap state machine and related logic. dbg_top contains all
51
// logic necessery for debugging.
52
//
53 37 mohor
// Revision 1.21  2002/03/08 15:28:16  mohor
54
// Structure changed. Hooks for jtag chain added.
55
//
56 36 mohor
// Revision 1.20  2002/02/06 12:23:09  mohor
57
// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
58
//
59 33 mohor
// Revision 1.19  2002/02/05 13:34:51  mohor
60
// Stupid bug that was entered by previous update fixed.
61
//
62 32 mohor
// Revision 1.18  2002/02/05 12:41:01  mohor
63
// trst synchronization is not needed and was removed.
64
//
65 31 mohor
// Revision 1.17  2002/01/25 07:58:35  mohor
66
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
67
// not filled-in. Tested in hw.
68
//
69 30 mohor
// Revision 1.16  2001/12/20 11:17:26  mohor
70
// TDO and TDO Enable signal are separated into two signals.
71
//
72 28 mohor
// Revision 1.15  2001/12/05 13:28:21  mohor
73
// trst signal is synchronized to wb_clk_i.
74
//
75 25 mohor
// Revision 1.14  2001/11/28 09:36:15  mohor
76
// Register length fixed.
77
//
78 22 mohor
// Revision 1.13  2001/11/27 13:37:43  mohor
79
// CRC is returned when chain selection data is transmitted.
80
//
81 21 mohor
// Revision 1.12  2001/11/26 10:47:09  mohor
82
// Crc generation is different for read or write commands. Small synthesys fixes.
83
//
84 20 mohor
// Revision 1.11  2001/11/14 10:10:41  mohor
85
// Wishbone data latched on wb_clk_i instead of risc_clk.
86
//
87 19 mohor
// Revision 1.10  2001/11/12 01:11:27  mohor
88
// Reset signals are not combined any more.
89
//
90 18 mohor
// Revision 1.9  2001/10/19 11:40:01  mohor
91
// dbg_timescale.v changed to timescale.v This is done for the simulation of
92
// few different cores in a single project.
93
//
94 17 mohor
// Revision 1.8  2001/10/17 10:39:03  mohor
95
// bs_chain_o added.
96
//
97 15 mohor
// Revision 1.7  2001/10/16 10:09:56  mohor
98
// Signal names changed to lowercase.
99 13 mohor
//
100 15 mohor
//
101 13 mohor
// Revision 1.6  2001/10/15 09:55:47  mohor
102
// Wishbone interface added, few fixes for better performance,
103
// hooks for boundary scan testing added.
104
//
105 12 mohor
// Revision 1.5  2001/09/24 14:06:42  mohor
106
// Changes connected to the OpenRISC access (SPR read, SPR write).
107
//
108 11 mohor
// Revision 1.4  2001/09/20 10:11:25  mohor
109
// Working version. Few bugs fixed, comments added.
110
//
111 9 mohor
// Revision 1.3  2001/09/19 11:55:13  mohor
112
// Asynchronous set/reset not used in trace any more.
113
//
114 8 mohor
// Revision 1.2  2001/09/18 14:13:47  mohor
115
// Trace fixed. Some registers changed, trace simplified.
116
//
117 5 mohor
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
118
// Initial official release.
119
//
120 2 mohor
// Revision 1.3  2001/06/01 22:22:35  mohor
121
// This is a backup. It is not a fully working version. Not for use, yet.
122
//
123
// Revision 1.2  2001/05/18 13:10:00  mohor
124
// Headers changed. All additional information is now avaliable in the README.txt file.
125
//
126
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
127
// Initial release
128
//
129
//
130
 
131 20 mohor
// synopsys translate_off
132 17 mohor
`include "timescale.v"
133 20 mohor
// synopsys translate_on
134 2 mohor
`include "dbg_defines.v"
135
 
136
// Top module
137 9 mohor
module dbg_top(
138
 
139
                // RISC signals
140 11 mohor
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
141
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
142 9 mohor
 
143 12 mohor
                // WISHBONE common signals
144
                wb_rst_i, wb_clk_i,
145
 
146
                // WISHBONE master interface
147
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
148 36 mohor
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
149 12 mohor
 
150 36 mohor
                // TAP states
151
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
152
 
153
                // Instructions
154
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
155
 
156
                // TAP signals
157 37 mohor
                trst_in, tck, tdi, TDOData,
158 36 mohor
 
159
                BypassRegister
160 37 mohor
 
161 2 mohor
              );
162
 
163
parameter Tp = 1;
164
 
165
 
166 9 mohor
// RISC signals
167 11 mohor
input         risc_clk_i;                 // Master clock (RISC clock)
168 9 mohor
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
169
input  [10:0] wp_i;                       // Watchpoint inputs
170
input         bp_i;                       // Breakpoint input
171
input  [3:0]  lsstatus_i;                 // Load/store status inputs
172
input  [1:0]  istatus_i;                  // Instruction status inputs
173
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
174
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
175
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
176
output                      risc_stall_o; // Stalls the RISC
177 11 mohor
output                      reset_o;      // Resets the RISC
178 2 mohor
 
179
 
180 12 mohor
// WISHBONE common signals
181 9 mohor
input         wb_rst_i;                   // WISHBONE reset
182 12 mohor
input         wb_clk_i;                   // WISHBONE clock
183 9 mohor
 
184 12 mohor
// WISHBONE master interface
185
output [31:0] wb_adr_o;
186
output [31:0] wb_dat_o;
187
input  [31:0] wb_dat_i;
188
output        wb_cyc_o;
189
output        wb_stb_o;
190
output  [3:0] wb_sel_o;
191
output        wb_we_o;
192
input         wb_ack_i;
193
output        wb_cab_o;
194
input         wb_err_i;
195 9 mohor
 
196
// TAP states
197 36 mohor
input         ShiftDR;
198
input         Exit1DR;
199
input         UpdateDR;
200
input         UpdateDR_q;
201 2 mohor
 
202 37 mohor
input trst_in;
203 36 mohor
input tck;
204
input tdi;
205 2 mohor
 
206 36 mohor
input BypassRegister;
207 9 mohor
 
208 36 mohor
output TDOData;
209
 
210
 
211 9 mohor
// Defining which instruction is selected
212 36 mohor
input         IDCODESelected;
213
input         CHAIN_SELECTSelected;
214
input         DEBUGSelected;
215 2 mohor
 
216 36 mohor
reg           wb_cyc_o;
217 9 mohor
 
218 36 mohor
reg [31:0]    ADDR;
219
reg [31:0]    DataOut;
220 11 mohor
 
221 36 mohor
reg [`OPSELECTWIDTH-1:0] opselect_o;        // Operation selection (selecting what kind of data is set to the risc_data_i)
222 2 mohor
 
223 36 mohor
reg [`CHAIN_ID_LENGTH-1:0] Chain;           // Selected chain
224
reg [31:0]    DataReadLatch;                // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
225
reg           RegAccessTck;                 // Indicates access to the registers (read or write)
226
reg           RISCAccessTck;                // Indicates access to the RISC (read or write)
227
reg [7:0]     BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
228
reg           RW;                           // Read/Write bit
229
reg           CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
230 2 mohor
 
231 36 mohor
reg           RegAccess_q;                  // Delayed signals used for accessing the registers
232
reg           RegAccess_q2;                 // Delayed signals used for accessing the registers
233
reg           RISCAccess_q;                 // Delayed signals used for accessing the RISC
234
reg           RISCAccess_q2;                // Delayed signals used for accessing the RISC
235 2 mohor
 
236 36 mohor
reg           wb_AccessTck;                 // Indicates access to the WISHBONE
237
reg [31:0]    WBReadLatch;                  // Data latched during WISHBONE read
238
reg           WBErrorLatch;                 // Error latched during WISHBONE read
239 30 mohor
 
240 37 mohor
wire trst;
241 30 mohor
 
242 37 mohor
 
243 9 mohor
wire [31:0]             RegDataIn;        // Data from registers (read data)
244
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
245 2 mohor
 
246 9 mohor
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
247
wire RiscReset_reg;                       // RISC is reset by setting the register bit
248
wire RiscStall_trace;                     // RISC is stalled by trace module
249
 
250
 
251
wire RegisterScanChain;                   // Register Scan chain selected
252
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
253 12 mohor
wire WishboneScanChain;                   // WISHBONE Scan chain selected
254 11 mohor
 
255
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
256
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
257
wire RiscStall_access;                    // Stalling RISC because of the read or write access
258
 
259 30 mohor
wire BitCounter_Lt4;
260
wire BitCounter_Eq5;
261
wire BitCounter_Eq32;
262
wire BitCounter_Lt38;
263
wire BitCounter_Lt65;
264
 
265 15 mohor
 
266
 
267 9 mohor
// This signals are used only when TRACE is used in the design
268 2 mohor
`ifdef TRACE_ENABLED
269 9 mohor
  wire [39:0] TraceChain;                 // Chain that comes from trace module
270 36 mohor
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with tck)
271 9 mohor
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
272
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
273
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
274 2 mohor
 
275
  // Outputs from registers
276 9 mohor
  wire ContinMode;                        // Trace working in continous mode
277
  wire TraceEnable;                       // Trace enabled
278 2 mohor
 
279 9 mohor
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
280
  wire        BpTrigger;                  // Breakpoint starts trigger
281
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
282
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
283
  wire [1:0]  TriggerOper;                // Trigger operation
284 2 mohor
 
285 9 mohor
  wire        WpTriggerValid;             // Watchpoint trigger is valid
286
  wire        BpTriggerValid;             // Breakpoint trigger is valid
287
  wire        LSSTriggerValid;            // Load/store status trigger is valid
288
  wire        ITriggerValid;              // Instruction status trigger is valid
289 2 mohor
 
290 9 mohor
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
291
  wire        BpQualif;                   // Breakpoint starts qualifier
292
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
293
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
294
  wire [1:0]  QualifOper;                 // Qualifier operation
295 2 mohor
 
296 9 mohor
  wire        WpQualifValid;              // Watchpoint qualifier is valid
297
  wire        BpQualifValid;              // Breakpoint qualifier is valid
298
  wire        LSSQualifValid;             // Load/store status qualifier is valid
299
  wire        IQualifValid;               // Instruction status qualifier is valid
300 2 mohor
 
301 9 mohor
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
302
  wire        BpStop;                     // Breakpoint stops recording of the trace
303
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
304
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
305
  wire [1:0]  StopOper;                   // Stop operation
306 2 mohor
 
307 9 mohor
  wire WpStopValid;                       // Watchpoint stop is valid
308
  wire BpStopValid;                       // Breakpoint stop is valid
309
  wire LSSStopValid;                      // Load/store status stop is valid
310
  wire IStopValid;                        // Instruction status stop is valid
311 2 mohor
 
312 9 mohor
  wire RecordPC;                          // Recording program counter
313
  wire RecordLSEA;                        // Recording load/store effective address
314
  wire RecordLDATA;                       // Recording load data
315
  wire RecordSDATA;                       // Recording store data
316
  wire RecordReadSPR;                     // Recording read SPR
317
  wire RecordWriteSPR;                    // Recording write SPR
318
  wire RecordINSTR;                       // Recording instruction
319 2 mohor
 
320
  // End: Outputs from registers
321
 
322 9 mohor
  wire TraceTestScanChain;                // Trace Test Scan chain selected
323
  wire [47:0] Trace_Data;                 // Trace data
324 2 mohor
 
325 11 mohor
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
326
                                          // data is set to the risc_data_i)
327 30 mohor
  wire BitCounter_Lt40;
328 11 mohor
 
329 2 mohor
`endif
330
 
331
 
332 37 mohor
assign trst = ~trst_in;                   // trst_pad_i is active low
333 25 mohor
 
334
 
335 2 mohor
/**********************************************************************************
336
*                                                                                 *
337
*   JTAG_DR:  JTAG Data Register                                                  *
338
*                                                                                 *
339
**********************************************************************************/
340
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
341
reg TDOData;
342
 
343
 
344 36 mohor
always @ (posedge tck or posedge trst)
345 2 mohor
begin
346 18 mohor
  if(trst)
347 2 mohor
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
348
  else
349 30 mohor
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
350
    begin
351
      if(ShiftDR)
352 36 mohor
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
353 30 mohor
      else
354
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
355
    end
356
  else
357
  if(CHAIN_SELECTSelected & ShiftDR)
358 36 mohor
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
359 30 mohor
  else
360
  if(DEBUGSelected & ShiftDR)
361
    begin
362
      if(RiscDebugScanChain | WishboneScanChain)
363 36 mohor
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
364 30 mohor
      else
365
      if(RegisterScanChain)
366 36 mohor
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
367 30 mohor
    end
368 2 mohor
end
369 30 mohor
 
370 22 mohor
wire [73:0] RISC_Data;
371
wire [46:0] Register_Data;
372
wire [73:0] WISHBONE_Data;
373 21 mohor
wire [12:0] chain_sel_data;
374 12 mohor
wire wb_Access_wbClk;
375 2 mohor
 
376
 
377 30 mohor
reg select_crc_out;
378 36 mohor
always @ (posedge tck or posedge trst)
379 30 mohor
begin
380
  if(trst)
381
    select_crc_out <= 0;
382
  else
383
  if( RegisterScanChain  & BitCounter_Eq5  |
384
      RiscDebugScanChain & BitCounter_Eq32 |
385
      WishboneScanChain  & BitCounter_Eq32 )
386 36 mohor
    select_crc_out <=#Tp tdi;
387 30 mohor
  else
388
  if(CHAIN_SELECTSelected)
389
    select_crc_out <=#Tp 1;
390
  else
391
  if(UpdateDR)
392
    select_crc_out <=#Tp 0;
393
end
394 12 mohor
 
395 20 mohor
wire [8:0] send_crc;
396
 
397 30 mohor
assign send_crc = select_crc_out? {9{BypassRegister}}    :    // Calculated CRC is returned when read operation is
398
                                  {CalculatedCrcOut, 1'b0} ;  // performed, else received crc is returned (loopback).
399 20 mohor
 
400 30 mohor
assign RISC_Data      = {send_crc, DataReadLatch, 33'h0};
401
assign Register_Data  = {send_crc, DataReadLatch, 6'h0};
402 20 mohor
assign WISHBONE_Data  = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
403 21 mohor
assign chain_sel_data = {send_crc, 4'h0};
404 20 mohor
 
405
 
406
`ifdef TRACE_ENABLED
407 2 mohor
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
408
`endif
409
 
410 36 mohor
//TDO is changing on the falling edge of tck
411
always @ (negedge tck or posedge trst)
412 2 mohor
begin
413 18 mohor
  if(trst)
414 2 mohor
    begin
415
      TDOData <= #Tp 0;
416
      `ifdef TRACE_ENABLED
417
      ReadBuffer_Tck<=#Tp 0;
418
      `endif
419
    end
420
  else
421
  if(UpdateDR)
422
    begin
423
      TDOData <= #Tp CrcMatch;
424
      `ifdef TRACE_ENABLED
425 9 mohor
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
426
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
427 2 mohor
      `endif
428
    end
429
  else
430
    begin
431
      if(ShiftDR)
432
        begin
433
          if(IDCODESelected)
434 36 mohor
            TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
435 2 mohor
          else
436
          if(CHAIN_SELECTSelected)
437 21 mohor
            TDOData <= #Tp chain_sel_data[BitCounter];        // Received crc is sent back
438 2 mohor
          else
439
          if(DEBUGSelected)
440
            begin
441
              if(RiscDebugScanChain)
442 9 mohor
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
443 2 mohor
              else
444
              if(RegisterScanChain)
445 9 mohor
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
446 12 mohor
              else
447
              if(WishboneScanChain)
448
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
449 2 mohor
              `ifdef TRACE_ENABLED
450
              else
451
              if(TraceTestScanChain)
452 9 mohor
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
453 2 mohor
              `endif
454
            end
455
        end
456
      else
457
        begin
458
          TDOData <= #Tp 0;
459
          `ifdef TRACE_ENABLED
460
          ReadBuffer_Tck<=#Tp 0;
461
          `endif
462
        end
463
    end
464
end
465
 
466 42 mohor
 
467
//synopsys translate_off
468
always @ (posedge tck)
469
begin
470
  if(ShiftDR & CHAIN_SELECTSelected & BitCounter > 12)
471
    begin
472
      $display("\n%m Error: BitCounter is bigger then chain_sel_data bits width[12:0]. BitCounter=%d\n",BitCounter);
473
      $stop;
474
    end
475
  else
476
  if(ShiftDR & DEBUGSelected)
477
    begin
478
      if(RiscDebugScanChain & BitCounter > 73)
479
        begin
480
          $display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
481
          $stop;
482
        end
483
      else
484
      if(RegisterScanChain & BitCounter > 45)
485
        begin
486
          $display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
487
          $stop;
488
        end
489
      else
490
      if(WishboneScanChain & BitCounter > 73)
491
        begin
492
          $display("\n%m Error: BitCounter is bigger then WISHBONE_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
493
          $stop;
494
        end
495
      `ifdef TRACE_ENABLED
496
      else
497
      if(TraceTestScanChain & BitCounter > 47)
498
        begin
499
          $display("\n%m Error: BitCounter is bigger then Trace_Data bits width[47:0]. BitCounter=%d\n",BitCounter);
500
          $stop;
501
        end
502
      `endif
503
    end
504
end
505
// synopsys translate_on
506
 
507
 
508
 
509
 
510
 
511
 
512
 
513
 
514 2 mohor
/**********************************************************************************
515
*                                                                                 *
516
*   End: JTAG_DR                                                                  *
517
*                                                                                 *
518
**********************************************************************************/
519
 
520
 
521
 
522
/**********************************************************************************
523
*                                                                                 *
524
*   CHAIN_SELECT logic                                                            *
525
*                                                                                 *
526
**********************************************************************************/
527 36 mohor
always @ (posedge tck or posedge trst)
528 2 mohor
begin
529 18 mohor
  if(trst)
530 9 mohor
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
531 2 mohor
  else
532
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
533 9 mohor
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
534 2 mohor
end
535
 
536
 
537
 
538
/**********************************************************************************
539
*                                                                                 *
540
*   Register read/write logic                                                     *
541
*   RISC registers read/write logic                                               *
542
*                                                                                 *
543
**********************************************************************************/
544 36 mohor
always @ (posedge tck or posedge trst)
545 2 mohor
begin
546 18 mohor
  if(trst)
547 2 mohor
    begin
548
      ADDR[31:0]        <=#Tp 32'h0;
549
      DataOut[31:0]     <=#Tp 32'h0;
550
      RW                <=#Tp 1'b0;
551
      RegAccessTck      <=#Tp 1'b0;
552
      RISCAccessTck     <=#Tp 1'b0;
553 12 mohor
      wb_AccessTck      <=#Tp 1'h0;
554 2 mohor
    end
555
  else
556
  if(UpdateDR & DEBUGSelected & CrcMatch)
557
    begin
558
      if(RegisterScanChain)
559
        begin
560
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
561
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
562
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
563
          RegAccessTck      <=#Tp 1'b1;
564
        end
565
      else
566
      if(RiscDebugScanChain)
567
        begin
568
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
569
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
570
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
571
          RISCAccessTck     <=#Tp 1'b1;
572
        end
573 12 mohor
      else
574
      if(WishboneScanChain)
575
        begin
576 20 mohor
          ADDR              <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
577
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
578
          DataOut           <=#Tp JTAG_DR_IN[64:33];  // latch data for write
579 12 mohor
          wb_AccessTck      <=#Tp 1'b1;               // 
580
        end
581 2 mohor
    end
582
  else
583
    begin
584 36 mohor
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one tck clock period only
585 2 mohor
      RISCAccessTck     <=#Tp 1'b0;
586 12 mohor
      wb_AccessTck      <=#Tp 1'b0;
587 2 mohor
    end
588
end
589
 
590 20 mohor
 
591
assign wb_adr_o = ADDR;
592
assign wb_we_o  = RW;
593
assign wb_dat_o = DataOut;
594 12 mohor
assign wb_sel_o[3:0] = 4'hf;
595
assign wb_cab_o = 1'b0;
596 20 mohor
 
597
 
598 11 mohor
// Synchronizing the RegAccess signal to risc_clk_i clock
599 36 mohor
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(tck),           .reset1(wb_rst_i),  .reset2(trst),
600 2 mohor
                         .set2(RegAccessTck), .sync_out(RegAccess)
601
                        );
602
 
603 11 mohor
// Synchronizing the RISCAccess signal to risc_clk_i clock
604 36 mohor
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(tck),          .reset1(wb_rst_i),  .reset2(trst),
605 2 mohor
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
606
                        );
607
 
608
 
609 12 mohor
// Synchronizing the wb_Access signal to wishbone clock
610 36 mohor
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),     .clk2(tck),           .reset1(wb_rst_i),  .reset2(trst),
611 12 mohor
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
612
                        );
613
 
614
 
615
 
616
 
617
 
618 9 mohor
// Delayed signals used for accessing registers and RISC
619 18 mohor
always @ (posedge risc_clk_i or posedge wb_rst_i)
620 2 mohor
begin
621 18 mohor
  if(wb_rst_i)
622 2 mohor
    begin
623
      RegAccess_q   <=#Tp 1'b0;
624
      RegAccess_q2  <=#Tp 1'b0;
625
      RISCAccess_q  <=#Tp 1'b0;
626
      RISCAccess_q2 <=#Tp 1'b0;
627
    end
628
  else
629
    begin
630
      RegAccess_q   <=#Tp RegAccess;
631
      RegAccess_q2  <=#Tp RegAccess_q;
632
      RISCAccess_q  <=#Tp RISCAccess;
633
      RISCAccess_q2 <=#Tp RISCAccess_q;
634
    end
635
end
636
 
637 9 mohor
// Chip select and read/write signals for accessing RISC
638 11 mohor
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
639
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
640
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
641 2 mohor
 
642
 
643 12 mohor
reg wb_Access_wbClk_q;
644
// Delayed signals used for accessing WISHBONE
645 18 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
646 12 mohor
begin
647 18 mohor
  if(wb_rst_i)
648 12 mohor
    wb_Access_wbClk_q <=#Tp 1'b0;
649
  else
650
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
651
end
652
 
653 18 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
654 12 mohor
begin
655 18 mohor
  if(wb_rst_i)
656 12 mohor
    wb_cyc_o <=#Tp 1'b0;
657
  else
658
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
659
    wb_cyc_o <=#Tp 1'b1;
660
  else
661
  if(wb_ack_i | wb_err_i)
662
    wb_cyc_o <=#Tp 1'b0;
663
end
664
 
665
assign wb_stb_o = wb_cyc_o;
666
 
667
 
668
// Latching data read from registers
669 19 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
670 12 mohor
begin
671 18 mohor
  if(wb_rst_i)
672 12 mohor
    WBReadLatch[31:0]<=#Tp 32'h0;
673
  else
674
  if(wb_ack_i)
675
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
676
end
677
 
678
// Latching WISHBONE error cycle
679 18 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
680 12 mohor
begin
681 18 mohor
  if(wb_rst_i)
682 12 mohor
    WBErrorLatch<=#Tp 1'b0;
683
  else
684
  if(wb_err_i)
685
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
686 20 mohor
  else
687 12 mohor
  if(wb_ack_i)
688
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
689
end
690
 
691
 
692 9 mohor
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
693 5 mohor
`ifdef TRACE_ENABLED
694 11 mohor
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
695 5 mohor
`else
696 12 mohor
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
697 5 mohor
`endif
698
 
699 11 mohor
assign  reset_o = RiscReset_reg;
700 5 mohor
 
701
 
702 12 mohor
`ifdef TRACE_ENABLED
703 11 mohor
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
704 12 mohor
`else
705
always @ (RiscStall_write_access or RiscStall_read_access)
706
`endif
707 11 mohor
begin
708
  if(RiscStall_write_access)
709
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
710
  else
711
  if(RiscStall_read_access)
712
    opselect_o = `DEBUG_READ_SPR;   // Read spr
713
  else
714 12 mohor
`ifdef TRACE_ENABLED
715 11 mohor
    opselect_o = opselect_trace;
716 12 mohor
`else
717
    opselect_o = 3'h0;
718
`endif
719 11 mohor
end
720 9 mohor
 
721 11 mohor
 
722 30 mohor
// Latching data read from RISC or registers
723 18 mohor
always @ (posedge risc_clk_i or posedge wb_rst_i)
724 2 mohor
begin
725 18 mohor
  if(wb_rst_i)
726 30 mohor
    DataReadLatch[31:0]<=#Tp 0;
727 2 mohor
  else
728
  if(RISCAccess_q & ~RISCAccess_q2)
729 30 mohor
    DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
730
  else
731
  if(RegAccess_q & ~RegAccess_q2)
732
    DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
733 2 mohor
end
734
 
735 12 mohor
assign risc_addr_o = ADDR;
736
assign risc_data_o = DataOut;
737 2 mohor
 
738
 
739
 
740
/**********************************************************************************
741
*                                                                                 *
742
*   Read Trace buffer logic                                                       *
743
*                                                                                 *
744
**********************************************************************************/
745
`ifdef TRACE_ENABLED
746
 
747 9 mohor
 
748 11 mohor
// Synchronizing the trace read buffer signal to risc_clk_i clock
749 36 mohor
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(tck),           .reset1(wb_rst_i),  .reset2(trst),
750 9 mohor
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
751
                        );
752
 
753
 
754
 
755 18 mohor
  always @(posedge risc_clk_i or posedge wb_rst_i)
756 2 mohor
  begin
757 18 mohor
    if(wb_rst_i)
758 9 mohor
      ReadTraceBuffer_q <=#Tp 0;
759 2 mohor
    else
760 9 mohor
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
761 2 mohor
  end
762 9 mohor
 
763
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
764
 
765 2 mohor
`endif
766
 
767
/**********************************************************************************
768
*                                                                                 *
769
*   End: Read Trace buffer logic                                                  *
770
*                                                                                 *
771
**********************************************************************************/
772
 
773
 
774
 
775
 
776
 
777
/**********************************************************************************
778
*                                                                                 *
779
*   Bit counter                                                                   *
780
*                                                                                 *
781
**********************************************************************************/
782
 
783
 
784 36 mohor
always @ (posedge tck or posedge trst)
785 2 mohor
begin
786 18 mohor
  if(trst)
787 2 mohor
    BitCounter[7:0]<=#Tp 0;
788
  else
789
  if(ShiftDR)
790
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
791
  else
792
  if(UpdateDR)
793
    BitCounter[7:0]<=#Tp 0;
794
end
795
 
796
 
797
 
798
/**********************************************************************************
799
*                                                                                 *
800
*   End: Bit counter                                                              *
801
*                                                                                 *
802
**********************************************************************************/
803
 
804
 
805
 
806
/**********************************************************************************
807
*                                                                                 *
808
*   Connecting Registers                                                          *
809
*                                                                                 *
810
**********************************************************************************/
811
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
812 11 mohor
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
813 12 mohor
                      .Bp(bp_i), .Reset(wb_rst_i),
814 2 mohor
                      `ifdef TRACE_ENABLED
815 5 mohor
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
816 2 mohor
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
817
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
818
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
819 5 mohor
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
820
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
821
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
822
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
823
                      .WpTriggerValid(WpTriggerValid),
824 2 mohor
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
825
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
826
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
827
                      .IQualifValid(IQualifValid),
828
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
829 5 mohor
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
830
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
831 2 mohor
                      `endif
832 5 mohor
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
833
 
834 2 mohor
                     );
835
 
836
/**********************************************************************************
837
*                                                                                 *
838
*   End: Connecting Registers                                                     *
839
*                                                                                 *
840
**********************************************************************************/
841
 
842
 
843
/**********************************************************************************
844
*                                                                                 *
845
*   Connecting CRC module                                                         *
846
*                                                                                 *
847
**********************************************************************************/
848 18 mohor
wire AsyncResetCrc = trst;
849 9 mohor
wire SyncResetCrc = UpdateDR_q;
850 2 mohor
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
851
 
852 30 mohor
assign BitCounter_Lt4   = BitCounter<4;
853
assign BitCounter_Eq5   = BitCounter==5;
854
assign BitCounter_Eq32  = BitCounter==32;
855
assign BitCounter_Lt38  = BitCounter<38;
856
assign BitCounter_Lt65  = BitCounter<65;
857
 
858
`ifdef TRACE_ENABLED
859
  assign BitCounter_Lt40 = BitCounter<40;
860
`endif
861
 
862
 
863 2 mohor
wire EnableCrcIn = ShiftDR &
864 30 mohor
                  ( (CHAIN_SELECTSelected                 & BitCounter_Lt4) |
865
                    ((DEBUGSelected & RegisterScanChain)  & BitCounter_Lt38)|
866
                    ((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
867
                    ((DEBUGSelected & WishboneScanChain)  & BitCounter_Lt65)
868 9 mohor
                  );
869 2 mohor
 
870
wire EnableCrcOut= ShiftDR &
871 9 mohor
                   (
872 30 mohor
                    ((DEBUGSelected & RegisterScanChain)  & BitCounter_Lt38)|
873
                    ((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
874
                    ((DEBUGSelected & WishboneScanChain)  & BitCounter_Lt65)
875 2 mohor
                    `ifdef TRACE_ENABLED
876 30 mohor
                                                                            |
877
                    ((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
878 2 mohor
                    `endif
879 9 mohor
                   );
880 2 mohor
 
881
// Calculating crc for input data
882 36 mohor
dbg_crc8_d1 crc1 (.Data(tdi), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
883
                  .CrcOut(CalculatedCrcIn), .Clk(tck));
884 2 mohor
 
885
// Calculating crc for output data
886 9 mohor
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
887 36 mohor
                  .CrcOut(CalculatedCrcOut), .Clk(tck));
888 2 mohor
 
889
 
890
// Generating CrcMatch signal
891 36 mohor
always @ (posedge tck or posedge trst)
892 2 mohor
begin
893 18 mohor
  if(trst)
894 2 mohor
    CrcMatch <=#Tp 1'b0;
895
  else
896
  if(Exit1DR)
897
    begin
898
      if(CHAIN_SELECTSelected)
899
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
900
      else
901 30 mohor
        begin
902
          if(RegisterScanChain)
903
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
904
          else
905
          if(RiscDebugScanChain)
906
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
907
          else
908
          if(WishboneScanChain)
909
            CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
910
        end
911 2 mohor
    end
912
end
913
 
914
 
915
// Active chain
916
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
917
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
918 12 mohor
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
919 2 mohor
 
920
`ifdef TRACE_ENABLED
921
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
922
`endif
923
 
924
/**********************************************************************************
925
*                                                                                 *
926
*   End: Connecting CRC module                                                    *
927
*                                                                                 *
928
**********************************************************************************/
929
 
930
/**********************************************************************************
931
*                                                                                 *
932
*   Connecting trace module                                                       *
933
*                                                                                 *
934
**********************************************************************************/
935
`ifdef TRACE_ENABLED
936 11 mohor
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
937 9 mohor
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
938 18 mohor
                      .Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
939 8 mohor
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
940 5 mohor
                      .WpTrigger(WpTrigger),
941 2 mohor
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
942
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
943
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
944 5 mohor
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
945
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
946
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
947
                      .RecordINSTR(RecordINSTR),
948 2 mohor
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
949
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
950
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
951
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
952 9 mohor
                      .ReadBuffer(ReadTraceBufferPulse),
953 2 mohor
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
954
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
955
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
956
                     );
957
`endif
958
/**********************************************************************************
959
*                                                                                 *
960
*   End: Connecting trace module                                                  *
961
*                                                                                 *
962
**********************************************************************************/
963
 
964
 
965
 
966 9 mohor
endmodule

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