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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_trace.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_trace.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:06  mohor
// Initial release
//
//
 
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, CpuStall,
                  Mclk, Reset, TraceChain, ContinMode, TraceEnable, RecSelDepend,
                  WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
                  BpQualif, LSSQualif, IQualif, QualifOper, RecordPC_Wp, RecordLSEA_Wp,
                  RecordLDATA_Wp, RecordSDATA_Wp, RecordReadSPR_Wp, RecordWriteSPR_Wp,
                  RecordINSTR_Wp, RecordPC_Bp, RecordLSEA_Bp, RecordLDATA_Bp,
                  RecordSDATA_Bp, RecordReadSPR_Bp, RecordWriteSPR_Bp, RecordINSTR_Bp,
                  WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
                  WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
                  WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
                  LSSStopValid, IStopValid
                 );
 
parameter Tp = 1;
 
 
input [10:0] Wp;        // Watchpoints
input        Bp;        // Breakpoint
input [31:0] DataIn;    // Data from the RISC
input [3:0]  LsStatus;  // Load/Store status
input [1:0]  IStatus;   // Instruction status
 
input        Mclk;      // Master clock (RISC clock)
input        Reset;     // Reset
input        ReadBuffer;// Instruction for reading a sample from the Buffer
 
// from registers
input ContinMode;
input TraceEnable;
input RecSelDepend;
 
input [10:0] WpTrigger;
input        BpTrigger;
input [3:0]  LSSTrigger;
input [1:0]  ITrigger;
input [1:0]  TriggerOper;
 
input [10:0] WpQualif;
input        BpQualif;
input [3:0]  LSSQualif;
input [1:0]  IQualif;
input [1:0]  QualifOper;
 
input [10:0] WpStop;
input        BpStop;
input [3:0]  LSSStop;
input [1:0]  IStop;
input [1:0]  StopOper;
 
input [10:0] RecordPC_Wp;
input [10:0] RecordLSEA_Wp;
input [10:0] RecordLDATA_Wp;
input [10:0] RecordSDATA_Wp;
input [10:0] RecordReadSPR_Wp;
input [10:0] RecordWriteSPR_Wp;
input [10:0] RecordINSTR_Wp;
 
input RecordPC_Bp;
input RecordLSEA_Bp;
input RecordLDATA_Bp;
input RecordSDATA_Bp;
input RecordReadSPR_Bp;
input RecordWriteSPR_Bp;
input RecordINSTR_Bp;
 
input WpTriggerValid;
input BpTriggerValid;
input LSSTriggerValid;
input ITriggerValid;
 
input WpQualifValid;
input BpQualifValid;
input LSSQualifValid;
input IQualifValid;
 
input WpStopValid;
input BpStopValid;
input LSSStopValid;
input IStopValid;
// end: from registers
 
 
output [`OPSELECTWIDTH-1:0]  OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
output        CpuStall;   // CPU stall (stalls the RISC)
output [39:0] TraceChain; // Scan shain from the trace module
 
 
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg CpuStall;
reg CpuStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
 
reg TriggerLatch;
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the trigger                                                     *
*                                                                                 *
**********************************************************************************/
wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
wire TempBpTrigger = Bp & BpTrigger;
wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
 
wire TempTriggerAND =  (  (TempWpTrigger  | ~WpTriggerValid)
                        & (TempBpTrigger  | ~BpTriggerValid)
                        & (TempLSSTrigger | ~LSSTriggerValid)
                        & (TempITrigger   | ~ITriggerValid)
                       )
                       & (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
 
wire TempTriggerOR =   (  (TempWpTrigger  &  WpTriggerValid)
                        | (TempBpTrigger  &  BpTriggerValid)
                        | (TempLSSTrigger &  LSSTriggerValid)
                        | (TempITrigger   &  ITriggerValid)
                       );
 
wire Trigger = TraceEnable & (~TriggerOper[1]?  1 :                               // any
                               TriggerOper[0]?  TempTriggerAND : TempTriggerOR    // AND : OR
                             );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the qualifier                                                   *
*                                                                                 *
**********************************************************************************/
wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
wire TempBpQualifier = Bp & BpQualif;
wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
 
wire TempQualifierAND =  (  (TempWpQualifier  | ~WpQualifValid)
                          & (TempBpQualifier  | ~BpQualifValid)
                          & (TempLSSQualifier | ~LSSQualifValid)
                          & (TempIQualifier   | ~IQualifValid)
                         )
                         & (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
 
wire TempQualifierOR =   (  (TempWpQualifier  &  WpQualifValid)
                          | (TempBpQualifier  &  BpQualifValid)
                          | (TempLSSQualifier &  LSSQualifValid)
                          | (TempIQualifier   &  IQualifValid)
                         );
 
 
wire Stop;
wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 :                                   // any
                                         QualifOper[0]? TempQualifierAND  :  TempQualifierOR  // AND : OR
                                       );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the stop signal                                                 *
*                                                                                 *
**********************************************************************************/
wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
wire TempBpStop = Bp & BpStop;
wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
wire TempIStop = IStatus[1:0] == IStop[1:0];
 
wire TempStopAND =  (  (TempWpStop  | ~WpStopValid)
                          & (TempBpStop  | ~BpStopValid)
                          & (TempLSSStop | ~LSSStopValid)
                          & (TempIStop   | ~IStopValid)
                         )
                         & (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
 
wire TempStopOR =   (  (TempWpStop  &  WpStopValid)
                          | (TempBpStop  &  BpStopValid)
                          | (TempLSSStop &  LSSStopValid)
                          | (TempIStop   &  IStopValid)
                         );
 
 
assign Stop = TraceEnable & (~StopOper[1]? 0 :                         // nothing
                              StopOper[0]? TempStopAND  :  TempStopOR  // AND : OR
                            );
 
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the TriggerLatch                                                *
*                                                                                 *
**********************************************************************************/
wire Reset_TriggerLatch = Reset | TriggerLatch & ~TraceEnable;
always @(posedge Mclk or posedge Reset_TriggerLatch)
begin
  if(Reset_TriggerLatch)
    TriggerLatch<=#Tp 0;
  else
  if(Trigger)
    TriggerLatch<=#Tp 1;
end
 
 
/**********************************************************************************
*                                                                                 *
*   CpuStall, counter and pointers generation                                     *
*                                                                                 *
**********************************************************************************/
reg BufferFullDetected;
reg [`OPSELECTIONCOUNTER-1:0] RecEnable;
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = CpuStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = CpuStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
wire CounterEn = IncrementCounter ^ Decrement;
 
wire ResetCpuStall;
wire ResetStallCounter;
reg BufferFull_q;
reg BufferFull_2q;
 
reg Qualifier_mclk;
 
always @(posedge Mclk)
begin
  Qualifier_mclk<=#Tp Qualifier;
  BufferFull_q<=#Tp BufferFull;
  BufferFull_2q<=#Tp BufferFull_q;
  CpuStall_q <=#Tp CpuStall;
end
 
 
wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch | Qualifier_mclk & Trigger & ~TriggerLatch |
                        Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
 
 
wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
                       (
                        (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                        (~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0)                   |
                        ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
                       );
 
assign ResetCpuStall = (
                        (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
                        (~ContinMode &  ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                        ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
                       ) | Reset;
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    Counter<=#Tp 0;
  else
  if(CounterEn)
    if(IncrementCounter)
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
    else
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    begin
      WritePointer<=#Tp 0;
      ReadPointer<=#Tp 0;
    end
  else
    begin
      if(IncrementPointer)
        WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
      // else igor !!! Probably else is missing here. Check it.
      if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
        ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
      else
      if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
        ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
    end
end
 
always @(posedge Mclk)
begin
  if(~TraceEnable)
    BufferFullDetected<=#Tp 0;
  else
  if(ContinMode & BufferFull)
    BufferFullDetected<=#Tp 1;
end
 
 
always @(posedge Mclk or posedge AsyncSetCpuStall)
begin
  if(AsyncSetCpuStall)
    CpuStall<=#Tp 1;
  else
  if(SyncSetCpuStall)
    CpuStall<=#Tp 1;
  else
  if(ResetCpuStall)
    CpuStall<=#Tp 0;
end
 
 
always @(posedge Mclk)
begin
  if(ResetStallCounter)
    StallCounter<=#Tp 0;
  else
  if(CpuStall_q & (~BufferFull | ContinMode))
    StallCounter<=#Tp StallCounter+1;
end
 
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
 
 
/**********************************************************************************
*                                                                                 *
*   Valid status                                                                  *
*                                                                                 *
**********************************************************************************/
wire Valid = ~BufferEmpty;
 
 
/**********************************************************************************
*                                                                                 *
*   Writing and reading the sample to/from the buffer                             *
*                                                                                 *
**********************************************************************************/
always @ (posedge Mclk)
begin
  if(WriteSample)
    Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
end
 
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
 
 
 
/**********************************************************************************
*                                                                                 *
*   Operation select (to select which kind of data appears on the DATAIN lines)   *
*                                                                                 *
**********************************************************************************/
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
 
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting which parts are going to be recorded as part of the sample          *
*                                                                                 *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    RecEnable<=#Tp 0;
  else
  if(CpuStall)
    begin
      RecEnable<=#Tp {1'b0, RecordINSTR_Wp[0],  RecordWriteSPR_Wp[0],  RecordReadSPR_Wp[0],  RecordSDATA_Wp[0],  RecordLDATA_Wp[0],  RecordLSEA_Wp[0],  RecordPC_Wp[0]} & {`OPSELECTIONCOUNTER{Wp[0]}}   |
                     {1'b0, RecordINSTR_Wp[1],  RecordWriteSPR_Wp[1],  RecordReadSPR_Wp[1],  RecordSDATA_Wp[1],  RecordLDATA_Wp[1],  RecordLSEA_Wp[1],  RecordPC_Wp[1]} & {`OPSELECTIONCOUNTER{Wp[1]}}   |
                     {1'b0, RecordINSTR_Wp[2],  RecordWriteSPR_Wp[2],  RecordReadSPR_Wp[2],  RecordSDATA_Wp[2],  RecordLDATA_Wp[2],  RecordLSEA_Wp[2],  RecordPC_Wp[2]} & {`OPSELECTIONCOUNTER{Wp[2]}}   |
                     {1'b0, RecordINSTR_Wp[3],  RecordWriteSPR_Wp[3],  RecordReadSPR_Wp[3],  RecordSDATA_Wp[3],  RecordLDATA_Wp[3],  RecordLSEA_Wp[3],  RecordPC_Wp[3]} & {`OPSELECTIONCOUNTER{Wp[3]}}   |
                     {1'b0, RecordINSTR_Wp[4],  RecordWriteSPR_Wp[4],  RecordReadSPR_Wp[4],  RecordSDATA_Wp[4],  RecordLDATA_Wp[4],  RecordLSEA_Wp[4],  RecordPC_Wp[4]} & {`OPSELECTIONCOUNTER{Wp[4]}}   |
                     {1'b0, RecordINSTR_Wp[5],  RecordWriteSPR_Wp[5],  RecordReadSPR_Wp[5],  RecordSDATA_Wp[5],  RecordLDATA_Wp[5],  RecordLSEA_Wp[5],  RecordPC_Wp[5]} & {`OPSELECTIONCOUNTER{Wp[5]}}   |
                     {1'b0, RecordINSTR_Wp[6],  RecordWriteSPR_Wp[6],  RecordReadSPR_Wp[6],  RecordSDATA_Wp[6],  RecordLDATA_Wp[6],  RecordLSEA_Wp[6],  RecordPC_Wp[6]} & {`OPSELECTIONCOUNTER{Wp[6]}}   |
                     {1'b0, RecordINSTR_Wp[7],  RecordWriteSPR_Wp[7],  RecordReadSPR_Wp[7],  RecordSDATA_Wp[7],  RecordLDATA_Wp[7],  RecordLSEA_Wp[7],  RecordPC_Wp[7]} & {`OPSELECTIONCOUNTER{Wp[7]}}   |
                     {1'b0, RecordINSTR_Wp[8],  RecordWriteSPR_Wp[8],  RecordReadSPR_Wp[8],  RecordSDATA_Wp[8],  RecordLDATA_Wp[8],  RecordLSEA_Wp[8],  RecordPC_Wp[8]} & {`OPSELECTIONCOUNTER{Wp[8]}}   |
                     {1'b0, RecordINSTR_Wp[9],  RecordWriteSPR_Wp[9],  RecordReadSPR_Wp[9],  RecordSDATA_Wp[9],  RecordLDATA_Wp[9],  RecordLSEA_Wp[9],  RecordPC_Wp[9]} & {`OPSELECTIONCOUNTER{Wp[9]}}   |
                     {1'b0, RecordINSTR_Wp[10], RecordWriteSPR_Wp[10], RecordReadSPR_Wp[10], RecordSDATA_Wp[10], RecordLDATA_Wp[10], RecordLSEA_Wp[10], RecordPC_Wp[10]}& {`OPSELECTIONCOUNTER{Wp[10]}}  |
                     {1'b0, RecordINSTR_Bp,     RecordWriteSPR_Bp,     RecordReadSPR_Bp,     RecordSDATA_Bp,     RecordLDATA_Bp,     RecordLSEA_Bp,     RecordPC_Bp}    & {`OPSELECTIONCOUNTER{Bp}};
    end
end
 
 
endmodule // Trace

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_trace.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_trace.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.3 2001/06/01 22:22:35 mohor`
49			`// This is a backup. It is not a fully working version. Not for use, yet.`
50			`//`
51			`// Revision 1.2 2001/05/18 13:10:00 mohor`
52			`// Headers changed. All additional information is now avaliable in the README.txt file.`
53			`//`
54			`// Revision 1.1.1.1 2001/05/18 06:35:06 mohor`
55			`// Initial release`
56			`//`
57			`//`
58
59
60			`include "dbg_timescale.v"
61			`include "dbg_defines.v"
62
63			`// module Trace`
64			`module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, CpuStall,`
65			`Mclk, Reset, TraceChain, ContinMode, TraceEnable, RecSelDepend,`
66			`WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,`
67			`BpQualif, LSSQualif, IQualif, QualifOper, RecordPC_Wp, RecordLSEA_Wp,`
68			`RecordLDATA_Wp, RecordSDATA_Wp, RecordReadSPR_Wp, RecordWriteSPR_Wp,`
69			`RecordINSTR_Wp, RecordPC_Bp, RecordLSEA_Bp, RecordLDATA_Bp,`
70			`RecordSDATA_Bp, RecordReadSPR_Bp, RecordWriteSPR_Bp, RecordINSTR_Bp,`
71			`WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,`
72			`WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,`
73			`WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,`
74			`LSSStopValid, IStopValid`
75			`);`
76
77			`parameter Tp = 1;`
78
79
80			`input [10:0] Wp; // Watchpoints`
81			`input Bp; // Breakpoint`
82			`input [31:0] DataIn; // Data from the RISC`
83			`input [3:0] LsStatus; // Load/Store status`
84			`input [1:0] IStatus; // Instruction status`
85
86			`input Mclk; // Master clock (RISC clock)`
87			`input Reset; // Reset`
88			`input ReadBuffer;// Instruction for reading a sample from the Buffer`
89
90			`// from registers`
91			`input ContinMode;`
92			`input TraceEnable;`
93			`input RecSelDepend;`
94
95			`input [10:0] WpTrigger;`
96			`input BpTrigger;`
97			`input [3:0] LSSTrigger;`
98			`input [1:0] ITrigger;`
99			`input [1:0] TriggerOper;`
100
101			`input [10:0] WpQualif;`
102			`input BpQualif;`
103			`input [3:0] LSSQualif;`
104			`input [1:0] IQualif;`
105			`input [1:0] QualifOper;`
106
107			`input [10:0] WpStop;`
108			`input BpStop;`
109			`input [3:0] LSSStop;`
110			`input [1:0] IStop;`
111			`input [1:0] StopOper;`
112
113			`input [10:0] RecordPC_Wp;`
114			`input [10:0] RecordLSEA_Wp;`
115			`input [10:0] RecordLDATA_Wp;`
116			`input [10:0] RecordSDATA_Wp;`
117			`input [10:0] RecordReadSPR_Wp;`
118			`input [10:0] RecordWriteSPR_Wp;`
119			`input [10:0] RecordINSTR_Wp;`
120
121			`input RecordPC_Bp;`
122			`input RecordLSEA_Bp;`
123			`input RecordLDATA_Bp;`
124			`input RecordSDATA_Bp;`
125			`input RecordReadSPR_Bp;`
126			`input RecordWriteSPR_Bp;`
127			`input RecordINSTR_Bp;`
128
129			`input WpTriggerValid;`
130			`input BpTriggerValid;`
131			`input LSSTriggerValid;`
132			`input ITriggerValid;`
133
134			`input WpQualifValid;`
135			`input BpQualifValid;`
136			`input LSSQualifValid;`
137			`input IQualifValid;`
138
139			`input WpStopValid;`
140			`input BpStopValid;`
141			`input LSSStopValid;`
142			`input IStopValid;`
143			`// end: from registers`
144
145
146			output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
147			`output CpuStall; // CPU stall (stalls the RISC)`
148			`output [39:0] TraceChain; // Scan shain from the trace module`
149
150
151			reg [`TRACECOUNTERWIDTH:0] Counter;
152			reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
153			reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
154			`reg CpuStall;`
155			`reg CpuStall_q;`
156			reg [`OPSELECTWIDTH-1:0] StallCounter;
157
158			reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
159
160			`reg TriggerLatch;`
161
162
163			`/**********************************************************************************`
164			`* *`
165			`* Generation of the trigger *`
166			`* *`
167			`**********************************************************************************/`
168			`wire TempWpTrigger = \|(Wp[10:0] & WpTrigger[10:0]);`
169			`wire TempBpTrigger = Bp & BpTrigger;`
170			`wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];`
171			`wire TempITrigger = IStatus[1:0] == ITrigger[1:0];`
172
173			`wire TempTriggerAND = ( (TempWpTrigger \| ~WpTriggerValid)`
174			`& (TempBpTrigger \| ~BpTriggerValid)`
175			`& (TempLSSTrigger \| ~LSSTriggerValid)`
176			`& (TempITrigger \| ~ITriggerValid)`
177			`)`
178			`& (WpTriggerValid \| BpTriggerValid \| LSSTriggerValid \| ITriggerValid);`
179
180			`wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)`
181			`\| (TempBpTrigger & BpTriggerValid)`
182			`\| (TempLSSTrigger & LSSTriggerValid)`
183			`\| (TempITrigger & ITriggerValid)`
184			`);`
185
186			`wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any`
187			`TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR`
188			`);`
189
190			`/**********************************************************************************`
191			`* *`
192			`* Generation of the qualifier *`
193			`* *`
194			`**********************************************************************************/`
195			`wire TempWpQualifier = \|(Wp[10:0] & WpQualif[10:0]);`
196			`wire TempBpQualifier = Bp & BpQualif;`
197			`wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];`
198			`wire TempIQualifier = IStatus[1:0] == IQualif[1:0];`
199
200			`wire TempQualifierAND = ( (TempWpQualifier \| ~WpQualifValid)`
201			`& (TempBpQualifier \| ~BpQualifValid)`
202			`& (TempLSSQualifier \| ~LSSQualifValid)`
203			`& (TempIQualifier \| ~IQualifValid)`
204			`)`
205			`& (WpQualifValid \| BpQualifValid \| LSSQualifValid \| IQualifValid);`
206
207			`wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)`
208			`\| (TempBpQualifier & BpQualifValid)`
209			`\| (TempLSSQualifier & LSSQualifValid)`
210			`\| (TempIQualifier & IQualifValid)`
211			`);`
212
213
214			`wire Stop;`
215			`wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any`
216			`QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR`
217			`);`
218
219			`/**********************************************************************************`
220			`* *`
221			`* Generation of the stop signal *`
222			`* *`
223			`**********************************************************************************/`
224			`wire TempWpStop = \|(Wp[10:0] & WpStop[10:0]);`
225			`wire TempBpStop = Bp & BpStop;`
226			`wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];`
227			`wire TempIStop = IStatus[1:0] == IStop[1:0];`
228
229			`wire TempStopAND = ( (TempWpStop \| ~WpStopValid)`
230			`& (TempBpStop \| ~BpStopValid)`
231			`& (TempLSSStop \| ~LSSStopValid)`
232			`& (TempIStop \| ~IStopValid)`
233			`)`
234			`& (WpStopValid \| BpStopValid \| LSSStopValid \| IStopValid);`
235
236			`wire TempStopOR = ( (TempWpStop & WpStopValid)`
237			`\| (TempBpStop & BpStopValid)`
238			`\| (TempLSSStop & LSSStopValid)`
239			`\| (TempIStop & IStopValid)`
240			`);`
241
242
243			`assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing`
244			`StopOper[0]? TempStopAND : TempStopOR // AND : OR`
245			`);`
246
247
248
249			`/**********************************************************************************`
250			`* *`
251			`* Generation of the TriggerLatch *`
252			`* *`
253			`**********************************************************************************/`
254			`wire Reset_TriggerLatch = Reset \| TriggerLatch & ~TraceEnable;`
255			`always @(posedge Mclk or posedge Reset_TriggerLatch)`
256			`begin`
257			`if(Reset_TriggerLatch)`
258			`TriggerLatch<=#Tp 0;`
259			`else`
260			`if(Trigger)`
261			`TriggerLatch<=#Tp 1;`
262			`end`
263
264
265			`/**********************************************************************************`
266			`* *`
267			`* CpuStall, counter and pointers generation *`
268			`* *`
269			`**********************************************************************************/`
270			`reg BufferFullDetected;`
271			reg [`OPSELECTIONCOUNTER-1:0] RecEnable;
272
273			wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
274			wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
275			`wire IncrementCounter = CpuStall_q & ~(BufferFull \| BufferFullDetected) & Qualifier & RecEnable[StallCounter];`
276			`wire IncrementPointer = CpuStall_q & (~BufferFull \| ContinMode) & Qualifier & RecEnable[StallCounter];`
277
278			`wire WriteSample = IncrementPointer;`
279
280			`wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode \| ContinMode & ~TraceEnable);`
281			`wire CounterEn = IncrementCounter ^ Decrement;`
282
283			`wire ResetCpuStall;`
284			`wire ResetStallCounter;`
285			`reg BufferFull_q;`
286			`reg BufferFull_2q;`
287
288			`reg Qualifier_mclk;`
289
290			`always @(posedge Mclk)`
291			`begin`
292			`Qualifier_mclk<=#Tp Qualifier;`
293			`BufferFull_q<=#Tp BufferFull;`
294			`BufferFull_2q<=#Tp BufferFull_q;`
295			`CpuStall_q <=#Tp CpuStall;`
296			`end`
297
298
299			`wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch \| Qualifier_mclk & Trigger & ~TriggerLatch \|`
300			`Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;`
301
302
303			`wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &`
304			`(`
305			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
306			`(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) \|`
307			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
308			`);`
309
310			`assign ResetCpuStall = (`
311			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) \|
312			(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
313			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
314			`) \| Reset;`
315
316
317			`always @(posedge Mclk or posedge Reset)`
318			`begin`
319			`if(Reset)`
320			`Counter<=#Tp 0;`
321			`else`
322			`if(CounterEn)`
323			`if(IncrementCounter)`
324			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
325			`else`
326			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
327			`end`
328
329
330			`always @(posedge Mclk or posedge Reset)`
331			`begin`
332			`if(Reset)`
333			`begin`
334			`WritePointer<=#Tp 0;`
335			`ReadPointer<=#Tp 0;`
336			`end`
337			`else`
338			`begin`
339			`if(IncrementPointer)`
340			WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
341			`// else igor !!! Probably else is missing here. Check it.`
342			`if(Decrement & ~ContinMode \| Decrement & ContinMode & ~TraceEnable)`
343			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
344			`else`
345			`if(ContinMode & IncrementPointer & (BufferFull \| BufferFullDetected))`
346			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
347			`end`
348			`end`
349
350			`always @(posedge Mclk)`
351			`begin`
352			`if(~TraceEnable)`
353			`BufferFullDetected<=#Tp 0;`
354			`else`
355			`if(ContinMode & BufferFull)`
356			`BufferFullDetected<=#Tp 1;`
357			`end`
358
359
360			`always @(posedge Mclk or posedge AsyncSetCpuStall)`
361			`begin`
362			`if(AsyncSetCpuStall)`
363			`CpuStall<=#Tp 1;`
364			`else`
365			`if(SyncSetCpuStall)`
366			`CpuStall<=#Tp 1;`
367			`else`
368			`if(ResetCpuStall)`
369			`CpuStall<=#Tp 0;`
370			`end`
371
372
373			`always @(posedge Mclk)`
374			`begin`
375			`if(ResetStallCounter)`
376			`StallCounter<=#Tp 0;`
377			`else`
378			`if(CpuStall_q & (~BufferFull \| ContinMode))`
379			`StallCounter<=#Tp StallCounter+1;`
380			`end`
381
382			assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull \| Reset;
383
384
385			`/**********************************************************************************`
386			`* *`
387			`* Valid status *`
388			`* *`
389			`**********************************************************************************/`
390			`wire Valid = ~BufferEmpty;`
391
392
393			`/**********************************************************************************`
394			`* *`
395			`* Writing and reading the sample to/from the buffer *`
396			`* *`
397			`**********************************************************************************/`
398			`always @ (posedge Mclk)`
399			`begin`
400			`if(WriteSample)`
401			Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
402			`end`
403
404			`assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};`
405
406
407
408			`/**********************************************************************************`
409			`* *`
410			`* Operation select (to select which kind of data appears on the DATAIN lines) *`
411			`* *`
412			`**********************************************************************************/`
413			assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
414
415
416
417			`/**********************************************************************************`
418			`* *`
419			`* Selecting which parts are going to be recorded as part of the sample *`
420			`* *`
421			`**********************************************************************************/`
422			`always @(posedge Mclk or posedge Reset)`
423			`begin`
424			`if(Reset)`
425			`RecEnable<=#Tp 0;`
426			`else`
427			`if(CpuStall)`
428			`begin`
429			RecEnable<=#Tp {1'b0, RecordINSTR_Wp[0], RecordWriteSPR_Wp[0], RecordReadSPR_Wp[0], RecordSDATA_Wp[0], RecordLDATA_Wp[0], RecordLSEA_Wp[0], RecordPC_Wp[0]} & {`OPSELECTIONCOUNTER{Wp[0]}} \|
430			{1'b0, RecordINSTR_Wp[1], RecordWriteSPR_Wp[1], RecordReadSPR_Wp[1], RecordSDATA_Wp[1], RecordLDATA_Wp[1], RecordLSEA_Wp[1], RecordPC_Wp[1]} & {`OPSELECTIONCOUNTER{Wp[1]}} \|
431			{1'b0, RecordINSTR_Wp[2], RecordWriteSPR_Wp[2], RecordReadSPR_Wp[2], RecordSDATA_Wp[2], RecordLDATA_Wp[2], RecordLSEA_Wp[2], RecordPC_Wp[2]} & {`OPSELECTIONCOUNTER{Wp[2]}} \|
432			{1'b0, RecordINSTR_Wp[3], RecordWriteSPR_Wp[3], RecordReadSPR_Wp[3], RecordSDATA_Wp[3], RecordLDATA_Wp[3], RecordLSEA_Wp[3], RecordPC_Wp[3]} & {`OPSELECTIONCOUNTER{Wp[3]}} \|
433			{1'b0, RecordINSTR_Wp[4], RecordWriteSPR_Wp[4], RecordReadSPR_Wp[4], RecordSDATA_Wp[4], RecordLDATA_Wp[4], RecordLSEA_Wp[4], RecordPC_Wp[4]} & {`OPSELECTIONCOUNTER{Wp[4]}} \|
434			{1'b0, RecordINSTR_Wp[5], RecordWriteSPR_Wp[5], RecordReadSPR_Wp[5], RecordSDATA_Wp[5], RecordLDATA_Wp[5], RecordLSEA_Wp[5], RecordPC_Wp[5]} & {`OPSELECTIONCOUNTER{Wp[5]}} \|
435			{1'b0, RecordINSTR_Wp[6], RecordWriteSPR_Wp[6], RecordReadSPR_Wp[6], RecordSDATA_Wp[6], RecordLDATA_Wp[6], RecordLSEA_Wp[6], RecordPC_Wp[6]} & {`OPSELECTIONCOUNTER{Wp[6]}} \|
436			{1'b0, RecordINSTR_Wp[7], RecordWriteSPR_Wp[7], RecordReadSPR_Wp[7], RecordSDATA_Wp[7], RecordLDATA_Wp[7], RecordLSEA_Wp[7], RecordPC_Wp[7]} & {`OPSELECTIONCOUNTER{Wp[7]}} \|
437			{1'b0, RecordINSTR_Wp[8], RecordWriteSPR_Wp[8], RecordReadSPR_Wp[8], RecordSDATA_Wp[8], RecordLDATA_Wp[8], RecordLSEA_Wp[8], RecordPC_Wp[8]} & {`OPSELECTIONCOUNTER{Wp[8]}} \|
438			{1'b0, RecordINSTR_Wp[9], RecordWriteSPR_Wp[9], RecordReadSPR_Wp[9], RecordSDATA_Wp[9], RecordLDATA_Wp[9], RecordLSEA_Wp[9], RecordPC_Wp[9]} & {`OPSELECTIONCOUNTER{Wp[9]}} \|
439			{1'b0, RecordINSTR_Wp[10], RecordWriteSPR_Wp[10], RecordReadSPR_Wp[10], RecordSDATA_Wp[10], RecordLDATA_Wp[10], RecordLSEA_Wp[10], RecordPC_Wp[10]}& {`OPSELECTIONCOUNTER{Wp[10]}} \|
440			{1'b0, RecordINSTR_Bp, RecordWriteSPR_Bp, RecordReadSPR_Bp, RecordSDATA_Bp, RecordLDATA_Bp, RecordLSEA_Bp, RecordPC_Bp} & {`OPSELECTIONCOUNTER{Bp}};
441			`end`
442			`end`
443
444
445			`endmodule // Trace`