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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_trace.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_trace.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:06  mohor
// Initial release
//
//
 
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall,
                  Mclk, Reset, TraceChain, ContinMode, TraceEnable,
                  WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
                  BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
                  RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
                  RecordINSTR,
                  WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
                  WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
                  WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
                  LSSStopValid, IStopValid
                 );
 
parameter Tp = 1;
 
 
input [10:0] Wp;        // Watchpoints
input        Bp;        // Breakpoint
input [31:0] DataIn;    // Data from the RISC
input [3:0]  LsStatus;  // Load/Store status
input [1:0]  IStatus;   // Instruction status
 
input        Mclk;      // Master clock (RISC clock)
input        Reset;     // Reset
input        ReadBuffer;// Instruction for reading a sample from the Buffer
 
// from registers
input ContinMode;
input TraceEnable;
 
input [10:0] WpTrigger;
input        BpTrigger;
input [3:0]  LSSTrigger;
input [1:0]  ITrigger;
input [1:0]  TriggerOper;
 
input [10:0] WpQualif;
input        BpQualif;
input [3:0]  LSSQualif;
input [1:0]  IQualif;
input [1:0]  QualifOper;
 
input [10:0] WpStop;
input        BpStop;
input [3:0]  LSSStop;
input [1:0]  IStop;
input [1:0]  StopOper;
 
input RecordPC;
input RecordLSEA;
input RecordLDATA;
input RecordSDATA;
input RecordReadSPR;
input RecordWriteSPR;
input RecordINSTR;
 
input WpTriggerValid;
input BpTriggerValid;
input LSSTriggerValid;
input ITriggerValid;
 
input WpQualifValid;
input BpQualifValid;
input LSSQualifValid;
input IQualifValid;
 
input WpStopValid;
input BpStopValid;
input LSSStopValid;
input IStopValid;
// end: from registers
 
 
output [`OPSELECTWIDTH-1:0]  OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
output        RiscStall;  // CPU stall (stalls the RISC)
output [39:0] TraceChain; // Scan shain from the trace module
 
 
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg RiscStall;
reg RiscStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
 
reg TriggerLatch;
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the trigger                                                     *
*                                                                                 *
**********************************************************************************/
wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
wire TempBpTrigger = Bp & BpTrigger;
wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
 
wire TempTriggerAND =  (  (TempWpTrigger  | ~WpTriggerValid)
                        & (TempBpTrigger  | ~BpTriggerValid)
                        & (TempLSSTrigger | ~LSSTriggerValid)
                        & (TempITrigger   | ~ITriggerValid)
                       )
                       & (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
 
wire TempTriggerOR =   (  (TempWpTrigger  &  WpTriggerValid)
                        | (TempBpTrigger  &  BpTriggerValid)
                        | (TempLSSTrigger &  LSSTriggerValid)
                        | (TempITrigger   &  ITriggerValid)
                       );
 
wire Trigger = TraceEnable & (~TriggerOper[1]?  1 :                               // any
                               TriggerOper[0]?  TempTriggerAND : TempTriggerOR    // AND : OR
                             );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the qualifier                                                   *
*                                                                                 *
**********************************************************************************/
wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
wire TempBpQualifier = Bp & BpQualif;
wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
 
wire TempQualifierAND =  (  (TempWpQualifier  | ~WpQualifValid)
                          & (TempBpQualifier  | ~BpQualifValid)
                          & (TempLSSQualifier | ~LSSQualifValid)
                          & (TempIQualifier   | ~IQualifValid)
                         )
                         & (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
 
wire TempQualifierOR =   (  (TempWpQualifier  &  WpQualifValid)
                          | (TempBpQualifier  &  BpQualifValid)
                          | (TempLSSQualifier &  LSSQualifValid)
                          | (TempIQualifier   &  IQualifValid)
                         );
 
 
wire Stop;
wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 :                                   // any
                                         QualifOper[0]? TempQualifierAND  :  TempQualifierOR  // AND : OR
                                       );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the stop signal                                                 *
*                                                                                 *
**********************************************************************************/
wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
wire TempBpStop = Bp & BpStop;
wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
wire TempIStop = IStatus[1:0] == IStop[1:0];
 
wire TempStopAND =  (  (TempWpStop  | ~WpStopValid)
                          & (TempBpStop  | ~BpStopValid)
                          & (TempLSSStop | ~LSSStopValid)
                          & (TempIStop   | ~IStopValid)
                         )
                         & (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
 
wire TempStopOR =   (  (TempWpStop  &  WpStopValid)
                          | (TempBpStop  &  BpStopValid)
                          | (TempLSSStop &  LSSStopValid)
                          | (TempIStop   &  IStopValid)
                         );
 
 
assign Stop = TraceEnable & (~StopOper[1]? 0 :                         // nothing
                              StopOper[0]? TempStopAND  :  TempStopOR  // AND : OR
                            );
 
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the TriggerLatch                                                *
*                                                                                 *
**********************************************************************************/
wire Reset_TriggerLatch = Reset | TriggerLatch & ~TraceEnable;
always @(posedge Mclk or posedge Reset_TriggerLatch)
begin
  if(Reset_TriggerLatch)
    TriggerLatch<=#Tp 0;
  else
  if(Trigger)
    TriggerLatch<=#Tp 1;
end
 
 
/**********************************************************************************
*                                                                                 *
*   RiscStall, counter and pointers generation                                     *
*                                                                                 *
**********************************************************************************/
reg BufferFullDetected;
wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
wire CounterEn = IncrementCounter ^ Decrement;
 
wire ResetCpuStall;
wire ResetStallCounter;
reg BufferFull_q;
reg BufferFull_2q;
 
reg Qualifier_mclk;
 
always @(posedge Mclk)
begin
  Qualifier_mclk<=#Tp Qualifier;
  BufferFull_q<=#Tp BufferFull;
  BufferFull_2q<=#Tp BufferFull_q;
  RiscStall_q <=#Tp RiscStall;
end
 
 
wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch | Qualifier_mclk & Trigger & ~TriggerLatch |
                        Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
 
 
wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
                       (
                        (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                        (~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0)                   |
                        ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
                       );
 
assign ResetCpuStall = (
                        (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
                        (~ContinMode &  ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                        ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
                       ) | Reset;
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    Counter<=#Tp 0;
  else
  if(CounterEn)
    if(IncrementCounter)
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
    else
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    begin
      WritePointer<=#Tp 0;
      ReadPointer<=#Tp 0;
    end
  else
    begin
      if(IncrementPointer)
        WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
      // else igor !!! Probably else is missing here. Check it.
      if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
        ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
      else
      if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
        ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
    end
end
 
always @(posedge Mclk)
begin
  if(~TraceEnable)
    BufferFullDetected<=#Tp 0;
  else
  if(ContinMode & BufferFull)
    BufferFullDetected<=#Tp 1;
end
 
 
always @(posedge Mclk or posedge AsyncSetCpuStall)
begin
  if(AsyncSetCpuStall)
    RiscStall<=#Tp 1;
  else
  if(SyncSetCpuStall)
    RiscStall<=#Tp 1;
  else
  if(ResetCpuStall)
    RiscStall<=#Tp 0;
end
 
 
always @(posedge Mclk)
begin
  if(ResetStallCounter)
    StallCounter<=#Tp 0;
  else
  if(RiscStall_q & (~BufferFull | ContinMode))
    StallCounter<=#Tp StallCounter+1;
end
 
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
 
 
/**********************************************************************************
*                                                                                 *
*   Valid status                                                                  *
*                                                                                 *
**********************************************************************************/
wire Valid = ~BufferEmpty;
 
 
/**********************************************************************************
*                                                                                 *
*   Writing and reading the sample to/from the buffer                             *
*                                                                                 *
**********************************************************************************/
always @ (posedge Mclk)
begin
  if(WriteSample)
    Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
end
 
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
 
 
 
/**********************************************************************************
*                                                                                 *
*   Operation select (to select which kind of data appears on the DATAIN lines)   *
*                                                                                 *
**********************************************************************************/
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
 
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting which parts are going to be recorded as part of the sample          *
*                                                                                 *
**********************************************************************************/
assign RecEnable = {1'b0, RecordINSTR,  RecordWriteSPR,  RecordReadSPR,  RecordSDATA,  RecordLDATA,  RecordLSEA,  RecordPC};
 
 
endmodule // Trace

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_trace.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_trace.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
49			`// Initial official release.`
50			`//`
51	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
52			`// This is a backup. It is not a fully working version. Not for use, yet.`
53			`//`
54			`// Revision 1.2 2001/05/18 13:10:00 mohor`
55			`// Headers changed. All additional information is now avaliable in the README.txt file.`
56			`//`
57			`// Revision 1.1.1.1 2001/05/18 06:35:06 mohor`
58			`// Initial release`
59			`//`
60			`//`
61
62
63			`include "dbg_timescale.v"
64			`include "dbg_defines.v"
65
66			`// module Trace`
67	5	mohor	`module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall,`
68			`Mclk, Reset, TraceChain, ContinMode, TraceEnable,`
69	2	mohor	`WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,`
70	5	mohor	`BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,`
71			`RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,`
72			`RecordINSTR,`
73	2	mohor	`WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,`
74			`WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,`
75			`WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,`
76			`LSSStopValid, IStopValid`
77			`);`
78
79			`parameter Tp = 1;`
80
81
82			`input [10:0] Wp; // Watchpoints`
83			`input Bp; // Breakpoint`
84			`input [31:0] DataIn; // Data from the RISC`
85			`input [3:0] LsStatus; // Load/Store status`
86			`input [1:0] IStatus; // Instruction status`
87
88			`input Mclk; // Master clock (RISC clock)`
89			`input Reset; // Reset`
90			`input ReadBuffer;// Instruction for reading a sample from the Buffer`
91
92			`// from registers`
93			`input ContinMode;`
94			`input TraceEnable;`
95
96			`input [10:0] WpTrigger;`
97			`input BpTrigger;`
98			`input [3:0] LSSTrigger;`
99			`input [1:0] ITrigger;`
100			`input [1:0] TriggerOper;`
101
102			`input [10:0] WpQualif;`
103			`input BpQualif;`
104			`input [3:0] LSSQualif;`
105			`input [1:0] IQualif;`
106			`input [1:0] QualifOper;`
107
108			`input [10:0] WpStop;`
109			`input BpStop;`
110			`input [3:0] LSSStop;`
111			`input [1:0] IStop;`
112			`input [1:0] StopOper;`
113
114	5	mohor	`input RecordPC;`
115			`input RecordLSEA;`
116			`input RecordLDATA;`
117			`input RecordSDATA;`
118			`input RecordReadSPR;`
119			`input RecordWriteSPR;`
120			`input RecordINSTR;`
121	2	mohor
122			`input WpTriggerValid;`
123			`input BpTriggerValid;`
124			`input LSSTriggerValid;`
125			`input ITriggerValid;`
126
127			`input WpQualifValid;`
128			`input BpQualifValid;`
129			`input LSSQualifValid;`
130			`input IQualifValid;`
131
132			`input WpStopValid;`
133			`input BpStopValid;`
134			`input LSSStopValid;`
135			`input IStopValid;`
136			`// end: from registers`
137
138
139			output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
140	5	mohor	`output RiscStall; // CPU stall (stalls the RISC)`
141	2	mohor	`output [39:0] TraceChain; // Scan shain from the trace module`
142
143
144			reg [`TRACECOUNTERWIDTH:0] Counter;
145			reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
146			reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
147	5	mohor	`reg RiscStall;`
148			`reg RiscStall_q;`
149	2	mohor	reg [`OPSELECTWIDTH-1:0] StallCounter;
150
151			reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
152
153			`reg TriggerLatch;`
154
155
156			`/**********************************************************************************`
157			`* *`
158			`* Generation of the trigger *`
159			`* *`
160			`**********************************************************************************/`
161			`wire TempWpTrigger = \|(Wp[10:0] & WpTrigger[10:0]);`
162			`wire TempBpTrigger = Bp & BpTrigger;`
163			`wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];`
164			`wire TempITrigger = IStatus[1:0] == ITrigger[1:0];`
165
166			`wire TempTriggerAND = ( (TempWpTrigger \| ~WpTriggerValid)`
167			`& (TempBpTrigger \| ~BpTriggerValid)`
168			`& (TempLSSTrigger \| ~LSSTriggerValid)`
169			`& (TempITrigger \| ~ITriggerValid)`
170			`)`
171			`& (WpTriggerValid \| BpTriggerValid \| LSSTriggerValid \| ITriggerValid);`
172
173			`wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)`
174			`\| (TempBpTrigger & BpTriggerValid)`
175			`\| (TempLSSTrigger & LSSTriggerValid)`
176			`\| (TempITrigger & ITriggerValid)`
177			`);`
178
179			`wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any`
180			`TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR`
181			`);`
182
183			`/**********************************************************************************`
184			`* *`
185			`* Generation of the qualifier *`
186			`* *`
187			`**********************************************************************************/`
188			`wire TempWpQualifier = \|(Wp[10:0] & WpQualif[10:0]);`
189			`wire TempBpQualifier = Bp & BpQualif;`
190			`wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];`
191			`wire TempIQualifier = IStatus[1:0] == IQualif[1:0];`
192
193			`wire TempQualifierAND = ( (TempWpQualifier \| ~WpQualifValid)`
194			`& (TempBpQualifier \| ~BpQualifValid)`
195			`& (TempLSSQualifier \| ~LSSQualifValid)`
196			`& (TempIQualifier \| ~IQualifValid)`
197			`)`
198			`& (WpQualifValid \| BpQualifValid \| LSSQualifValid \| IQualifValid);`
199
200			`wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)`
201			`\| (TempBpQualifier & BpQualifValid)`
202			`\| (TempLSSQualifier & LSSQualifValid)`
203			`\| (TempIQualifier & IQualifValid)`
204			`);`
205
206
207			`wire Stop;`
208			`wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any`
209			`QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR`
210			`);`
211
212			`/**********************************************************************************`
213			`* *`
214			`* Generation of the stop signal *`
215			`* *`
216			`**********************************************************************************/`
217			`wire TempWpStop = \|(Wp[10:0] & WpStop[10:0]);`
218			`wire TempBpStop = Bp & BpStop;`
219			`wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];`
220			`wire TempIStop = IStatus[1:0] == IStop[1:0];`
221
222			`wire TempStopAND = ( (TempWpStop \| ~WpStopValid)`
223			`& (TempBpStop \| ~BpStopValid)`
224			`& (TempLSSStop \| ~LSSStopValid)`
225			`& (TempIStop \| ~IStopValid)`
226			`)`
227			`& (WpStopValid \| BpStopValid \| LSSStopValid \| IStopValid);`
228
229			`wire TempStopOR = ( (TempWpStop & WpStopValid)`
230			`\| (TempBpStop & BpStopValid)`
231			`\| (TempLSSStop & LSSStopValid)`
232			`\| (TempIStop & IStopValid)`
233			`);`
234
235
236			`assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing`
237			`StopOper[0]? TempStopAND : TempStopOR // AND : OR`
238			`);`
239
240
241
242			`/**********************************************************************************`
243			`* *`
244			`* Generation of the TriggerLatch *`
245			`* *`
246			`**********************************************************************************/`
247			`wire Reset_TriggerLatch = Reset \| TriggerLatch & ~TraceEnable;`
248			`always @(posedge Mclk or posedge Reset_TriggerLatch)`
249			`begin`
250			`if(Reset_TriggerLatch)`
251			`TriggerLatch<=#Tp 0;`
252			`else`
253			`if(Trigger)`
254			`TriggerLatch<=#Tp 1;`
255			`end`
256
257
258			`/**********************************************************************************`
259			`* *`
260	5	mohor	`* RiscStall, counter and pointers generation *`
261	2	mohor	`* *`
262			`**********************************************************************************/`
263			`reg BufferFullDetected;`
264	5	mohor	wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
265	2	mohor
266			wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
267			wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
268	5	mohor	`wire IncrementCounter = RiscStall_q & ~(BufferFull \| BufferFullDetected) & Qualifier & RecEnable[StallCounter];`
269			`wire IncrementPointer = RiscStall_q & (~BufferFull \| ContinMode) & Qualifier & RecEnable[StallCounter];`
270	2	mohor
271			`wire WriteSample = IncrementPointer;`
272
273			`wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode \| ContinMode & ~TraceEnable);`
274			`wire CounterEn = IncrementCounter ^ Decrement;`
275
276			`wire ResetCpuStall;`
277			`wire ResetStallCounter;`
278			`reg BufferFull_q;`
279			`reg BufferFull_2q;`
280
281			`reg Qualifier_mclk;`
282
283			`always @(posedge Mclk)`
284			`begin`
285			`Qualifier_mclk<=#Tp Qualifier;`
286			`BufferFull_q<=#Tp BufferFull;`
287			`BufferFull_2q<=#Tp BufferFull_q;`
288	5	mohor	`RiscStall_q <=#Tp RiscStall;`
289	2	mohor	`end`
290
291
292			`wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch \| Qualifier_mclk & Trigger & ~TriggerLatch \|`
293			`Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;`
294
295
296			`wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &`
297			`(`
298			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
299			`(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) \|`
300			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
301			`);`
302
303			`assign ResetCpuStall = (`
304			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) \|
305			(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
306			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
307			`) \| Reset;`
308
309
310			`always @(posedge Mclk or posedge Reset)`
311			`begin`
312			`if(Reset)`
313			`Counter<=#Tp 0;`
314			`else`
315			`if(CounterEn)`
316			`if(IncrementCounter)`
317			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
318			`else`
319			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
320			`end`
321
322
323			`always @(posedge Mclk or posedge Reset)`
324			`begin`
325			`if(Reset)`
326			`begin`
327			`WritePointer<=#Tp 0;`
328			`ReadPointer<=#Tp 0;`
329			`end`
330			`else`
331			`begin`
332			`if(IncrementPointer)`
333			WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
334			`// else igor !!! Probably else is missing here. Check it.`
335			`if(Decrement & ~ContinMode \| Decrement & ContinMode & ~TraceEnable)`
336			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
337			`else`
338			`if(ContinMode & IncrementPointer & (BufferFull \| BufferFullDetected))`
339			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
340			`end`
341			`end`
342
343			`always @(posedge Mclk)`
344			`begin`
345			`if(~TraceEnable)`
346			`BufferFullDetected<=#Tp 0;`
347			`else`
348			`if(ContinMode & BufferFull)`
349			`BufferFullDetected<=#Tp 1;`
350			`end`
351
352
353			`always @(posedge Mclk or posedge AsyncSetCpuStall)`
354			`begin`
355			`if(AsyncSetCpuStall)`
356	5	mohor	`RiscStall<=#Tp 1;`
357	2	mohor	`else`
358			`if(SyncSetCpuStall)`
359	5	mohor	`RiscStall<=#Tp 1;`
360	2	mohor	`else`
361			`if(ResetCpuStall)`
362	5	mohor	`RiscStall<=#Tp 0;`
363	2	mohor	`end`
364
365
366			`always @(posedge Mclk)`
367			`begin`
368			`if(ResetStallCounter)`
369			`StallCounter<=#Tp 0;`
370			`else`
371	5	mohor	`if(RiscStall_q & (~BufferFull \| ContinMode))`
372	2	mohor	`StallCounter<=#Tp StallCounter+1;`
373			`end`
374
375			assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull \| Reset;
376
377
378			`/**********************************************************************************`
379			`* *`
380			`* Valid status *`
381			`* *`
382			`**********************************************************************************/`
383			`wire Valid = ~BufferEmpty;`
384
385
386			`/**********************************************************************************`
387			`* *`
388			`* Writing and reading the sample to/from the buffer *`
389			`* *`
390			`**********************************************************************************/`
391			`always @ (posedge Mclk)`
392			`begin`
393			`if(WriteSample)`
394			Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
395			`end`
396
397			`assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};`
398
399
400
401			`/**********************************************************************************`
402			`* *`
403			`* Operation select (to select which kind of data appears on the DATAIN lines) *`
404			`* *`
405			`**********************************************************************************/`
406			assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
407
408
409
410			`/**********************************************************************************`
411			`* *`
412			`* Selecting which parts are going to be recorded as part of the sample *`
413			`* *`
414			`**********************************************************************************/`
415	5	mohor	`assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};`
416	2	mohor
417
418	5	mohor	`endmodule // Trace`