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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_trace.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:06  mohor
// Initial release
//
//
 
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,
                  Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
                  WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
                  BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
                  RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
                  RecordINSTR,
                  WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
                  WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
                  WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
                  LSSStopValid, IStopValid
                 );
 
parameter Tp = 1;
 
 
input [10:0] Wp;        // Watchpoints
input        Bp;        // Breakpoint
input [31:0] DataIn;    // Data from the RISC
input [3:0]  LsStatus;  // Load/Store status
input [1:0]  IStatus;   // Instruction status
 
input        Mclk;      // Master clock (RISC clock)
input        Reset;     // Reset
input        ReadBuffer;// Instruction for reading a sample from the Buffer
 
// from registers
input ContinMode;
input TraceEnable_reg;
 
input [10:0] WpTrigger;
input        BpTrigger;
input [3:0]  LSSTrigger;
input [1:0]  ITrigger;
input [1:0]  TriggerOper;
 
input [10:0] WpQualif;
input        BpQualif;
input [3:0]  LSSQualif;
input [1:0]  IQualif;
input [1:0]  QualifOper;
 
input [10:0] WpStop;
input        BpStop;
input [3:0]  LSSStop;
input [1:0]  IStop;
input [1:0]  StopOper;
 
input RecordPC;
input RecordLSEA;
input RecordLDATA;
input RecordSDATA;
input RecordReadSPR;
input RecordWriteSPR;
input RecordINSTR;
 
input WpTriggerValid;
input BpTriggerValid;
input LSSTriggerValid;
input ITriggerValid;
 
input WpQualifValid;
input BpQualifValid;
input LSSQualifValid;
input IQualifValid;
 
input WpStopValid;
input BpStopValid;
input LSSStopValid;
input IStopValid;
// end: from registers
 
 
output [`OPSELECTWIDTH-1:0]  OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
output        RiscStall_O;  // CPU stall (stalls the RISC)
output [39:0] TraceChain; // Scan shain from the trace module
 
reg TraceEnable_d;
reg TraceEnable;
 
 
 
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg RiscStall;
reg RiscStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
 
reg TriggerLatch;
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the trigger                                                     *
*                                                                                 *
**********************************************************************************/
wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
wire TempBpTrigger = Bp & BpTrigger;
wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
 
wire TempTriggerAND =  (  (TempWpTrigger  | ~WpTriggerValid)
                        & (TempBpTrigger  | ~BpTriggerValid)
                        & (TempLSSTrigger | ~LSSTriggerValid)
                        & (TempITrigger   | ~ITriggerValid)
                       )
                       & (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
 
wire TempTriggerOR =   (  (TempWpTrigger  &  WpTriggerValid)
                        | (TempBpTrigger  &  BpTriggerValid)
                        | (TempLSSTrigger &  LSSTriggerValid)
                        | (TempITrigger   &  ITriggerValid)
                       );
 
wire Trigger = TraceEnable & (~TriggerOper[1]?  1 :                               // any
                               TriggerOper[0]?  TempTriggerAND : TempTriggerOR    // AND : OR
                             );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the qualifier                                                   *
*                                                                                 *
**********************************************************************************/
wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
wire TempBpQualifier = Bp & BpQualif;
wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
 
wire TempQualifierAND =  (  (TempWpQualifier  | ~WpQualifValid)
                          & (TempBpQualifier  | ~BpQualifValid)
                          & (TempLSSQualifier | ~LSSQualifValid)
                          & (TempIQualifier   | ~IQualifValid)
                         )
                         & (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
 
wire TempQualifierOR =   (  (TempWpQualifier  &  WpQualifValid)
                          | (TempBpQualifier  &  BpQualifValid)
                          | (TempLSSQualifier &  LSSQualifValid)
                          | (TempIQualifier   &  IQualifValid)
                         );
 
 
wire Stop;
wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 :                                   // any
                                         QualifOper[0]? TempQualifierAND  :  TempQualifierOR  // AND : OR
                                       );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the stop signal                                                 *
*                                                                                 *
**********************************************************************************/
wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
wire TempBpStop = Bp & BpStop;
wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
wire TempIStop = IStatus[1:0] == IStop[1:0];
 
wire TempStopAND =       (  (TempWpStop  | ~WpStopValid)
                          & (TempBpStop  | ~BpStopValid)
                          & (TempLSSStop | ~LSSStopValid)
                          & (TempIStop   | ~IStopValid)
                         )
                         & (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
 
wire TempStopOR =        (  (TempWpStop  &  WpStopValid)
                          | (TempBpStop  &  BpStopValid)
                          | (TempLSSStop &  LSSStopValid)
                          | (TempIStop   &  IStopValid)
                         );
 
 
assign Stop = TraceEnable & (~StopOper[1]? 0 :                         // nothing
                              StopOper[0]? TempStopAND  :  TempStopOR  // AND : OR
                            );
 
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the TriggerLatch                                                *
*                                                                                 *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    TriggerLatch<=#Tp 0;
  else
  if(TriggerLatch & ~TraceEnable)
    TriggerLatch<=#Tp 0;
  else
  if(Trigger)
    TriggerLatch<=#Tp 1;
end
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   TraceEnable Synchronization                                                   *
*                                                                                 *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    begin
      TraceEnable_d<=#Tp 0;
      TraceEnable<=#Tp 0;
    end
  else
    begin
      TraceEnable_d<=#Tp TraceEnable_reg;
      TraceEnable<=#Tp TraceEnable_d;
    end
end
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   RiscStall, counter and pointers generation                                     *
*                                                                                 *
**********************************************************************************/
reg BufferFullDetected;
wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
wire CounterEn = IncrementCounter ^ Decrement;
 
wire SyncResetCpuStall;
wire ResetStallCounter;
reg BufferFull_q;
reg BufferFull_2q;
 
reg Qualifier_mclk;
 
always @(posedge Mclk)
begin
  Qualifier_mclk<=#Tp Qualifier;
  BufferFull_q<=#Tp BufferFull;
  BufferFull_2q<=#Tp BufferFull_q;
  RiscStall_q <=#Tp RiscStall_O;
end
 
 
wire FirstCpuStall =    Qualifier & ~Qualifier_mclk & TriggerLatch              |
                        Qualifier_mclk & Trigger & ~TriggerLatch                |
                        Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch   ;
 
 
//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
 
wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q |
                        Qualifier_mclk & TriggerLatch &
                       (
                        (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                        (~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0)                   |
                        ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
                       );
 
assign SyncResetCpuStall = (
                            (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
                            (~ContinMode &  ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                            ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
                           );
 
assign RiscStall_O = FirstCpuStall | RiscStall;
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    Counter<=#Tp 0;
  else
  if(CounterEn)
    if(IncrementCounter)
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
    else
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    WritePointer<=#Tp 0;
  else
  if(IncrementPointer)
    WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    ReadPointer<=#Tp 0;
  else
  if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
    ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
  else
  if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
    ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
 
always @(posedge Mclk)
begin
  if(~TraceEnable)
    BufferFullDetected<=#Tp 0;
  else
  if(ContinMode & BufferFull)
    BufferFullDetected<=#Tp 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    RiscStall<=#Tp 0;
  else
  if(SyncResetCpuStall)
    RiscStall<=#Tp 0;
  else
  if(SyncSetCpuStall)
    RiscStall<=#Tp 1;
end
 
 
always @(posedge Mclk)
begin
  if(ResetStallCounter)
    StallCounter<=#Tp 0;
  else
  if(RiscStall_q & (~BufferFull | ContinMode))
    StallCounter<=#Tp StallCounter+1;
end
 
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
 
 
/**********************************************************************************
*                                                                                 *
*   Valid status                                                                  *
*                                                                                 *
**********************************************************************************/
wire Valid = ~BufferEmpty;
 
 
/**********************************************************************************
*                                                                                 *
*   Writing and reading the sample to/from the buffer                             *
*                                                                                 *
**********************************************************************************/
always @ (posedge Mclk)
begin
  if(WriteSample)
    Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
end
 
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
 
 
 
/**********************************************************************************
*                                                                                 *
*   Operation select (to select which kind of data appears on the DATAIN lines)   *
*                                                                                 *
**********************************************************************************/
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
 
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting which parts are going to be recorded as part of the sample          *
*                                                                                 *
**********************************************************************************/
assign RecEnable = {1'b0, RecordINSTR,  RecordWriteSPR,  RecordReadSPR,  RecordSDATA,  RecordLDATA,  RecordLSEA,  RecordPC};
 
 
endmodule // Trace

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_trace.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	8	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
49			`// Trace fixed. Some registers changed, trace simplified.`
50			`//`
51	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
52			`// Initial official release.`
53			`//`
54	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
55			`// This is a backup. It is not a fully working version. Not for use, yet.`
56			`//`
57			`// Revision 1.2 2001/05/18 13:10:00 mohor`
58			`// Headers changed. All additional information is now avaliable in the README.txt file.`
59			`//`
60			`// Revision 1.1.1.1 2001/05/18 06:35:06 mohor`
61			`// Initial release`
62			`//`
63			`//`
64
65
66			`include "dbg_timescale.v"
67			`include "dbg_defines.v"
68
69			`// module Trace`
70	8	mohor	`module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,`
71			`Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,`
72	2	mohor	`WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,`
73	5	mohor	`BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,`
74			`RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,`
75			`RecordINSTR,`
76	2	mohor	`WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,`
77			`WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,`
78			`WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,`
79			`LSSStopValid, IStopValid`
80			`);`
81
82			`parameter Tp = 1;`
83
84
85			`input [10:0] Wp; // Watchpoints`
86			`input Bp; // Breakpoint`
87			`input [31:0] DataIn; // Data from the RISC`
88			`input [3:0] LsStatus; // Load/Store status`
89			`input [1:0] IStatus; // Instruction status`
90
91			`input Mclk; // Master clock (RISC clock)`
92			`input Reset; // Reset`
93			`input ReadBuffer;// Instruction for reading a sample from the Buffer`
94
95			`// from registers`
96			`input ContinMode;`
97	8	mohor	`input TraceEnable_reg;`
98	2	mohor
99			`input [10:0] WpTrigger;`
100			`input BpTrigger;`
101			`input [3:0] LSSTrigger;`
102			`input [1:0] ITrigger;`
103			`input [1:0] TriggerOper;`
104
105			`input [10:0] WpQualif;`
106			`input BpQualif;`
107			`input [3:0] LSSQualif;`
108			`input [1:0] IQualif;`
109			`input [1:0] QualifOper;`
110
111			`input [10:0] WpStop;`
112			`input BpStop;`
113			`input [3:0] LSSStop;`
114			`input [1:0] IStop;`
115			`input [1:0] StopOper;`
116
117	5	mohor	`input RecordPC;`
118			`input RecordLSEA;`
119			`input RecordLDATA;`
120			`input RecordSDATA;`
121			`input RecordReadSPR;`
122			`input RecordWriteSPR;`
123			`input RecordINSTR;`
124	2	mohor
125			`input WpTriggerValid;`
126			`input BpTriggerValid;`
127			`input LSSTriggerValid;`
128			`input ITriggerValid;`
129
130			`input WpQualifValid;`
131			`input BpQualifValid;`
132			`input LSSQualifValid;`
133			`input IQualifValid;`
134
135			`input WpStopValid;`
136			`input BpStopValid;`
137			`input LSSStopValid;`
138			`input IStopValid;`
139			`// end: from registers`
140
141
142			output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
143	8	mohor	`output RiscStall_O; // CPU stall (stalls the RISC)`
144	2	mohor	`output [39:0] TraceChain; // Scan shain from the trace module`
145
146	8	mohor	`reg TraceEnable_d;`
147			`reg TraceEnable;`
148	2	mohor
149	8	mohor
150
151	2	mohor	reg [`TRACECOUNTERWIDTH:0] Counter;
152			reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
153			reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
154	5	mohor	`reg RiscStall;`
155			`reg RiscStall_q;`
156	2	mohor	reg [`OPSELECTWIDTH-1:0] StallCounter;
157
158			reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
159
160			`reg TriggerLatch;`
161
162
163			`/**********************************************************************************`
164			`* *`
165			`* Generation of the trigger *`
166			`* *`
167			`**********************************************************************************/`
168			`wire TempWpTrigger = \|(Wp[10:0] & WpTrigger[10:0]);`
169			`wire TempBpTrigger = Bp & BpTrigger;`
170			`wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];`
171			`wire TempITrigger = IStatus[1:0] == ITrigger[1:0];`
172
173			`wire TempTriggerAND = ( (TempWpTrigger \| ~WpTriggerValid)`
174			`& (TempBpTrigger \| ~BpTriggerValid)`
175			`& (TempLSSTrigger \| ~LSSTriggerValid)`
176			`& (TempITrigger \| ~ITriggerValid)`
177			`)`
178			`& (WpTriggerValid \| BpTriggerValid \| LSSTriggerValid \| ITriggerValid);`
179
180			`wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)`
181			`\| (TempBpTrigger & BpTriggerValid)`
182			`\| (TempLSSTrigger & LSSTriggerValid)`
183			`\| (TempITrigger & ITriggerValid)`
184			`);`
185
186			`wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any`
187			`TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR`
188			`);`
189
190			`/**********************************************************************************`
191			`* *`
192			`* Generation of the qualifier *`
193			`* *`
194			`**********************************************************************************/`
195			`wire TempWpQualifier = \|(Wp[10:0] & WpQualif[10:0]);`
196			`wire TempBpQualifier = Bp & BpQualif;`
197			`wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];`
198			`wire TempIQualifier = IStatus[1:0] == IQualif[1:0];`
199
200			`wire TempQualifierAND = ( (TempWpQualifier \| ~WpQualifValid)`
201			`& (TempBpQualifier \| ~BpQualifValid)`
202			`& (TempLSSQualifier \| ~LSSQualifValid)`
203			`& (TempIQualifier \| ~IQualifValid)`
204			`)`
205			`& (WpQualifValid \| BpQualifValid \| LSSQualifValid \| IQualifValid);`
206
207			`wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)`
208			`\| (TempBpQualifier & BpQualifValid)`
209			`\| (TempLSSQualifier & LSSQualifValid)`
210			`\| (TempIQualifier & IQualifValid)`
211			`);`
212
213
214			`wire Stop;`
215			`wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any`
216			`QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR`
217			`);`
218
219			`/**********************************************************************************`
220			`* *`
221			`* Generation of the stop signal *`
222			`* *`
223			`**********************************************************************************/`
224			`wire TempWpStop = \|(Wp[10:0] & WpStop[10:0]);`
225			`wire TempBpStop = Bp & BpStop;`
226			`wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];`
227			`wire TempIStop = IStatus[1:0] == IStop[1:0];`
228
229	8	mohor	`wire TempStopAND = ( (TempWpStop \| ~WpStopValid)`
230	2	mohor	`& (TempBpStop \| ~BpStopValid)`
231			`& (TempLSSStop \| ~LSSStopValid)`
232			`& (TempIStop \| ~IStopValid)`
233			`)`
234			`& (WpStopValid \| BpStopValid \| LSSStopValid \| IStopValid);`
235
236	8	mohor	`wire TempStopOR = ( (TempWpStop & WpStopValid)`
237	2	mohor	`\| (TempBpStop & BpStopValid)`
238			`\| (TempLSSStop & LSSStopValid)`
239			`\| (TempIStop & IStopValid)`
240			`);`
241
242
243			`assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing`
244			`StopOper[0]? TempStopAND : TempStopOR // AND : OR`
245			`);`
246
247
248
249			`/**********************************************************************************`
250			`* *`
251			`* Generation of the TriggerLatch *`
252			`* *`
253			`**********************************************************************************/`
254	8	mohor	`always @(posedge Mclk or posedge Reset)`
255	2	mohor	`begin`
256	8	mohor	`if(Reset)`
257	2	mohor	`TriggerLatch<=#Tp 0;`
258			`else`
259	8	mohor	`if(TriggerLatch & ~TraceEnable)`
260			`TriggerLatch<=#Tp 0;`
261			`else`
262	2	mohor	`if(Trigger)`
263			`TriggerLatch<=#Tp 1;`
264			`end`
265
266
267	8	mohor
268
269	2	mohor	`/**********************************************************************************`
270			`* *`
271	8	mohor	`* TraceEnable Synchronization *`
272			`* *`
273			`**********************************************************************************/`
274			`always @(posedge Mclk or posedge Reset)`
275			`begin`
276			`if(Reset)`
277			`begin`
278			`TraceEnable_d<=#Tp 0;`
279			`TraceEnable<=#Tp 0;`
280			`end`
281			`else`
282			`begin`
283			`TraceEnable_d<=#Tp TraceEnable_reg;`
284			`TraceEnable<=#Tp TraceEnable_d;`
285			`end`
286			`end`
287
288
289
290
291			`/**********************************************************************************`
292			`* *`
293	5	mohor	`* RiscStall, counter and pointers generation *`
294	2	mohor	`* *`
295			`**********************************************************************************/`
296			`reg BufferFullDetected;`
297	5	mohor	wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
298	2	mohor
299			wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
300			wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
301	5	mohor	`wire IncrementCounter = RiscStall_q & ~(BufferFull \| BufferFullDetected) & Qualifier & RecEnable[StallCounter];`
302			`wire IncrementPointer = RiscStall_q & (~BufferFull \| ContinMode) & Qualifier & RecEnable[StallCounter];`
303	2	mohor
304			`wire WriteSample = IncrementPointer;`
305
306			`wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode \| ContinMode & ~TraceEnable);`
307			`wire CounterEn = IncrementCounter ^ Decrement;`
308
309	8	mohor	`wire SyncResetCpuStall;`
310	2	mohor	`wire ResetStallCounter;`
311			`reg BufferFull_q;`
312			`reg BufferFull_2q;`
313
314			`reg Qualifier_mclk;`
315
316			`always @(posedge Mclk)`
317			`begin`
318			`Qualifier_mclk<=#Tp Qualifier;`
319			`BufferFull_q<=#Tp BufferFull;`
320			`BufferFull_2q<=#Tp BufferFull_q;`
321	8	mohor	`RiscStall_q <=#Tp RiscStall_O;`
322	2	mohor	`end`
323
324
325	8	mohor	`wire FirstCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch \|`
326			`Qualifier_mclk & Trigger & ~TriggerLatch \|`
327			`Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch ;`
328	2	mohor
329
330	8	mohor	`//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &`
331
332			`wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q \|`
333			`Qualifier_mclk & TriggerLatch &`
334	2	mohor	`(`
335			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
336			`(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) \|`
337			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
338			`);`
339
340	8	mohor	`assign SyncResetCpuStall = (`
341			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) \|
342			(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
343			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
344			`);`
345	2	mohor
346	8	mohor	`assign RiscStall_O = FirstCpuStall \| RiscStall;`
347	2	mohor
348	8	mohor
349	2	mohor	`always @(posedge Mclk or posedge Reset)`
350			`begin`
351			`if(Reset)`
352			`Counter<=#Tp 0;`
353			`else`
354			`if(CounterEn)`
355			`if(IncrementCounter)`
356			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
357			`else`
358			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
359			`end`
360
361
362			`always @(posedge Mclk or posedge Reset)`
363			`begin`
364			`if(Reset)`
365	8	mohor	`WritePointer<=#Tp 0;`
366	2	mohor	`else`
367	8	mohor	`if(IncrementPointer)`
368			WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
369	2	mohor	`end`
370
371	8	mohor	`always @(posedge Mclk or posedge Reset)`
372			`begin`
373			`if(Reset)`
374			`ReadPointer<=#Tp 0;`
375			`else`
376			`if(Decrement & ~ContinMode \| Decrement & ContinMode & ~TraceEnable)`
377			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
378			`else`
379			`if(ContinMode & IncrementPointer & (BufferFull \| BufferFullDetected))`
380			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
381			`end`
382
383	2	mohor	`always @(posedge Mclk)`
384			`begin`
385			`if(~TraceEnable)`
386			`BufferFullDetected<=#Tp 0;`
387			`else`
388			`if(ContinMode & BufferFull)`
389			`BufferFullDetected<=#Tp 1;`
390			`end`
391
392
393	8	mohor	`always @(posedge Mclk or posedge Reset)`
394	2	mohor	`begin`
395	8	mohor	`if(Reset)`
396			`RiscStall<=#Tp 0;`
397	2	mohor	`else`
398	8	mohor	`if(SyncResetCpuStall)`
399			`RiscStall<=#Tp 0;`
400			`else`
401	2	mohor	`if(SyncSetCpuStall)`
402	5	mohor	`RiscStall<=#Tp 1;`
403	2	mohor	`end`
404
405
406			`always @(posedge Mclk)`
407			`begin`
408			`if(ResetStallCounter)`
409			`StallCounter<=#Tp 0;`
410			`else`
411	5	mohor	`if(RiscStall_q & (~BufferFull \| ContinMode))`
412	2	mohor	`StallCounter<=#Tp StallCounter+1;`
413			`end`
414
415			assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull \| Reset;
416
417
418			`/**********************************************************************************`
419			`* *`
420			`* Valid status *`
421			`* *`
422			`**********************************************************************************/`
423			`wire Valid = ~BufferEmpty;`
424
425
426			`/**********************************************************************************`
427			`* *`
428			`* Writing and reading the sample to/from the buffer *`
429			`* *`
430			`**********************************************************************************/`
431			`always @ (posedge Mclk)`
432			`begin`
433			`if(WriteSample)`
434			Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
435			`end`
436
437			`assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};`
438
439
440
441			`/**********************************************************************************`
442			`* *`
443			`* Operation select (to select which kind of data appears on the DATAIN lines) *`
444			`* *`
445			`**********************************************************************************/`
446			assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
447
448
449
450			`/**********************************************************************************`
451			`* *`
452			`* Selecting which parts are going to be recorded as part of the sample *`
453			`* *`
454			`**********************************************************************************/`
455	5	mohor	`assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};`
456	2	mohor
457
458	5	mohor	`endmodule // Trace`

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