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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [jtag_chain.v] - Blame information for rev 36

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1 36 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  jtag_chain.v                                                ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the SoC/OpenRISC Development Interface ////
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////  http://www.opencores.org/projects/DebugInterface/           ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Igor Mohor                                             ////
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////       igorm@opencores.org                                    ////
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////                                                              ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001, 2002 Authors                       ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "dbg_defines.v"
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// Top module
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module jtag_chain   ( capture_dr_i, shift_dr_i, update_dr_i, extest_selected_i,
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                      bs_chain_i,   bs_chain_o
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                    );
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parameter Tp = 1;
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input   capture_dr_i;
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input   shift_dr_i;
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input   update_dr_i;
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input   extest_selected_i;
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input   bs_chain_i;
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output  bs_chain_o;
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assign  bs_chain_o = 0;
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endmodule

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