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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 158

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001, 2002 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
 
                // TAP states
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
 
                // Instructions
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
 
                // TDO from dbg module
                TDOData_dbg, BypassRegister,
 
                // From Boundary Scan Chain
                bs_chain_i
 
              );
 
parameter Tp = 1;
 
// JTAG pins
input   tms_pad_i;                  // JTAG test mode select pad
input   tck_pad_i;                  // JTAG test clock pad
input   trst_pad_i;                 // JTAG test reset pad
input   tdi_pad_i;                  // JTAG test data input pad
output  tdo_pad_o;                  // JTAG test data output pad
output  tdo_padoe_o;                // Output enable for JTAG test data output pad 
 
// TAP states
output  ShiftDR;
output  Exit1DR;
output  UpdateDR;
output  UpdateDR_q;
output  CaptureDR;
 
// Instructions
output  IDCODESelected;
output  CHAIN_SELECTSelected;
output  DEBUGSelected;
output  EXTESTSelected;
 
input   TDOData_dbg;
output  BypassRegister;
 
// From Boundary Scan Chain
input   bs_chain_i;
 
 
reg     tdo_pad_o;
 
// TAP states
reg     TestLogicReset;
reg     RunTestIdle;
reg     SelectDRScan;
reg     CaptureDR;
reg     ShiftDR;
reg     Exit1DR;
reg     PauseDR;
reg     Exit2DR;
reg     UpdateDR;
 
reg     SelectIRScan;
reg     CaptureIR;
reg     ShiftIR;
reg     Exit1IR;
reg     PauseIR;
reg     Exit2IR;
reg     UpdateIR;
 
 
// Defining which instruction is selected
reg     EXTESTSelected;
reg     SAMPLE_PRELOADSelected;
reg     IDCODESelected;
reg     CHAIN_SELECTSelected;
reg     INTESTSelected;
reg     CLAMPSelected;
reg     CLAMPZSelected;
reg     HIGHZSelected;
reg     DEBUGSelected;
reg     BYPASSSelected;
 
reg     BypassRegister;               // Bypass register
 
wire    trst;                         // trst is active high while trst_pad_i is active low
wire    tck;
wire    TMS;
wire    tdi;
 
wire    RiscDebugScanChain;
wire    WishboneScanChain;
wire    RegisterScanChain;
 
 
assign trst = ~trst_pad_i;                // trst_pad_i is active low
assign tck  = tck_pad_i;
assign TMS  = tms_pad_i;
assign tdi  = tdi_pad_i;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
  if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
    RunTestIdle<=#Tp 1;
  else
    RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
  if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
    SelectDRScan<=#Tp 1;
  else
    SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
  if(~TMS & SelectDRScan)
    CaptureDR<=#Tp 1;
  else
    CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
  if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
    ShiftDR<=#Tp 1;
  else
    ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
  if(TMS & (CaptureDR | ShiftDR))
    Exit1DR<=#Tp 1;
  else
    Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
  if(~TMS & (Exit1DR | PauseDR))
    PauseDR<=#Tp 1;
  else
    PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
  if(TMS & PauseDR)
    Exit2DR<=#Tp 1;
  else
    Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
  if(TMS & (Exit1DR | Exit2DR))
    UpdateDR<=#Tp 1;
  else
    UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
  if(TMS & SelectDRScan)
    SelectIRScan<=#Tp 1;
  else
    SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
  if(~TMS & SelectIRScan)
    CaptureIR<=#Tp 1;
  else
    CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
  if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
    ShiftIR<=#Tp 1;
  else
    ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
  if(TMS & (CaptureIR | ShiftIR))
    Exit1IR<=#Tp 1;
  else
    Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
  if(~TMS & (Exit1IR | PauseIR))
    PauseIR<=#Tp 1;
  else
    PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
  if(TMS & PauseIR)
    Exit2IR<=#Tp 1;
  else
    Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
  if(TMS & (Exit1IR | Exit2IR))
    UpdateIR<=#Tp 1;
  else
    UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
  if(CaptureIR)
    begin
      JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
      JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
    end
  else
  if(ShiftIR)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
 
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
    begin
      if(ShiftDR)
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
      else
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
    end
  else
  if(CHAIN_SELECTSelected & ShiftDR)
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
  else
  if(DEBUGSelected & ShiftDR)
    begin
      if(RiscDebugScanChain | WishboneScanChain)
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
      else
      if(RegisterScanChain)
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
    end
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
  if(ShiftDR)
    BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
  TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
begin
  if(ShiftIR | Exit1IR)
    tdo_pad_o <=#Tp TDOInstruction;
  else
    begin
      case(LatchedJTAG_IR)
        `IDCODE:            tdo_pad_o <=#Tp TDOData_dbg;      // Reading ID code
        `CHAIN_SELECT:      tdo_pad_o <=#Tp TDOData_dbg;      // Selecting the chain
        `DEBUG:             tdo_pad_o <=#Tp TDOData_dbg;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o <=#Tp bs_chain_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o <=#Tp bs_chain_i;   // External test
        default:            tdo_pad_o <=#Tp TDOBypassed;  // BYPASS instruction
      endcase
    end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoe_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 158

Line No.	Rev	Author	Line
1	36	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000, 2001, 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	45	mohor	`// Revision 1.5 2002/03/26 14:23:38 mohor`
49			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
50			`//`
51	40	mohor	`// Revision 1.4 2002/03/25 13:16:15 mohor`
52			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
53			`// not named correctly.`
54			`//`
55	39	mohor	`// Revision 1.3 2002/03/12 14:30:05 mohor`
56			`// Few outputs for boundary scan chain added.`
57			`//`
58	38	mohor	`// Revision 1.2 2002/03/12 10:31:53 mohor`
59			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
60			`// contains only tap state machine and related logic. dbg_top contains all`
61			`// logic necessery for debugging.`
62			`//`
63	37	mohor	`// Revision 1.1 2002/03/08 15:28:16 mohor`
64			`// Structure changed. Hooks for jtag chain added.`
65	36	mohor	`//`
66			`//`
67			`//`
68	37	mohor	`//`
69	36	mohor
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "dbg_defines.v"
74
75			`// Top module`
76			`module tap_top(`
77			`// JTAG pins`
78	45	mohor	`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,`
79	36	mohor
80	37	mohor	`// TAP states`
81	38	mohor	`ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,`
82	36	mohor
83	37	mohor	`// Instructions`
84	38	mohor	`IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,`
85	37	mohor
86			`// TDO from dbg module`
87	38	mohor	`TDOData_dbg, BypassRegister,`
88
89			`// From Boundary Scan Chain`
90			`bs_chain_i`
91
92	36	mohor	`);`
93
94			`parameter Tp = 1;`
95
96			`// JTAG pins`
97			`input tms_pad_i; // JTAG test mode select pad`
98			`input tck_pad_i; // JTAG test clock pad`
99			`input trst_pad_i; // JTAG test reset pad`
100			`input tdi_pad_i; // JTAG test data input pad`
101			`output tdo_pad_o; // JTAG test data output pad`
102	45	mohor	`output tdo_padoe_o; // Output enable for JTAG test data output pad`
103	36	mohor
104	37	mohor	`// TAP states`
105			`output ShiftDR;`
106			`output Exit1DR;`
107			`output UpdateDR;`
108			`output UpdateDR_q;`
109	38	mohor	`output CaptureDR;`
110	36	mohor
111	37	mohor	`// Instructions`
112			`output IDCODESelected;`
113			`output CHAIN_SELECTSelected;`
114			`output DEBUGSelected;`
115	38	mohor	`output EXTESTSelected;`
116	36	mohor
117	37	mohor	`input TDOData_dbg;`
118			`output BypassRegister;`
119	36	mohor
120	38	mohor	`// From Boundary Scan Chain`
121			`input bs_chain_i;`
122
123
124	36	mohor	`reg tdo_pad_o;`
125
126			`// TAP states`
127			`reg TestLogicReset;`
128			`reg RunTestIdle;`
129			`reg SelectDRScan;`
130			`reg CaptureDR;`
131			`reg ShiftDR;`
132			`reg Exit1DR;`
133			`reg PauseDR;`
134			`reg Exit2DR;`
135			`reg UpdateDR;`
136
137			`reg SelectIRScan;`
138			`reg CaptureIR;`
139			`reg ShiftIR;`
140			`reg Exit1IR;`
141			`reg PauseIR;`
142			`reg Exit2IR;`
143			`reg UpdateIR;`
144
145
146			`// Defining which instruction is selected`
147			`reg EXTESTSelected;`
148			`reg SAMPLE_PRELOADSelected;`
149			`reg IDCODESelected;`
150			`reg CHAIN_SELECTSelected;`
151			`reg INTESTSelected;`
152			`reg CLAMPSelected;`
153			`reg CLAMPZSelected;`
154			`reg HIGHZSelected;`
155			`reg DEBUGSelected;`
156			`reg BYPASSSelected;`
157
158			`reg BypassRegister; // Bypass register`
159
160			`wire trst; // trst is active high while trst_pad_i is active low`
161			`wire tck;`
162			`wire TMS;`
163			`wire tdi;`
164
165			`wire RiscDebugScanChain;`
166			`wire WishboneScanChain;`
167			`wire RegisterScanChain;`
168
169
170			`assign trst = ~trst_pad_i; // trst_pad_i is active low`
171			`assign tck = tck_pad_i;`
172			`assign TMS = tms_pad_i;`
173			`assign tdi = tdi_pad_i;`
174
175
176			`/**********************************************************************************`
177			`* *`
178			`* TAP State Machine: Fully JTAG compliant *`
179			`* *`
180			`**********************************************************************************/`
181
182			`// TestLogicReset state`
183			`always @ (posedge tck or posedge trst)`
184			`begin`
185			`if(trst)`
186			`TestLogicReset<=#Tp 1;`
187			`else`
188			`begin`
189			`if(TMS & (TestLogicReset \| SelectIRScan))`
190			`TestLogicReset<=#Tp 1;`
191			`else`
192			`TestLogicReset<=#Tp 0;`
193			`end`
194			`end`
195
196			`// RunTestIdle state`
197			`always @ (posedge tck or posedge trst)`
198			`begin`
199			`if(trst)`
200			`RunTestIdle<=#Tp 0;`
201			`else`
202			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
203			`RunTestIdle<=#Tp 1;`
204			`else`
205			`RunTestIdle<=#Tp 0;`
206			`end`
207
208			`// SelectDRScan state`
209			`always @ (posedge tck or posedge trst)`
210			`begin`
211			`if(trst)`
212			`SelectDRScan<=#Tp 0;`
213			`else`
214			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
215			`SelectDRScan<=#Tp 1;`
216			`else`
217			`SelectDRScan<=#Tp 0;`
218			`end`
219
220			`// CaptureDR state`
221			`always @ (posedge tck or posedge trst)`
222			`begin`
223			`if(trst)`
224			`CaptureDR<=#Tp 0;`
225			`else`
226			`if(~TMS & SelectDRScan)`
227			`CaptureDR<=#Tp 1;`
228			`else`
229			`CaptureDR<=#Tp 0;`
230			`end`
231
232			`// ShiftDR state`
233			`always @ (posedge tck or posedge trst)`
234			`begin`
235			`if(trst)`
236			`ShiftDR<=#Tp 0;`
237			`else`
238			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
239			`ShiftDR<=#Tp 1;`
240			`else`
241			`ShiftDR<=#Tp 0;`
242			`end`
243
244			`// Exit1DR state`
245			`always @ (posedge tck or posedge trst)`
246			`begin`
247			`if(trst)`
248			`Exit1DR<=#Tp 0;`
249			`else`
250			`if(TMS & (CaptureDR \| ShiftDR))`
251			`Exit1DR<=#Tp 1;`
252			`else`
253			`Exit1DR<=#Tp 0;`
254			`end`
255
256			`// PauseDR state`
257			`always @ (posedge tck or posedge trst)`
258			`begin`
259			`if(trst)`
260			`PauseDR<=#Tp 0;`
261			`else`
262			`if(~TMS & (Exit1DR \| PauseDR))`
263			`PauseDR<=#Tp 1;`
264			`else`
265			`PauseDR<=#Tp 0;`
266			`end`
267
268			`// Exit2DR state`
269			`always @ (posedge tck or posedge trst)`
270			`begin`
271			`if(trst)`
272			`Exit2DR<=#Tp 0;`
273			`else`
274			`if(TMS & PauseDR)`
275			`Exit2DR<=#Tp 1;`
276			`else`
277			`Exit2DR<=#Tp 0;`
278			`end`
279
280			`// UpdateDR state`
281			`always @ (posedge tck or posedge trst)`
282			`begin`
283			`if(trst)`
284			`UpdateDR<=#Tp 0;`
285			`else`
286			`if(TMS & (Exit1DR \| Exit2DR))`
287			`UpdateDR<=#Tp 1;`
288			`else`
289			`UpdateDR<=#Tp 0;`
290			`end`
291
292			`// Delayed UpdateDR state`
293			`reg UpdateDR_q;`
294			`always @ (posedge tck)`
295			`begin`
296			`UpdateDR_q<=#Tp UpdateDR;`
297			`end`
298
299			`// SelectIRScan state`
300			`always @ (posedge tck or posedge trst)`
301			`begin`
302			`if(trst)`
303			`SelectIRScan<=#Tp 0;`
304			`else`
305			`if(TMS & SelectDRScan)`
306			`SelectIRScan<=#Tp 1;`
307			`else`
308			`SelectIRScan<=#Tp 0;`
309			`end`
310
311			`// CaptureIR state`
312			`always @ (posedge tck or posedge trst)`
313			`begin`
314			`if(trst)`
315			`CaptureIR<=#Tp 0;`
316			`else`
317			`if(~TMS & SelectIRScan)`
318			`CaptureIR<=#Tp 1;`
319			`else`
320			`CaptureIR<=#Tp 0;`
321			`end`
322
323			`// ShiftIR state`
324			`always @ (posedge tck or posedge trst)`
325			`begin`
326			`if(trst)`
327			`ShiftIR<=#Tp 0;`
328			`else`
329			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
330			`ShiftIR<=#Tp 1;`
331			`else`
332			`ShiftIR<=#Tp 0;`
333			`end`
334
335			`// Exit1IR state`
336			`always @ (posedge tck or posedge trst)`
337			`begin`
338			`if(trst)`
339			`Exit1IR<=#Tp 0;`
340			`else`
341			`if(TMS & (CaptureIR \| ShiftIR))`
342			`Exit1IR<=#Tp 1;`
343			`else`
344			`Exit1IR<=#Tp 0;`
345			`end`
346
347			`// PauseIR state`
348			`always @ (posedge tck or posedge trst)`
349			`begin`
350			`if(trst)`
351			`PauseIR<=#Tp 0;`
352			`else`
353			`if(~TMS & (Exit1IR \| PauseIR))`
354			`PauseIR<=#Tp 1;`
355			`else`
356			`PauseIR<=#Tp 0;`
357			`end`
358
359			`// Exit2IR state`
360			`always @ (posedge tck or posedge trst)`
361			`begin`
362			`if(trst)`
363			`Exit2IR<=#Tp 0;`
364			`else`
365			`if(TMS & PauseIR)`
366			`Exit2IR<=#Tp 1;`
367			`else`
368			`Exit2IR<=#Tp 0;`
369			`end`
370
371			`// UpdateIR state`
372			`always @ (posedge tck or posedge trst)`
373			`begin`
374			`if(trst)`
375			`UpdateIR<=#Tp 0;`
376			`else`
377			`if(TMS & (Exit1IR \| Exit2IR))`
378			`UpdateIR<=#Tp 1;`
379			`else`
380			`UpdateIR<=#Tp 0;`
381			`end`
382
383			`/**********************************************************************************`
384			`* *`
385			`* End: TAP State Machine *`
386			`* *`
387			`**********************************************************************************/`
388
389
390
391			`/**********************************************************************************`
392			`* *`
393			`* JTAG_IR: JTAG Instruction Register *`
394			`* *`
395			`**********************************************************************************/`
396			`wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.`
397
398			reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
399			reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
400
401			`reg TDOInstruction;`
402
403			`always @ (posedge tck or posedge trst)`
404			`begin`
405			`if(trst)`
406			JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
407			`else`
408			`if(CaptureIR)`
409			`begin`
410			`JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection`
411			`JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip`
412			`end`
413			`else`
414			`if(ShiftIR)`
415			JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
416			`end`
417
418
419			`//TDO is changing on the falling edge of tck`
420			`always @ (negedge tck)`
421			`begin`
422			`if(ShiftIR)`
423			`TDOInstruction <= #Tp JTAG_IR[0];`
424			`end`
425
426			`/**********************************************************************************`
427			`* *`
428			`* End: JTAG_IR *`
429			`* *`
430			`**********************************************************************************/`
431
432
433			`/**********************************************************************************`
434			`* *`
435			`* JTAG_DR: JTAG Data Register *`
436			`* *`
437			`**********************************************************************************/`
438			reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
439
440
441			`always @ (posedge tck or posedge trst)`
442			`begin`
443			`if(trst)`
444			JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
445			`else`
446			`if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE`
447			`begin`
448			`if(ShiftDR)`
449			`JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};`
450			`else`
451			JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
452			`end`
453			`else`
454			`if(CHAIN_SELECTSelected & ShiftDR)`
455			`JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};`
456			`else`
457			`if(DEBUGSelected & ShiftDR)`
458			`begin`
459			`if(RiscDebugScanChain \| WishboneScanChain)`
460			`JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};`
461			`else`
462			`if(RegisterScanChain)`
463			`JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};`
464			`end`
465			`end`
466
467
468
469			`/**********************************************************************************`
470			`* *`
471			`* End: JTAG_DR *`
472			`* *`
473			`**********************************************************************************/`
474
475
476
477
478
479			`/**********************************************************************************`
480			`* *`
481			`* Bypass logic *`
482			`* *`
483			`**********************************************************************************/`
484			`reg TDOBypassed;`
485
486			`always @ (posedge tck)`
487			`begin`
488			`if(ShiftDR)`
489			`BypassRegister<=#Tp tdi;`
490			`end`
491
492			`always @ (negedge tck)`
493			`begin`
494			`TDOBypassed<=#Tp BypassRegister;`
495			`end`
496			`/**********************************************************************************`
497			`* *`
498			`* End: Bypass logic *`
499			`* *`
500			`**********************************************************************************/`
501
502
503
504
505
506			`/**********************************************************************************`
507			`* *`
508			`* Activating Instructions *`
509			`* *`
510			`**********************************************************************************/`
511
512			`// Updating JTAG_IR (Instruction Register)`
513			`always @ (posedge tck or posedge trst)`
514			`begin`
515			`if(trst)`
516			LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
517			`else`
518			`if(UpdateIR)`
519			`LatchedJTAG_IR <=#Tp JTAG_IR;`
520			`end`
521
522			`/**********************************************************************************`
523			`* *`
524			`* End: Activating Instructions *`
525			`* *`
526			`**********************************************************************************/`
527
528
529			`// Updating JTAG_IR (Instruction Register)`
530			`always @ (LatchedJTAG_IR)`
531			`begin`
532			`EXTESTSelected = 0;`
533			`SAMPLE_PRELOADSelected = 0;`
534			`IDCODESelected = 0;`
535			`CHAIN_SELECTSelected = 0;`
536			`INTESTSelected = 0;`
537			`CLAMPSelected = 0;`
538			`CLAMPZSelected = 0;`
539			`HIGHZSelected = 0;`
540			`DEBUGSelected = 0;`
541			`BYPASSSelected = 0;`
542
543			`case(LatchedJTAG_IR)`
544			`EXTEST: EXTESTSelected = 1; // External test
545			`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
546			`IDCODE: IDCODESelected = 1; // ID Code
547			`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
548			`INTEST: INTESTSelected = 1; // Internal test
549			`CLAMP: CLAMPSelected = 1; // Clamp
550			`CLAMPZ: CLAMPZSelected = 1; // ClampZ
551			`HIGHZ: HIGHZSelected = 1; // High Z
552			`DEBUG: DEBUGSelected = 1; // Debug
553			`BYPASS: BYPASSSelected = 1; // BYPASS
554			`default: BYPASSSelected = 1; // BYPASS`
555			`endcase`
556			`end`
557
558
559
560			`/**********************************************************************************`
561			`* *`
562			`* Multiplexing TDO data *`
563			`* *`
564			`**********************************************************************************/`
565
566			`// This multiplexer can be expanded with number of user registers`
567	38	mohor	`always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)`
568	36	mohor	`begin`
569			`if(ShiftIR \| Exit1IR)`
570			`tdo_pad_o <=#Tp TDOInstruction;`
571			`else`
572			`begin`
573			`case(LatchedJTAG_IR)`
574	37	mohor	`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
575			`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
576			`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
577	38	mohor	`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
578			`EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
579	36	mohor	`default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction`
580			`endcase`
581			`end`
582			`end`
583
584			`// Tristate control for tdo_pad_o pin`
585	45	mohor	`assign tdo_padoe_o = ShiftIR \| ShiftDR \| Exit1IR \| Exit1DR \| UpdateDR;`
586	36	mohor
587			`/**********************************************************************************`
588			`* *`
589			`* End: Multiplexing TDO data *`
590			`* *`
591			`**********************************************************************************/`
592
593			`endmodule`