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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001, 2002 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
 
                // RISC signals
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
              );
 
parameter Tp = 1;
 
// JTAG pins
input   tms_pad_i;                  // JTAG test mode select pad
input   tck_pad_i;                  // JTAG test clock pad
input   trst_pad_i;                 // JTAG test reset pad
input   tdi_pad_i;                  // JTAG test data input pad
output  tdo_pad_o;                  // JTAG test data output pad
output  tdo_padoen_o;               // Output enable for JTAG test data output pad 
 
 
// RISC signals
input         risc_clk_i;                 // Master clock (RISC clock)
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
input  [10:0] wp_i;                       // Watchpoint inputs
input         bp_i;                       // Breakpoint input
input  [3:0]  lsstatus_i;                 // Load/store status inputs
input  [1:0]  istatus_i;                  // Instruction status inputs
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
output                      risc_stall_o; // Stalls the RISC
output                      reset_o;      // Resets the RISC
 
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
 
 
reg     tdo_pad_o;
 
// TAP states
reg     TestLogicReset;
reg     RunTestIdle;
reg     SelectDRScan;
reg     CaptureDR;
reg     ShiftDR;
reg     Exit1DR;
reg     PauseDR;
reg     Exit2DR;
reg     UpdateDR;
 
reg     SelectIRScan;
reg     CaptureIR;
reg     ShiftIR;
reg     Exit1IR;
reg     PauseIR;
reg     Exit2IR;
reg     UpdateIR;
 
 
// Defining which instruction is selected
reg     EXTESTSelected;
reg     SAMPLE_PRELOADSelected;
reg     IDCODESelected;
reg     CHAIN_SELECTSelected;
reg     INTESTSelected;
reg     CLAMPSelected;
reg     CLAMPZSelected;
reg     HIGHZSelected;
reg     DEBUGSelected;
reg     BYPASSSelected;
 
reg     BypassRegister;               // Bypass register
 
wire    trst;                         // trst is active high while trst_pad_i is active low
wire    tck;
wire    TMS;
wire    tdi;
wire    TDOData;
 
wire    RiscDebugScanChain;
wire    WishboneScanChain;
wire    RegisterScanChain;
wire    bs_chain_o;
 
 
assign trst = ~trst_pad_i;                // trst_pad_i is active low
assign tck  = tck_pad_i;
assign TMS  = tms_pad_i;
assign tdi  = tdi_pad_i;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
  if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
    RunTestIdle<=#Tp 1;
  else
    RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
  if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
    SelectDRScan<=#Tp 1;
  else
    SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
  if(~TMS & SelectDRScan)
    CaptureDR<=#Tp 1;
  else
    CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
  if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
    ShiftDR<=#Tp 1;
  else
    ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
  if(TMS & (CaptureDR | ShiftDR))
    Exit1DR<=#Tp 1;
  else
    Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
  if(~TMS & (Exit1DR | PauseDR))
    PauseDR<=#Tp 1;
  else
    PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
  if(TMS & PauseDR)
    Exit2DR<=#Tp 1;
  else
    Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
  if(TMS & (Exit1DR | Exit2DR))
    UpdateDR<=#Tp 1;
  else
    UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
  if(TMS & SelectDRScan)
    SelectIRScan<=#Tp 1;
  else
    SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
  if(~TMS & SelectIRScan)
    CaptureIR<=#Tp 1;
  else
    CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
  if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
    ShiftIR<=#Tp 1;
  else
    ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
  if(TMS & (CaptureIR | ShiftIR))
    Exit1IR<=#Tp 1;
  else
    Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
  if(~TMS & (Exit1IR | PauseIR))
    PauseIR<=#Tp 1;
  else
    PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
  if(TMS & PauseIR)
    Exit2IR<=#Tp 1;
  else
    Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
  if(TMS & (Exit1IR | Exit2IR))
    UpdateIR<=#Tp 1;
  else
    UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
  if(CaptureIR)
    begin
      JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
      JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
    end
  else
  if(ShiftIR)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
 
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
    begin
      if(ShiftDR)
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
      else
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
    end
  else
  if(CHAIN_SELECTSelected & ShiftDR)
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
  else
  if(DEBUGSelected & ShiftDR)
    begin
      if(RiscDebugScanChain | WishboneScanChain)
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
      else
      if(RegisterScanChain)
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
    end
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
  if(ShiftDR)
    BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
  TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData or TDOBypassed or bs_chain_o or ShiftIR or Exit1IR)
begin
  if(ShiftIR | Exit1IR)
    tdo_pad_o <=#Tp TDOInstruction;
  else
    begin
      case(LatchedJTAG_IR)
        `IDCODE:            tdo_pad_o <=#Tp TDOData;      // Reading ID code
        `CHAIN_SELECT:      tdo_pad_o <=#Tp TDOData;      // Selecting the chain
        `DEBUG:             tdo_pad_o <=#Tp TDOData;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o <=#Tp bs_chain_o;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o <=#Tp bs_chain_o;   // External test
        default:            tdo_pad_o <=#Tp TDOBypassed;  // BYPASS instruction
      endcase
    end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
 
 
 
// Connecting dbg_top module
dbg_top i_dbg_top (
                    // RISC signals
                    .risc_clk_i(risc_clk_i),      .risc_addr_o(risc_addr_o),  .risc_data_i(risc_data_i),
                    .risc_data_o(risc_data_o),    .wp_i(wp_i),                .bp_i(bp_i),
                    .opselect_o(opselect_o),      .lsstatus_i(lsstatus_i),    .istatus_i(istatus_i),
                    .risc_stall_o(risc_stall_o),  .reset_o(reset_o),
 
                    // WISHBONE common signals
                    .wb_rst_i(wb_rst_i),          .wb_clk_i(wb_clk_i),
 
                    // WISHBONE master interface
                    .wb_adr_o(wb_adr_o),          .wb_dat_o(wb_dat_o),        .wb_dat_i(wb_dat_i),
                    .wb_cyc_o(wb_cyc_o),          .wb_stb_o(wb_stb_o),        .wb_sel_o(wb_sel_o),
                    .wb_we_o(wb_we_o),            .wb_ack_i(wb_ack_i),        .wb_cab_o(wb_cab_o),
                    .wb_err_i(wb_err_i),
 
                    // TAP states
                    .ShiftDR(ShiftDR),            .Exit1DR(Exit1DR),          .UpdateDR(UpdateDR),
                    .UpdateDR_q(UpdateDR_q),
 
                    // Instructions
                    .IDCODESelected(IDCODESelected),
                    .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
                    .DEBUGSelected(DEBUGSelected),
 
                    // TAP signals
                    .trst(trst),                  .tck(tck),                  .tdi(tdi),
                    .TDOData(TDOData),
 
                    .BypassRegister(BypassRegister)
 
                  );
 
 
 
// Connecting bender_jtag module
jtag_chain i_jtag_chain   (
                            .capture_dr_i(CaptureDR),           .shift_dr_i(ShiftDR),
                            .update_dr_i(UpdateDR),             .extest_selected_i(EXTESTSelected),
                            .bs_chain_i(tdi),                   .bs_chain_o(bs_chain_o)
                          );
 
endmodule

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 36

Line No.	Rev	Author	Line
1	36	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000, 2001, 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49			`//`
50			`//`
51
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "dbg_defines.v"
56
57			`// Top module`
58			`module tap_top(`
59			`// JTAG pins`
60			`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,`
61
62			`// RISC signals`
63			`risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,`
64			`bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,`
65
66			`// WISHBONE common signals`
67			`wb_rst_i, wb_clk_i,`
68
69			`// WISHBONE master interface`
70			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
71			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i`
72			`);`
73
74			`parameter Tp = 1;`
75
76			`// JTAG pins`
77			`input tms_pad_i; // JTAG test mode select pad`
78			`input tck_pad_i; // JTAG test clock pad`
79			`input trst_pad_i; // JTAG test reset pad`
80			`input tdi_pad_i; // JTAG test data input pad`
81			`output tdo_pad_o; // JTAG test data output pad`
82			`output tdo_padoen_o; // Output enable for JTAG test data output pad`
83
84
85			`// RISC signals`
86			`input risc_clk_i; // Master clock (RISC clock)`
87			`input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)`
88			`input [10:0] wp_i; // Watchpoint inputs`
89			`input bp_i; // Breakpoint input`
90			`input [3:0] lsstatus_i; // Load/store status inputs`
91			`input [1:0] istatus_i; // Instruction status inputs`
92			`output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)`
93			`output [31:0] risc_data_o; // RISC data output (data read from risc registers)`
94			output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
95			`output risc_stall_o; // Stalls the RISC`
96			`output reset_o; // Resets the RISC`
97
98
99			`// WISHBONE common signals`
100			`input wb_rst_i; // WISHBONE reset`
101			`input wb_clk_i; // WISHBONE clock`
102
103			`// WISHBONE master interface`
104			`output [31:0] wb_adr_o;`
105			`output [31:0] wb_dat_o;`
106			`input [31:0] wb_dat_i;`
107			`output wb_cyc_o;`
108			`output wb_stb_o;`
109			`output [3:0] wb_sel_o;`
110			`output wb_we_o;`
111			`input wb_ack_i;`
112			`output wb_cab_o;`
113			`input wb_err_i;`
114
115
116			`reg tdo_pad_o;`
117
118			`// TAP states`
119			`reg TestLogicReset;`
120			`reg RunTestIdle;`
121			`reg SelectDRScan;`
122			`reg CaptureDR;`
123			`reg ShiftDR;`
124			`reg Exit1DR;`
125			`reg PauseDR;`
126			`reg Exit2DR;`
127			`reg UpdateDR;`
128
129			`reg SelectIRScan;`
130			`reg CaptureIR;`
131			`reg ShiftIR;`
132			`reg Exit1IR;`
133			`reg PauseIR;`
134			`reg Exit2IR;`
135			`reg UpdateIR;`
136
137
138			`// Defining which instruction is selected`
139			`reg EXTESTSelected;`
140			`reg SAMPLE_PRELOADSelected;`
141			`reg IDCODESelected;`
142			`reg CHAIN_SELECTSelected;`
143			`reg INTESTSelected;`
144			`reg CLAMPSelected;`
145			`reg CLAMPZSelected;`
146			`reg HIGHZSelected;`
147			`reg DEBUGSelected;`
148			`reg BYPASSSelected;`
149
150			`reg BypassRegister; // Bypass register`
151
152			`wire trst; // trst is active high while trst_pad_i is active low`
153			`wire tck;`
154			`wire TMS;`
155			`wire tdi;`
156			`wire TDOData;`
157
158			`wire RiscDebugScanChain;`
159			`wire WishboneScanChain;`
160			`wire RegisterScanChain;`
161			`wire bs_chain_o;`
162
163
164			`assign trst = ~trst_pad_i; // trst_pad_i is active low`
165			`assign tck = tck_pad_i;`
166			`assign TMS = tms_pad_i;`
167			`assign tdi = tdi_pad_i;`
168
169
170			`/**********************************************************************************`
171			`* *`
172			`* TAP State Machine: Fully JTAG compliant *`
173			`* *`
174			`**********************************************************************************/`
175
176			`// TestLogicReset state`
177			`always @ (posedge tck or posedge trst)`
178			`begin`
179			`if(trst)`
180			`TestLogicReset<=#Tp 1;`
181			`else`
182			`begin`
183			`if(TMS & (TestLogicReset \| SelectIRScan))`
184			`TestLogicReset<=#Tp 1;`
185			`else`
186			`TestLogicReset<=#Tp 0;`
187			`end`
188			`end`
189
190			`// RunTestIdle state`
191			`always @ (posedge tck or posedge trst)`
192			`begin`
193			`if(trst)`
194			`RunTestIdle<=#Tp 0;`
195			`else`
196			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
197			`RunTestIdle<=#Tp 1;`
198			`else`
199			`RunTestIdle<=#Tp 0;`
200			`end`
201
202			`// SelectDRScan state`
203			`always @ (posedge tck or posedge trst)`
204			`begin`
205			`if(trst)`
206			`SelectDRScan<=#Tp 0;`
207			`else`
208			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
209			`SelectDRScan<=#Tp 1;`
210			`else`
211			`SelectDRScan<=#Tp 0;`
212			`end`
213
214			`// CaptureDR state`
215			`always @ (posedge tck or posedge trst)`
216			`begin`
217			`if(trst)`
218			`CaptureDR<=#Tp 0;`
219			`else`
220			`if(~TMS & SelectDRScan)`
221			`CaptureDR<=#Tp 1;`
222			`else`
223			`CaptureDR<=#Tp 0;`
224			`end`
225
226			`// ShiftDR state`
227			`always @ (posedge tck or posedge trst)`
228			`begin`
229			`if(trst)`
230			`ShiftDR<=#Tp 0;`
231			`else`
232			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
233			`ShiftDR<=#Tp 1;`
234			`else`
235			`ShiftDR<=#Tp 0;`
236			`end`
237
238			`// Exit1DR state`
239			`always @ (posedge tck or posedge trst)`
240			`begin`
241			`if(trst)`
242			`Exit1DR<=#Tp 0;`
243			`else`
244			`if(TMS & (CaptureDR \| ShiftDR))`
245			`Exit1DR<=#Tp 1;`
246			`else`
247			`Exit1DR<=#Tp 0;`
248			`end`
249
250			`// PauseDR state`
251			`always @ (posedge tck or posedge trst)`
252			`begin`
253			`if(trst)`
254			`PauseDR<=#Tp 0;`
255			`else`
256			`if(~TMS & (Exit1DR \| PauseDR))`
257			`PauseDR<=#Tp 1;`
258			`else`
259			`PauseDR<=#Tp 0;`
260			`end`
261
262			`// Exit2DR state`
263			`always @ (posedge tck or posedge trst)`
264			`begin`
265			`if(trst)`
266			`Exit2DR<=#Tp 0;`
267			`else`
268			`if(TMS & PauseDR)`
269			`Exit2DR<=#Tp 1;`
270			`else`
271			`Exit2DR<=#Tp 0;`
272			`end`
273
274			`// UpdateDR state`
275			`always @ (posedge tck or posedge trst)`
276			`begin`
277			`if(trst)`
278			`UpdateDR<=#Tp 0;`
279			`else`
280			`if(TMS & (Exit1DR \| Exit2DR))`
281			`UpdateDR<=#Tp 1;`
282			`else`
283			`UpdateDR<=#Tp 0;`
284			`end`
285
286			`// Delayed UpdateDR state`
287			`reg UpdateDR_q;`
288			`always @ (posedge tck)`
289			`begin`
290			`UpdateDR_q<=#Tp UpdateDR;`
291			`end`
292
293			`// SelectIRScan state`
294			`always @ (posedge tck or posedge trst)`
295			`begin`
296			`if(trst)`
297			`SelectIRScan<=#Tp 0;`
298			`else`
299			`if(TMS & SelectDRScan)`
300			`SelectIRScan<=#Tp 1;`
301			`else`
302			`SelectIRScan<=#Tp 0;`
303			`end`
304
305			`// CaptureIR state`
306			`always @ (posedge tck or posedge trst)`
307			`begin`
308			`if(trst)`
309			`CaptureIR<=#Tp 0;`
310			`else`
311			`if(~TMS & SelectIRScan)`
312			`CaptureIR<=#Tp 1;`
313			`else`
314			`CaptureIR<=#Tp 0;`
315			`end`
316
317			`// ShiftIR state`
318			`always @ (posedge tck or posedge trst)`
319			`begin`
320			`if(trst)`
321			`ShiftIR<=#Tp 0;`
322			`else`
323			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
324			`ShiftIR<=#Tp 1;`
325			`else`
326			`ShiftIR<=#Tp 0;`
327			`end`
328
329			`// Exit1IR state`
330			`always @ (posedge tck or posedge trst)`
331			`begin`
332			`if(trst)`
333			`Exit1IR<=#Tp 0;`
334			`else`
335			`if(TMS & (CaptureIR \| ShiftIR))`
336			`Exit1IR<=#Tp 1;`
337			`else`
338			`Exit1IR<=#Tp 0;`
339			`end`
340
341			`// PauseIR state`
342			`always @ (posedge tck or posedge trst)`
343			`begin`
344			`if(trst)`
345			`PauseIR<=#Tp 0;`
346			`else`
347			`if(~TMS & (Exit1IR \| PauseIR))`
348			`PauseIR<=#Tp 1;`
349			`else`
350			`PauseIR<=#Tp 0;`
351			`end`
352
353			`// Exit2IR state`
354			`always @ (posedge tck or posedge trst)`
355			`begin`
356			`if(trst)`
357			`Exit2IR<=#Tp 0;`
358			`else`
359			`if(TMS & PauseIR)`
360			`Exit2IR<=#Tp 1;`
361			`else`
362			`Exit2IR<=#Tp 0;`
363			`end`
364
365			`// UpdateIR state`
366			`always @ (posedge tck or posedge trst)`
367			`begin`
368			`if(trst)`
369			`UpdateIR<=#Tp 0;`
370			`else`
371			`if(TMS & (Exit1IR \| Exit2IR))`
372			`UpdateIR<=#Tp 1;`
373			`else`
374			`UpdateIR<=#Tp 0;`
375			`end`
376
377			`/**********************************************************************************`
378			`* *`
379			`* End: TAP State Machine *`
380			`* *`
381			`**********************************************************************************/`
382
383
384
385			`/**********************************************************************************`
386			`* *`
387			`* JTAG_IR: JTAG Instruction Register *`
388			`* *`
389			`**********************************************************************************/`
390			`wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.`
391
392			reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
393			reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
394
395			`reg TDOInstruction;`
396
397			`always @ (posedge tck or posedge trst)`
398			`begin`
399			`if(trst)`
400			JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
401			`else`
402			`if(CaptureIR)`
403			`begin`
404			`JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection`
405			`JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip`
406			`end`
407			`else`
408			`if(ShiftIR)`
409			JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
410			`end`
411
412
413			`//TDO is changing on the falling edge of tck`
414			`always @ (negedge tck)`
415			`begin`
416			`if(ShiftIR)`
417			`TDOInstruction <= #Tp JTAG_IR[0];`
418			`end`
419
420			`/**********************************************************************************`
421			`* *`
422			`* End: JTAG_IR *`
423			`* *`
424			`**********************************************************************************/`
425
426
427			`/**********************************************************************************`
428			`* *`
429			`* JTAG_DR: JTAG Data Register *`
430			`* *`
431			`**********************************************************************************/`
432			reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
433
434
435			`always @ (posedge tck or posedge trst)`
436			`begin`
437			`if(trst)`
438			JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
439			`else`
440			`if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE`
441			`begin`
442			`if(ShiftDR)`
443			`JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};`
444			`else`
445			JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
446			`end`
447			`else`
448			`if(CHAIN_SELECTSelected & ShiftDR)`
449			`JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};`
450			`else`
451			`if(DEBUGSelected & ShiftDR)`
452			`begin`
453			`if(RiscDebugScanChain \| WishboneScanChain)`
454			`JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};`
455			`else`
456			`if(RegisterScanChain)`
457			`JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};`
458			`end`
459			`end`
460
461
462
463			`/**********************************************************************************`
464			`* *`
465			`* End: JTAG_DR *`
466			`* *`
467			`**********************************************************************************/`
468
469
470
471
472
473			`/**********************************************************************************`
474			`* *`
475			`* Bypass logic *`
476			`* *`
477			`**********************************************************************************/`
478			`reg TDOBypassed;`
479
480			`always @ (posedge tck)`
481			`begin`
482			`if(ShiftDR)`
483			`BypassRegister<=#Tp tdi;`
484			`end`
485
486			`always @ (negedge tck)`
487			`begin`
488			`TDOBypassed<=#Tp BypassRegister;`
489			`end`
490			`/**********************************************************************************`
491			`* *`
492			`* End: Bypass logic *`
493			`* *`
494			`**********************************************************************************/`
495
496
497
498
499
500			`/**********************************************************************************`
501			`* *`
502			`* Activating Instructions *`
503			`* *`
504			`**********************************************************************************/`
505
506			`// Updating JTAG_IR (Instruction Register)`
507			`always @ (posedge tck or posedge trst)`
508			`begin`
509			`if(trst)`
510			LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
511			`else`
512			`if(UpdateIR)`
513			`LatchedJTAG_IR <=#Tp JTAG_IR;`
514			`end`
515
516			`/**********************************************************************************`
517			`* *`
518			`* End: Activating Instructions *`
519			`* *`
520			`**********************************************************************************/`
521
522
523			`// Updating JTAG_IR (Instruction Register)`
524			`always @ (LatchedJTAG_IR)`
525			`begin`
526			`EXTESTSelected = 0;`
527			`SAMPLE_PRELOADSelected = 0;`
528			`IDCODESelected = 0;`
529			`CHAIN_SELECTSelected = 0;`
530			`INTESTSelected = 0;`
531			`CLAMPSelected = 0;`
532			`CLAMPZSelected = 0;`
533			`HIGHZSelected = 0;`
534			`DEBUGSelected = 0;`
535			`BYPASSSelected = 0;`
536
537			`case(LatchedJTAG_IR)`
538			`EXTEST: EXTESTSelected = 1; // External test
539			`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
540			`IDCODE: IDCODESelected = 1; // ID Code
541			`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
542			`INTEST: INTESTSelected = 1; // Internal test
543			`CLAMP: CLAMPSelected = 1; // Clamp
544			`CLAMPZ: CLAMPZSelected = 1; // ClampZ
545			`HIGHZ: HIGHZSelected = 1; // High Z
546			`DEBUG: DEBUGSelected = 1; // Debug
547			`BYPASS: BYPASSSelected = 1; // BYPASS
548			`default: BYPASSSelected = 1; // BYPASS`
549			`endcase`
550			`end`
551
552
553
554			`/**********************************************************************************`
555			`* *`
556			`* Multiplexing TDO data *`
557			`* *`
558			`**********************************************************************************/`
559
560			`// This multiplexer can be expanded with number of user registers`
561			`always @ (LatchedJTAG_IR or TDOInstruction or TDOData or TDOBypassed or bs_chain_o or ShiftIR or Exit1IR)`
562			`begin`
563			`if(ShiftIR \| Exit1IR)`
564			`tdo_pad_o <=#Tp TDOInstruction;`
565			`else`
566			`begin`
567			`case(LatchedJTAG_IR)`
568			`IDCODE: tdo_pad_o <=#Tp TDOData; // Reading ID code
569			`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData; // Selecting the chain
570			`DEBUG: tdo_pad_o <=#Tp TDOData; // Debug
571			`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_o; // Sampling/Preloading
572			`EXTEST: tdo_pad_o <=#Tp bs_chain_o; // External test
573			`default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction`
574			`endcase`
575			`end`
576			`end`
577
578			`// Tristate control for tdo_pad_o pin`
579			`assign tdo_padoen_o = ShiftIR \| ShiftDR \| Exit1IR \| Exit1DR \| UpdateDR;`
580
581			`/**********************************************************************************`
582			`* *`
583			`* End: Multiplexing TDO data *`
584			`* *`
585			`**********************************************************************************/`
586
587
588
589
590			`// Connecting dbg_top module`
591			`dbg_top i_dbg_top (`
592			`// RISC signals`
593			`.risc_clk_i(risc_clk_i), .risc_addr_o(risc_addr_o), .risc_data_i(risc_data_i),`
594			`.risc_data_o(risc_data_o), .wp_i(wp_i), .bp_i(bp_i),`
595			`.opselect_o(opselect_o), .lsstatus_i(lsstatus_i), .istatus_i(istatus_i),`
596			`.risc_stall_o(risc_stall_o), .reset_o(reset_o),`
597
598			`// WISHBONE common signals`
599			`.wb_rst_i(wb_rst_i), .wb_clk_i(wb_clk_i),`
600
601			`// WISHBONE master interface`
602			`.wb_adr_o(wb_adr_o), .wb_dat_o(wb_dat_o), .wb_dat_i(wb_dat_i),`
603			`.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_sel_o(wb_sel_o),`
604			`.wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), .wb_cab_o(wb_cab_o),`
605			`.wb_err_i(wb_err_i),`
606
607			`// TAP states`
608			`.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR),`
609			`.UpdateDR_q(UpdateDR_q),`
610
611			`// Instructions`
612			`.IDCODESelected(IDCODESelected),`
613			`.CHAIN_SELECTSelected(CHAIN_SELECTSelected),`
614			`.DEBUGSelected(DEBUGSelected),`
615
616			`// TAP signals`
617			`.trst(trst), .tck(tck), .tdi(tdi),`
618			`.TDOData(TDOData),`
619
620			`.BypassRegister(BypassRegister)`
621
622			`);`
623
624
625
626			`// Connecting bender_jtag module`
627			`jtag_chain i_jtag_chain (`
628			`.capture_dr_i(CaptureDR), .shift_dr_i(ShiftDR),`
629			`.update_dr_i(UpdateDR), .extest_selected_i(EXTESTSelected),`
630			`.bs_chain_i(tdi), .bs_chain_o(bs_chain_o)`
631			`);`
632
633			`endmodule`