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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 37

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001, 2002 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
 
                // TAP states
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
 
                // Instructions
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
 
                // TDO from dbg module
                TDOData_dbg, BypassRegister
              );
 
parameter Tp = 1;
 
// JTAG pins
input   tms_pad_i;                  // JTAG test mode select pad
input   tck_pad_i;                  // JTAG test clock pad
input   trst_pad_i;                 // JTAG test reset pad
input   tdi_pad_i;                  // JTAG test data input pad
output  tdo_pad_o;                  // JTAG test data output pad
output  tdo_padoen_o;               // Output enable for JTAG test data output pad 
 
// TAP states
output  ShiftDR;
output  Exit1DR;
output  UpdateDR;
output  UpdateDR_q;
 
// Instructions
output  IDCODESelected;
output  CHAIN_SELECTSelected;
output  DEBUGSelected;
 
input   TDOData_dbg;
output  BypassRegister;
 
reg     tdo_pad_o;
 
// TAP states
reg     TestLogicReset;
reg     RunTestIdle;
reg     SelectDRScan;
reg     CaptureDR;
reg     ShiftDR;
reg     Exit1DR;
reg     PauseDR;
reg     Exit2DR;
reg     UpdateDR;
 
reg     SelectIRScan;
reg     CaptureIR;
reg     ShiftIR;
reg     Exit1IR;
reg     PauseIR;
reg     Exit2IR;
reg     UpdateIR;
 
 
// Defining which instruction is selected
reg     EXTESTSelected;
reg     SAMPLE_PRELOADSelected;
reg     IDCODESelected;
reg     CHAIN_SELECTSelected;
reg     INTESTSelected;
reg     CLAMPSelected;
reg     CLAMPZSelected;
reg     HIGHZSelected;
reg     DEBUGSelected;
reg     BYPASSSelected;
 
reg     BypassRegister;               // Bypass register
 
wire    trst;                         // trst is active high while trst_pad_i is active low
wire    tck;
wire    TMS;
wire    tdi;
 
wire    RiscDebugScanChain;
wire    WishboneScanChain;
wire    RegisterScanChain;
wire    bs_chain_o;
 
 
assign trst = ~trst_pad_i;                // trst_pad_i is active low
assign tck  = tck_pad_i;
assign TMS  = tms_pad_i;
assign tdi  = tdi_pad_i;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
  if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
    RunTestIdle<=#Tp 1;
  else
    RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
  if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
    SelectDRScan<=#Tp 1;
  else
    SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
  if(~TMS & SelectDRScan)
    CaptureDR<=#Tp 1;
  else
    CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
  if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
    ShiftDR<=#Tp 1;
  else
    ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
  if(TMS & (CaptureDR | ShiftDR))
    Exit1DR<=#Tp 1;
  else
    Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
  if(~TMS & (Exit1DR | PauseDR))
    PauseDR<=#Tp 1;
  else
    PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
  if(TMS & PauseDR)
    Exit2DR<=#Tp 1;
  else
    Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
  if(TMS & (Exit1DR | Exit2DR))
    UpdateDR<=#Tp 1;
  else
    UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
  if(TMS & SelectDRScan)
    SelectIRScan<=#Tp 1;
  else
    SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
  if(~TMS & SelectIRScan)
    CaptureIR<=#Tp 1;
  else
    CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
  if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
    ShiftIR<=#Tp 1;
  else
    ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
  if(TMS & (CaptureIR | ShiftIR))
    Exit1IR<=#Tp 1;
  else
    Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
  if(~TMS & (Exit1IR | PauseIR))
    PauseIR<=#Tp 1;
  else
    PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
  if(TMS & PauseIR)
    Exit2IR<=#Tp 1;
  else
    Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
  if(TMS & (Exit1IR | Exit2IR))
    UpdateIR<=#Tp 1;
  else
    UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
  if(CaptureIR)
    begin
      JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
      JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
    end
  else
  if(ShiftIR)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
 
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
    begin
      if(ShiftDR)
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
      else
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
    end
  else
  if(CHAIN_SELECTSelected & ShiftDR)
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
  else
  if(DEBUGSelected & ShiftDR)
    begin
      if(RiscDebugScanChain | WishboneScanChain)
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
      else
      if(RegisterScanChain)
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
    end
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
  if(ShiftDR)
    BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
  TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_o or ShiftIR or Exit1IR)
begin
  if(ShiftIR | Exit1IR)
    tdo_pad_o <=#Tp TDOInstruction;
  else
    begin
      case(LatchedJTAG_IR)
        `IDCODE:            tdo_pad_o <=#Tp TDOData_dbg;      // Reading ID code
        `CHAIN_SELECT:      tdo_pad_o <=#Tp TDOData_dbg;      // Selecting the chain
        `DEBUG:             tdo_pad_o <=#Tp TDOData_dbg;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o <=#Tp bs_chain_o;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o <=#Tp bs_chain_o;   // External test
        default:            tdo_pad_o <=#Tp TDOBypassed;  // BYPASS instruction
      endcase
    end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 37

Line No.	Rev	Author	Line
1	36	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000, 2001, 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	37	mohor	`// Revision 1.1 2002/03/08 15:28:16 mohor`
49			`// Structure changed. Hooks for jtag chain added.`
50	36	mohor	`//`
51			`//`
52			`//`
53	37	mohor	`//`
54	36	mohor
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58			`include "dbg_defines.v"
59
60			`// Top module`
61			`module tap_top(`
62			`// JTAG pins`
63			`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,`
64
65	37	mohor	`// TAP states`
66			`ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,`
67	36	mohor
68	37	mohor	`// Instructions`
69			`IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,`
70
71			`// TDO from dbg module`
72			`TDOData_dbg, BypassRegister`
73	36	mohor	`);`
74
75			`parameter Tp = 1;`
76
77			`// JTAG pins`
78			`input tms_pad_i; // JTAG test mode select pad`
79			`input tck_pad_i; // JTAG test clock pad`
80			`input trst_pad_i; // JTAG test reset pad`
81			`input tdi_pad_i; // JTAG test data input pad`
82			`output tdo_pad_o; // JTAG test data output pad`
83			`output tdo_padoen_o; // Output enable for JTAG test data output pad`
84
85	37	mohor	`// TAP states`
86			`output ShiftDR;`
87			`output Exit1DR;`
88			`output UpdateDR;`
89			`output UpdateDR_q;`
90	36	mohor
91	37	mohor	`// Instructions`
92			`output IDCODESelected;`
93			`output CHAIN_SELECTSelected;`
94			`output DEBUGSelected;`
95	36	mohor
96	37	mohor	`input TDOData_dbg;`
97			`output BypassRegister;`
98	36	mohor
99			`reg tdo_pad_o;`
100
101			`// TAP states`
102			`reg TestLogicReset;`
103			`reg RunTestIdle;`
104			`reg SelectDRScan;`
105			`reg CaptureDR;`
106			`reg ShiftDR;`
107			`reg Exit1DR;`
108			`reg PauseDR;`
109			`reg Exit2DR;`
110			`reg UpdateDR;`
111
112			`reg SelectIRScan;`
113			`reg CaptureIR;`
114			`reg ShiftIR;`
115			`reg Exit1IR;`
116			`reg PauseIR;`
117			`reg Exit2IR;`
118			`reg UpdateIR;`
119
120
121			`// Defining which instruction is selected`
122			`reg EXTESTSelected;`
123			`reg SAMPLE_PRELOADSelected;`
124			`reg IDCODESelected;`
125			`reg CHAIN_SELECTSelected;`
126			`reg INTESTSelected;`
127			`reg CLAMPSelected;`
128			`reg CLAMPZSelected;`
129			`reg HIGHZSelected;`
130			`reg DEBUGSelected;`
131			`reg BYPASSSelected;`
132
133			`reg BypassRegister; // Bypass register`
134
135			`wire trst; // trst is active high while trst_pad_i is active low`
136			`wire tck;`
137			`wire TMS;`
138			`wire tdi;`
139
140			`wire RiscDebugScanChain;`
141			`wire WishboneScanChain;`
142			`wire RegisterScanChain;`
143			`wire bs_chain_o;`
144
145
146			`assign trst = ~trst_pad_i; // trst_pad_i is active low`
147			`assign tck = tck_pad_i;`
148			`assign TMS = tms_pad_i;`
149			`assign tdi = tdi_pad_i;`
150
151
152			`/**********************************************************************************`
153			`* *`
154			`* TAP State Machine: Fully JTAG compliant *`
155			`* *`
156			`**********************************************************************************/`
157
158			`// TestLogicReset state`
159			`always @ (posedge tck or posedge trst)`
160			`begin`
161			`if(trst)`
162			`TestLogicReset<=#Tp 1;`
163			`else`
164			`begin`
165			`if(TMS & (TestLogicReset \| SelectIRScan))`
166			`TestLogicReset<=#Tp 1;`
167			`else`
168			`TestLogicReset<=#Tp 0;`
169			`end`
170			`end`
171
172			`// RunTestIdle state`
173			`always @ (posedge tck or posedge trst)`
174			`begin`
175			`if(trst)`
176			`RunTestIdle<=#Tp 0;`
177			`else`
178			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
179			`RunTestIdle<=#Tp 1;`
180			`else`
181			`RunTestIdle<=#Tp 0;`
182			`end`
183
184			`// SelectDRScan state`
185			`always @ (posedge tck or posedge trst)`
186			`begin`
187			`if(trst)`
188			`SelectDRScan<=#Tp 0;`
189			`else`
190			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
191			`SelectDRScan<=#Tp 1;`
192			`else`
193			`SelectDRScan<=#Tp 0;`
194			`end`
195
196			`// CaptureDR state`
197			`always @ (posedge tck or posedge trst)`
198			`begin`
199			`if(trst)`
200			`CaptureDR<=#Tp 0;`
201			`else`
202			`if(~TMS & SelectDRScan)`
203			`CaptureDR<=#Tp 1;`
204			`else`
205			`CaptureDR<=#Tp 0;`
206			`end`
207
208			`// ShiftDR state`
209			`always @ (posedge tck or posedge trst)`
210			`begin`
211			`if(trst)`
212			`ShiftDR<=#Tp 0;`
213			`else`
214			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
215			`ShiftDR<=#Tp 1;`
216			`else`
217			`ShiftDR<=#Tp 0;`
218			`end`
219
220			`// Exit1DR state`
221			`always @ (posedge tck or posedge trst)`
222			`begin`
223			`if(trst)`
224			`Exit1DR<=#Tp 0;`
225			`else`
226			`if(TMS & (CaptureDR \| ShiftDR))`
227			`Exit1DR<=#Tp 1;`
228			`else`
229			`Exit1DR<=#Tp 0;`
230			`end`
231
232			`// PauseDR state`
233			`always @ (posedge tck or posedge trst)`
234			`begin`
235			`if(trst)`
236			`PauseDR<=#Tp 0;`
237			`else`
238			`if(~TMS & (Exit1DR \| PauseDR))`
239			`PauseDR<=#Tp 1;`
240			`else`
241			`PauseDR<=#Tp 0;`
242			`end`
243
244			`// Exit2DR state`
245			`always @ (posedge tck or posedge trst)`
246			`begin`
247			`if(trst)`
248			`Exit2DR<=#Tp 0;`
249			`else`
250			`if(TMS & PauseDR)`
251			`Exit2DR<=#Tp 1;`
252			`else`
253			`Exit2DR<=#Tp 0;`
254			`end`
255
256			`// UpdateDR state`
257			`always @ (posedge tck or posedge trst)`
258			`begin`
259			`if(trst)`
260			`UpdateDR<=#Tp 0;`
261			`else`
262			`if(TMS & (Exit1DR \| Exit2DR))`
263			`UpdateDR<=#Tp 1;`
264			`else`
265			`UpdateDR<=#Tp 0;`
266			`end`
267
268			`// Delayed UpdateDR state`
269			`reg UpdateDR_q;`
270			`always @ (posedge tck)`
271			`begin`
272			`UpdateDR_q<=#Tp UpdateDR;`
273			`end`
274
275			`// SelectIRScan state`
276			`always @ (posedge tck or posedge trst)`
277			`begin`
278			`if(trst)`
279			`SelectIRScan<=#Tp 0;`
280			`else`
281			`if(TMS & SelectDRScan)`
282			`SelectIRScan<=#Tp 1;`
283			`else`
284			`SelectIRScan<=#Tp 0;`
285			`end`
286
287			`// CaptureIR state`
288			`always @ (posedge tck or posedge trst)`
289			`begin`
290			`if(trst)`
291			`CaptureIR<=#Tp 0;`
292			`else`
293			`if(~TMS & SelectIRScan)`
294			`CaptureIR<=#Tp 1;`
295			`else`
296			`CaptureIR<=#Tp 0;`
297			`end`
298
299			`// ShiftIR state`
300			`always @ (posedge tck or posedge trst)`
301			`begin`
302			`if(trst)`
303			`ShiftIR<=#Tp 0;`
304			`else`
305			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
306			`ShiftIR<=#Tp 1;`
307			`else`
308			`ShiftIR<=#Tp 0;`
309			`end`
310
311			`// Exit1IR state`
312			`always @ (posedge tck or posedge trst)`
313			`begin`
314			`if(trst)`
315			`Exit1IR<=#Tp 0;`
316			`else`
317			`if(TMS & (CaptureIR \| ShiftIR))`
318			`Exit1IR<=#Tp 1;`
319			`else`
320			`Exit1IR<=#Tp 0;`
321			`end`
322
323			`// PauseIR state`
324			`always @ (posedge tck or posedge trst)`
325			`begin`
326			`if(trst)`
327			`PauseIR<=#Tp 0;`
328			`else`
329			`if(~TMS & (Exit1IR \| PauseIR))`
330			`PauseIR<=#Tp 1;`
331			`else`
332			`PauseIR<=#Tp 0;`
333			`end`
334
335			`// Exit2IR state`
336			`always @ (posedge tck or posedge trst)`
337			`begin`
338			`if(trst)`
339			`Exit2IR<=#Tp 0;`
340			`else`
341			`if(TMS & PauseIR)`
342			`Exit2IR<=#Tp 1;`
343			`else`
344			`Exit2IR<=#Tp 0;`
345			`end`
346
347			`// UpdateIR state`
348			`always @ (posedge tck or posedge trst)`
349			`begin`
350			`if(trst)`
351			`UpdateIR<=#Tp 0;`
352			`else`
353			`if(TMS & (Exit1IR \| Exit2IR))`
354			`UpdateIR<=#Tp 1;`
355			`else`
356			`UpdateIR<=#Tp 0;`
357			`end`
358
359			`/**********************************************************************************`
360			`* *`
361			`* End: TAP State Machine *`
362			`* *`
363			`**********************************************************************************/`
364
365
366
367			`/**********************************************************************************`
368			`* *`
369			`* JTAG_IR: JTAG Instruction Register *`
370			`* *`
371			`**********************************************************************************/`
372			`wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.`
373
374			reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
375			reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
376
377			`reg TDOInstruction;`
378
379			`always @ (posedge tck or posedge trst)`
380			`begin`
381			`if(trst)`
382			JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
383			`else`
384			`if(CaptureIR)`
385			`begin`
386			`JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection`
387			`JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip`
388			`end`
389			`else`
390			`if(ShiftIR)`
391			JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
392			`end`
393
394
395			`//TDO is changing on the falling edge of tck`
396			`always @ (negedge tck)`
397			`begin`
398			`if(ShiftIR)`
399			`TDOInstruction <= #Tp JTAG_IR[0];`
400			`end`
401
402			`/**********************************************************************************`
403			`* *`
404			`* End: JTAG_IR *`
405			`* *`
406			`**********************************************************************************/`
407
408
409			`/**********************************************************************************`
410			`* *`
411			`* JTAG_DR: JTAG Data Register *`
412			`* *`
413			`**********************************************************************************/`
414			reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
415
416
417			`always @ (posedge tck or posedge trst)`
418			`begin`
419			`if(trst)`
420			JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
421			`else`
422			`if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE`
423			`begin`
424			`if(ShiftDR)`
425			`JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};`
426			`else`
427			JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
428			`end`
429			`else`
430			`if(CHAIN_SELECTSelected & ShiftDR)`
431			`JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};`
432			`else`
433			`if(DEBUGSelected & ShiftDR)`
434			`begin`
435			`if(RiscDebugScanChain \| WishboneScanChain)`
436			`JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};`
437			`else`
438			`if(RegisterScanChain)`
439			`JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};`
440			`end`
441			`end`
442
443
444
445			`/**********************************************************************************`
446			`* *`
447			`* End: JTAG_DR *`
448			`* *`
449			`**********************************************************************************/`
450
451
452
453
454
455			`/**********************************************************************************`
456			`* *`
457			`* Bypass logic *`
458			`* *`
459			`**********************************************************************************/`
460			`reg TDOBypassed;`
461
462			`always @ (posedge tck)`
463			`begin`
464			`if(ShiftDR)`
465			`BypassRegister<=#Tp tdi;`
466			`end`
467
468			`always @ (negedge tck)`
469			`begin`
470			`TDOBypassed<=#Tp BypassRegister;`
471			`end`
472			`/**********************************************************************************`
473			`* *`
474			`* End: Bypass logic *`
475			`* *`
476			`**********************************************************************************/`
477
478
479
480
481
482			`/**********************************************************************************`
483			`* *`
484			`* Activating Instructions *`
485			`* *`
486			`**********************************************************************************/`
487
488			`// Updating JTAG_IR (Instruction Register)`
489			`always @ (posedge tck or posedge trst)`
490			`begin`
491			`if(trst)`
492			LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
493			`else`
494			`if(UpdateIR)`
495			`LatchedJTAG_IR <=#Tp JTAG_IR;`
496			`end`
497
498			`/**********************************************************************************`
499			`* *`
500			`* End: Activating Instructions *`
501			`* *`
502			`**********************************************************************************/`
503
504
505			`// Updating JTAG_IR (Instruction Register)`
506			`always @ (LatchedJTAG_IR)`
507			`begin`
508			`EXTESTSelected = 0;`
509			`SAMPLE_PRELOADSelected = 0;`
510			`IDCODESelected = 0;`
511			`CHAIN_SELECTSelected = 0;`
512			`INTESTSelected = 0;`
513			`CLAMPSelected = 0;`
514			`CLAMPZSelected = 0;`
515			`HIGHZSelected = 0;`
516			`DEBUGSelected = 0;`
517			`BYPASSSelected = 0;`
518
519			`case(LatchedJTAG_IR)`
520			`EXTEST: EXTESTSelected = 1; // External test
521			`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
522			`IDCODE: IDCODESelected = 1; // ID Code
523			`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
524			`INTEST: INTESTSelected = 1; // Internal test
525			`CLAMP: CLAMPSelected = 1; // Clamp
526			`CLAMPZ: CLAMPZSelected = 1; // ClampZ
527			`HIGHZ: HIGHZSelected = 1; // High Z
528			`DEBUG: DEBUGSelected = 1; // Debug
529			`BYPASS: BYPASSSelected = 1; // BYPASS
530			`default: BYPASSSelected = 1; // BYPASS`
531			`endcase`
532			`end`
533
534
535
536			`/**********************************************************************************`
537			`* *`
538			`* Multiplexing TDO data *`
539			`* *`
540			`**********************************************************************************/`
541
542			`// This multiplexer can be expanded with number of user registers`
543	37	mohor	`always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_o or ShiftIR or Exit1IR)`
544	36	mohor	`begin`
545			`if(ShiftIR \| Exit1IR)`
546			`tdo_pad_o <=#Tp TDOInstruction;`
547			`else`
548			`begin`
549			`case(LatchedJTAG_IR)`
550	37	mohor	`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
551			`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
552			`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
553	36	mohor	`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_o; // Sampling/Preloading
554			`EXTEST: tdo_pad_o <=#Tp bs_chain_o; // External test
555			`default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction`
556			`endcase`
557			`end`
558			`end`
559
560			`// Tristate control for tdo_pad_o pin`
561			`assign tdo_padoen_o = ShiftIR \| ShiftDR \| Exit1IR \| Exit1DR \| UpdateDR;`
562
563			`/**********************************************************************************`
564			`* *`
565			`* End: Multiplexing TDO data *`
566			`* *`
567			`**********************************************************************************/`
568
569			`endmodule`