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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 38

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001, 2002 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
 
                // TAP states
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
 
                // Instructions
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
 
                // TDO from dbg module
                TDOData_dbg, BypassRegister,
 
                // From Boundary Scan Chain
                bs_chain_i
 
              );
 
parameter Tp = 1;
 
// JTAG pins
input   tms_pad_i;                  // JTAG test mode select pad
input   tck_pad_i;                  // JTAG test clock pad
input   trst_pad_i;                 // JTAG test reset pad
input   tdi_pad_i;                  // JTAG test data input pad
output  tdo_pad_o;                  // JTAG test data output pad
output  tdo_padoen_o;               // Output enable for JTAG test data output pad 
 
// TAP states
output  ShiftDR;
output  Exit1DR;
output  UpdateDR;
output  UpdateDR_q;
output  CaptureDR;
 
// Instructions
output  IDCODESelected;
output  CHAIN_SELECTSelected;
output  DEBUGSelected;
output  EXTESTSelected;
 
input   TDOData_dbg;
output  BypassRegister;
 
// From Boundary Scan Chain
input   bs_chain_i;
 
 
reg     tdo_pad_o;
 
// TAP states
reg     TestLogicReset;
reg     RunTestIdle;
reg     SelectDRScan;
reg     CaptureDR;
reg     ShiftDR;
reg     Exit1DR;
reg     PauseDR;
reg     Exit2DR;
reg     UpdateDR;
 
reg     SelectIRScan;
reg     CaptureIR;
reg     ShiftIR;
reg     Exit1IR;
reg     PauseIR;
reg     Exit2IR;
reg     UpdateIR;
 
 
// Defining which instruction is selected
reg     EXTESTSelected;
reg     SAMPLE_PRELOADSelected;
reg     IDCODESelected;
reg     CHAIN_SELECTSelected;
reg     INTESTSelected;
reg     CLAMPSelected;
reg     CLAMPZSelected;
reg     HIGHZSelected;
reg     DEBUGSelected;
reg     BYPASSSelected;
 
reg     BypassRegister;               // Bypass register
 
wire    trst;                         // trst is active high while trst_pad_i is active low
wire    tck;
wire    TMS;
wire    tdi;
 
wire    RiscDebugScanChain;
wire    WishboneScanChain;
wire    RegisterScanChain;
 
 
assign trst = ~trst_pad_i;                // trst_pad_i is active low
assign tck  = tck_pad_i;
assign TMS  = tms_pad_i;
assign tdi  = tdi_pad_i;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
  if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
    RunTestIdle<=#Tp 1;
  else
    RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
  if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
    SelectDRScan<=#Tp 1;
  else
    SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
  if(~TMS & SelectDRScan)
    CaptureDR<=#Tp 1;
  else
    CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
  if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
    ShiftDR<=#Tp 1;
  else
    ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
  if(TMS & (CaptureDR | ShiftDR))
    Exit1DR<=#Tp 1;
  else
    Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
  if(~TMS & (Exit1DR | PauseDR))
    PauseDR<=#Tp 1;
  else
    PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
  if(TMS & PauseDR)
    Exit2DR<=#Tp 1;
  else
    Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
  if(TMS & (Exit1DR | Exit2DR))
    UpdateDR<=#Tp 1;
  else
    UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
  if(TMS & SelectDRScan)
    SelectIRScan<=#Tp 1;
  else
    SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
  if(~TMS & SelectIRScan)
    CaptureIR<=#Tp 1;
  else
    CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
  if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
    ShiftIR<=#Tp 1;
  else
    ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
  if(TMS & (CaptureIR | ShiftIR))
    Exit1IR<=#Tp 1;
  else
    Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
  if(~TMS & (Exit1IR | PauseIR))
    PauseIR<=#Tp 1;
  else
    PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
  if(TMS & PauseIR)
    Exit2IR<=#Tp 1;
  else
    Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
  if(TMS & (Exit1IR | Exit2IR))
    UpdateIR<=#Tp 1;
  else
    UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
  if(CaptureIR)
    begin
      JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
      JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
    end
  else
  if(ShiftIR)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
 
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
    begin
      if(ShiftDR)
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
      else
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
    end
  else
  if(CHAIN_SELECTSelected & ShiftDR)
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
  else
  if(DEBUGSelected & ShiftDR)
    begin
      if(RiscDebugScanChain | WishboneScanChain)
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
      else
      if(RegisterScanChain)
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
    end
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
  if(ShiftDR)
    BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
  TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
begin
  if(ShiftIR | Exit1IR)
    tdo_pad_o <=#Tp TDOInstruction;
  else
    begin
      case(LatchedJTAG_IR)
        `IDCODE:            tdo_pad_o <=#Tp TDOData_dbg;      // Reading ID code
        `CHAIN_SELECT:      tdo_pad_o <=#Tp TDOData_dbg;      // Selecting the chain
        `DEBUG:             tdo_pad_o <=#Tp TDOData_dbg;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o <=#Tp bs_chain_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o <=#Tp bs_chain_i;   // External test
        default:            tdo_pad_o <=#Tp TDOBypassed;  // BYPASS instruction
      endcase
    end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 38

Line No.	Rev	Author	Line
1	36	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000, 2001, 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	38	mohor	`// Revision 1.2 2002/03/12 10:31:53 mohor`
49			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
50			`// contains only tap state machine and related logic. dbg_top contains all`
51			`// logic necessery for debugging.`
52			`//`
53	37	mohor	`// Revision 1.1 2002/03/08 15:28:16 mohor`
54			`// Structure changed. Hooks for jtag chain added.`
55	36	mohor	`//`
56			`//`
57			`//`
58	37	mohor	`//`
59	36	mohor
60			`// synopsys translate_off`
61			`include "timescale.v"
62			`// synopsys translate_on`
63			`include "dbg_defines.v"
64
65			`// Top module`
66			`module tap_top(`
67			`// JTAG pins`
68			`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,`
69
70	37	mohor	`// TAP states`
71	38	mohor	`ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,`
72	36	mohor
73	37	mohor	`// Instructions`
74	38	mohor	`IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,`
75	37	mohor
76			`// TDO from dbg module`
77	38	mohor	`TDOData_dbg, BypassRegister,`
78
79			`// From Boundary Scan Chain`
80			`bs_chain_i`
81
82	36	mohor	`);`
83
84			`parameter Tp = 1;`
85
86			`// JTAG pins`
87			`input tms_pad_i; // JTAG test mode select pad`
88			`input tck_pad_i; // JTAG test clock pad`
89			`input trst_pad_i; // JTAG test reset pad`
90			`input tdi_pad_i; // JTAG test data input pad`
91			`output tdo_pad_o; // JTAG test data output pad`
92			`output tdo_padoen_o; // Output enable for JTAG test data output pad`
93
94	37	mohor	`// TAP states`
95			`output ShiftDR;`
96			`output Exit1DR;`
97			`output UpdateDR;`
98			`output UpdateDR_q;`
99	38	mohor	`output CaptureDR;`
100	36	mohor
101	37	mohor	`// Instructions`
102			`output IDCODESelected;`
103			`output CHAIN_SELECTSelected;`
104			`output DEBUGSelected;`
105	38	mohor	`output EXTESTSelected;`
106	36	mohor
107	37	mohor	`input TDOData_dbg;`
108			`output BypassRegister;`
109	36	mohor
110	38	mohor	`// From Boundary Scan Chain`
111			`input bs_chain_i;`
112
113
114	36	mohor	`reg tdo_pad_o;`
115
116			`// TAP states`
117			`reg TestLogicReset;`
118			`reg RunTestIdle;`
119			`reg SelectDRScan;`
120			`reg CaptureDR;`
121			`reg ShiftDR;`
122			`reg Exit1DR;`
123			`reg PauseDR;`
124			`reg Exit2DR;`
125			`reg UpdateDR;`
126
127			`reg SelectIRScan;`
128			`reg CaptureIR;`
129			`reg ShiftIR;`
130			`reg Exit1IR;`
131			`reg PauseIR;`
132			`reg Exit2IR;`
133			`reg UpdateIR;`
134
135
136			`// Defining which instruction is selected`
137			`reg EXTESTSelected;`
138			`reg SAMPLE_PRELOADSelected;`
139			`reg IDCODESelected;`
140			`reg CHAIN_SELECTSelected;`
141			`reg INTESTSelected;`
142			`reg CLAMPSelected;`
143			`reg CLAMPZSelected;`
144			`reg HIGHZSelected;`
145			`reg DEBUGSelected;`
146			`reg BYPASSSelected;`
147
148			`reg BypassRegister; // Bypass register`
149
150			`wire trst; // trst is active high while trst_pad_i is active low`
151			`wire tck;`
152			`wire TMS;`
153			`wire tdi;`
154
155			`wire RiscDebugScanChain;`
156			`wire WishboneScanChain;`
157			`wire RegisterScanChain;`
158
159
160			`assign trst = ~trst_pad_i; // trst_pad_i is active low`
161			`assign tck = tck_pad_i;`
162			`assign TMS = tms_pad_i;`
163			`assign tdi = tdi_pad_i;`
164
165
166			`/**********************************************************************************`
167			`* *`
168			`* TAP State Machine: Fully JTAG compliant *`
169			`* *`
170			`**********************************************************************************/`
171
172			`// TestLogicReset state`
173			`always @ (posedge tck or posedge trst)`
174			`begin`
175			`if(trst)`
176			`TestLogicReset<=#Tp 1;`
177			`else`
178			`begin`
179			`if(TMS & (TestLogicReset \| SelectIRScan))`
180			`TestLogicReset<=#Tp 1;`
181			`else`
182			`TestLogicReset<=#Tp 0;`
183			`end`
184			`end`
185
186			`// RunTestIdle state`
187			`always @ (posedge tck or posedge trst)`
188			`begin`
189			`if(trst)`
190			`RunTestIdle<=#Tp 0;`
191			`else`
192			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
193			`RunTestIdle<=#Tp 1;`
194			`else`
195			`RunTestIdle<=#Tp 0;`
196			`end`
197
198			`// SelectDRScan state`
199			`always @ (posedge tck or posedge trst)`
200			`begin`
201			`if(trst)`
202			`SelectDRScan<=#Tp 0;`
203			`else`
204			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
205			`SelectDRScan<=#Tp 1;`
206			`else`
207			`SelectDRScan<=#Tp 0;`
208			`end`
209
210			`// CaptureDR state`
211			`always @ (posedge tck or posedge trst)`
212			`begin`
213			`if(trst)`
214			`CaptureDR<=#Tp 0;`
215			`else`
216			`if(~TMS & SelectDRScan)`
217			`CaptureDR<=#Tp 1;`
218			`else`
219			`CaptureDR<=#Tp 0;`
220			`end`
221
222			`// ShiftDR state`
223			`always @ (posedge tck or posedge trst)`
224			`begin`
225			`if(trst)`
226			`ShiftDR<=#Tp 0;`
227			`else`
228			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
229			`ShiftDR<=#Tp 1;`
230			`else`
231			`ShiftDR<=#Tp 0;`
232			`end`
233
234			`// Exit1DR state`
235			`always @ (posedge tck or posedge trst)`
236			`begin`
237			`if(trst)`
238			`Exit1DR<=#Tp 0;`
239			`else`
240			`if(TMS & (CaptureDR \| ShiftDR))`
241			`Exit1DR<=#Tp 1;`
242			`else`
243			`Exit1DR<=#Tp 0;`
244			`end`
245
246			`// PauseDR state`
247			`always @ (posedge tck or posedge trst)`
248			`begin`
249			`if(trst)`
250			`PauseDR<=#Tp 0;`
251			`else`
252			`if(~TMS & (Exit1DR \| PauseDR))`
253			`PauseDR<=#Tp 1;`
254			`else`
255			`PauseDR<=#Tp 0;`
256			`end`
257
258			`// Exit2DR state`
259			`always @ (posedge tck or posedge trst)`
260			`begin`
261			`if(trst)`
262			`Exit2DR<=#Tp 0;`
263			`else`
264			`if(TMS & PauseDR)`
265			`Exit2DR<=#Tp 1;`
266			`else`
267			`Exit2DR<=#Tp 0;`
268			`end`
269
270			`// UpdateDR state`
271			`always @ (posedge tck or posedge trst)`
272			`begin`
273			`if(trst)`
274			`UpdateDR<=#Tp 0;`
275			`else`
276			`if(TMS & (Exit1DR \| Exit2DR))`
277			`UpdateDR<=#Tp 1;`
278			`else`
279			`UpdateDR<=#Tp 0;`
280			`end`
281
282			`// Delayed UpdateDR state`
283			`reg UpdateDR_q;`
284			`always @ (posedge tck)`
285			`begin`
286			`UpdateDR_q<=#Tp UpdateDR;`
287			`end`
288
289			`// SelectIRScan state`
290			`always @ (posedge tck or posedge trst)`
291			`begin`
292			`if(trst)`
293			`SelectIRScan<=#Tp 0;`
294			`else`
295			`if(TMS & SelectDRScan)`
296			`SelectIRScan<=#Tp 1;`
297			`else`
298			`SelectIRScan<=#Tp 0;`
299			`end`
300
301			`// CaptureIR state`
302			`always @ (posedge tck or posedge trst)`
303			`begin`
304			`if(trst)`
305			`CaptureIR<=#Tp 0;`
306			`else`
307			`if(~TMS & SelectIRScan)`
308			`CaptureIR<=#Tp 1;`
309			`else`
310			`CaptureIR<=#Tp 0;`
311			`end`
312
313			`// ShiftIR state`
314			`always @ (posedge tck or posedge trst)`
315			`begin`
316			`if(trst)`
317			`ShiftIR<=#Tp 0;`
318			`else`
319			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
320			`ShiftIR<=#Tp 1;`
321			`else`
322			`ShiftIR<=#Tp 0;`
323			`end`
324
325			`// Exit1IR state`
326			`always @ (posedge tck or posedge trst)`
327			`begin`
328			`if(trst)`
329			`Exit1IR<=#Tp 0;`
330			`else`
331			`if(TMS & (CaptureIR \| ShiftIR))`
332			`Exit1IR<=#Tp 1;`
333			`else`
334			`Exit1IR<=#Tp 0;`
335			`end`
336
337			`// PauseIR state`
338			`always @ (posedge tck or posedge trst)`
339			`begin`
340			`if(trst)`
341			`PauseIR<=#Tp 0;`
342			`else`
343			`if(~TMS & (Exit1IR \| PauseIR))`
344			`PauseIR<=#Tp 1;`
345			`else`
346			`PauseIR<=#Tp 0;`
347			`end`
348
349			`// Exit2IR state`
350			`always @ (posedge tck or posedge trst)`
351			`begin`
352			`if(trst)`
353			`Exit2IR<=#Tp 0;`
354			`else`
355			`if(TMS & PauseIR)`
356			`Exit2IR<=#Tp 1;`
357			`else`
358			`Exit2IR<=#Tp 0;`
359			`end`
360
361			`// UpdateIR state`
362			`always @ (posedge tck or posedge trst)`
363			`begin`
364			`if(trst)`
365			`UpdateIR<=#Tp 0;`
366			`else`
367			`if(TMS & (Exit1IR \| Exit2IR))`
368			`UpdateIR<=#Tp 1;`
369			`else`
370			`UpdateIR<=#Tp 0;`
371			`end`
372
373			`/**********************************************************************************`
374			`* *`
375			`* End: TAP State Machine *`
376			`* *`
377			`**********************************************************************************/`
378
379
380
381			`/**********************************************************************************`
382			`* *`
383			`* JTAG_IR: JTAG Instruction Register *`
384			`* *`
385			`**********************************************************************************/`
386			`wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.`
387
388			reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
389			reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
390
391			`reg TDOInstruction;`
392
393			`always @ (posedge tck or posedge trst)`
394			`begin`
395			`if(trst)`
396			JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
397			`else`
398			`if(CaptureIR)`
399			`begin`
400			`JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection`
401			`JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip`
402			`end`
403			`else`
404			`if(ShiftIR)`
405			JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
406			`end`
407
408
409			`//TDO is changing on the falling edge of tck`
410			`always @ (negedge tck)`
411			`begin`
412			`if(ShiftIR)`
413			`TDOInstruction <= #Tp JTAG_IR[0];`
414			`end`
415
416			`/**********************************************************************************`
417			`* *`
418			`* End: JTAG_IR *`
419			`* *`
420			`**********************************************************************************/`
421
422
423			`/**********************************************************************************`
424			`* *`
425			`* JTAG_DR: JTAG Data Register *`
426			`* *`
427			`**********************************************************************************/`
428			reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
429
430
431			`always @ (posedge tck or posedge trst)`
432			`begin`
433			`if(trst)`
434			JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
435			`else`
436			`if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE`
437			`begin`
438			`if(ShiftDR)`
439			`JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};`
440			`else`
441			JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
442			`end`
443			`else`
444			`if(CHAIN_SELECTSelected & ShiftDR)`
445			`JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};`
446			`else`
447			`if(DEBUGSelected & ShiftDR)`
448			`begin`
449			`if(RiscDebugScanChain \| WishboneScanChain)`
450			`JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};`
451			`else`
452			`if(RegisterScanChain)`
453			`JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};`
454			`end`
455			`end`
456
457
458
459			`/**********************************************************************************`
460			`* *`
461			`* End: JTAG_DR *`
462			`* *`
463			`**********************************************************************************/`
464
465
466
467
468
469			`/**********************************************************************************`
470			`* *`
471			`* Bypass logic *`
472			`* *`
473			`**********************************************************************************/`
474			`reg TDOBypassed;`
475
476			`always @ (posedge tck)`
477			`begin`
478			`if(ShiftDR)`
479			`BypassRegister<=#Tp tdi;`
480			`end`
481
482			`always @ (negedge tck)`
483			`begin`
484			`TDOBypassed<=#Tp BypassRegister;`
485			`end`
486			`/**********************************************************************************`
487			`* *`
488			`* End: Bypass logic *`
489			`* *`
490			`**********************************************************************************/`
491
492
493
494
495
496			`/**********************************************************************************`
497			`* *`
498			`* Activating Instructions *`
499			`* *`
500			`**********************************************************************************/`
501
502			`// Updating JTAG_IR (Instruction Register)`
503			`always @ (posedge tck or posedge trst)`
504			`begin`
505			`if(trst)`
506			LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
507			`else`
508			`if(UpdateIR)`
509			`LatchedJTAG_IR <=#Tp JTAG_IR;`
510			`end`
511
512			`/**********************************************************************************`
513			`* *`
514			`* End: Activating Instructions *`
515			`* *`
516			`**********************************************************************************/`
517
518
519			`// Updating JTAG_IR (Instruction Register)`
520			`always @ (LatchedJTAG_IR)`
521			`begin`
522			`EXTESTSelected = 0;`
523			`SAMPLE_PRELOADSelected = 0;`
524			`IDCODESelected = 0;`
525			`CHAIN_SELECTSelected = 0;`
526			`INTESTSelected = 0;`
527			`CLAMPSelected = 0;`
528			`CLAMPZSelected = 0;`
529			`HIGHZSelected = 0;`
530			`DEBUGSelected = 0;`
531			`BYPASSSelected = 0;`
532
533			`case(LatchedJTAG_IR)`
534			`EXTEST: EXTESTSelected = 1; // External test
535			`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
536			`IDCODE: IDCODESelected = 1; // ID Code
537			`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
538			`INTEST: INTESTSelected = 1; // Internal test
539			`CLAMP: CLAMPSelected = 1; // Clamp
540			`CLAMPZ: CLAMPZSelected = 1; // ClampZ
541			`HIGHZ: HIGHZSelected = 1; // High Z
542			`DEBUG: DEBUGSelected = 1; // Debug
543			`BYPASS: BYPASSSelected = 1; // BYPASS
544			`default: BYPASSSelected = 1; // BYPASS`
545			`endcase`
546			`end`
547
548
549
550			`/**********************************************************************************`
551			`* *`
552			`* Multiplexing TDO data *`
553			`* *`
554			`**********************************************************************************/`
555
556			`// This multiplexer can be expanded with number of user registers`
557	38	mohor	`always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)`
558	36	mohor	`begin`
559			`if(ShiftIR \| Exit1IR)`
560			`tdo_pad_o <=#Tp TDOInstruction;`
561			`else`
562			`begin`
563			`case(LatchedJTAG_IR)`
564	37	mohor	`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
565			`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
566			`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
567	38	mohor	`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
568			`EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
569	36	mohor	`default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction`
570			`endcase`
571			`end`
572			`end`
573
574			`// Tristate control for tdo_pad_o pin`
575			`assign tdo_padoen_o = ShiftIR \| ShiftDR \| Exit1IR \| Exit1DR \| UpdateDR;`
576
577			`/**********************************************************************************`
578			`* *`
579			`* End: Multiplexing TDO data *`
580			`* *`
581			`**********************************************************************************/`
582
583			`endmodule`