URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] [cpu_behavioral.v] - Blame information for rev 158

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
//// cpu_behavioral.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2004/01/22 11:07:28  mohor
// test stall_test added.
//
// Revision 1.2  2004/01/17 18:01:31  mohor
// New version.
//
// Revision 1.1  2004/01/17 17:01:25  mohor
// Almost finished.
//
//
//
//
//
`include "timescale.v"
`include "dbg_cpu_defines.v"
 
 
 
module cpu_behavioral
                   (
                    // CPU signals
                    cpu_rst_i,
                    cpu_clk_o,
                    cpu_addr_i,
                    cpu_data_o,
                    cpu_data_i,
                    cpu_bp_o,
                    cpu_stall_i,
                    cpu_stb_i,
                    cpu_we_i,
                    cpu_ack_o,
                    cpu_rst_o
                   );
 
 
// CPU signals
input         cpu_rst_i;
output        cpu_clk_o;
input  [31:0] cpu_addr_i;
output [31:0] cpu_data_o;
input  [31:0] cpu_data_i;
output        cpu_bp_o;
input         cpu_stall_i;
input         cpu_stb_i;
input         cpu_we_i;
output        cpu_ack_o;
output        cpu_rst_o;
 
reg           cpu_clk_o;
reg    [31:0] cpu_data_o;
reg           cpu_bp_o;
reg           cpu_ack_o;
reg           cpu_ack_q;
wire          cpu_ack;
initial
begin
  cpu_clk_o = 1'b0;
  forever #5 cpu_clk_o = ~cpu_clk_o;
end
 
 
initial
begin
  cpu_bp_o = 1'b0;
end
 
assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
 
 
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
  if (cpu_rst_i)
    begin
      cpu_ack_o <= #1 1'b0;
      cpu_ack_q <= #1 1'b0;
    end
  else
    begin
      cpu_ack_o <= #1 cpu_ack;
      cpu_ack_q <= #1 cpu_ack_o;
    end
end
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
  if (cpu_rst_i)
    cpu_data_o <= #1 32'h12345678;
  else if (cpu_ack_o && (!cpu_ack_q))
    cpu_data_o <= #1 cpu_data_o + 32'h11111111;
end
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	101	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// cpu_behavioral.v ////`
4			`//// ////`
5			`//// ////`
6	139	igorm	`//// This file is part of the SoC Debug Interface. ////`
7	101	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	139	igorm	`// Revision 1.3 2004/01/22 11:07:28 mohor`
47			`// test stall_test added.`
48			`//`
49	120	mohor	`// Revision 1.2 2004/01/17 18:01:31 mohor`
50			`// New version.`
51			`//`
52	102	mohor	`// Revision 1.1 2004/01/17 17:01:25 mohor`
53			`// Almost finished.`
54	101	mohor	`//`
55			`//`
56			`//`
57			`//`
58	102	mohor	`//`
59	101	mohor	`include "timescale.v"
60			`include "dbg_cpu_defines.v"
61
62
63
64			`module cpu_behavioral`
65			`(`
66			`// CPU signals`
67			`cpu_rst_i,`
68			`cpu_clk_o,`
69			`cpu_addr_i,`
70			`cpu_data_o,`
71			`cpu_data_i,`
72			`cpu_bp_o,`
73			`cpu_stall_i,`
74			`cpu_stb_i,`
75			`cpu_we_i,`
76			`cpu_ack_o,`
77			`cpu_rst_o`
78			`);`
79
80
81			`// CPU signals`
82			`input cpu_rst_i;`
83			`output cpu_clk_o;`
84			`input [31:0] cpu_addr_i;`
85			`output [31:0] cpu_data_o;`
86			`input [31:0] cpu_data_i;`
87			`output cpu_bp_o;`
88			`input cpu_stall_i;`
89			`input cpu_stb_i;`
90			`input cpu_we_i;`
91			`output cpu_ack_o;`
92			`output cpu_rst_o;`
93
94			`reg cpu_clk_o;`
95	102	mohor	`reg [31:0] cpu_data_o;`
96	120	mohor	`reg cpu_bp_o;`
97	139	igorm	`reg cpu_ack_o;`
98			`reg cpu_ack_q;`
99			`wire cpu_ack;`
100	101	mohor	`initial`
101			`begin`
102			`cpu_clk_o = 1'b0;`
103			`forever #5 cpu_clk_o = ~cpu_clk_o;`
104			`end`
105
106
107	120	mohor	`initial`
108			`begin`
109			`cpu_bp_o = 1'b0;`
110			`end`
111	101	mohor
112	139	igorm	`assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;`
113	101	mohor
114
115
116			`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`
117			`begin`
118			`if (cpu_rst_i)`
119	139	igorm	`begin`
120			`cpu_ack_o <= #1 1'b0;`
121			`cpu_ack_q <= #1 1'b0;`
122			`end`
123			`else`
124			`begin`
125			`cpu_ack_o <= #1 cpu_ack;`
126			`cpu_ack_q <= #1 cpu_ack_o;`
127			`end`
128	101	mohor	`end`
129
130	139	igorm	`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`
131			`begin`
132			`if (cpu_rst_i)`
133			`cpu_data_o <= #1 32'h12345678;`
134			`else if (cpu_ack_o && (!cpu_ack_q))`
135			`cpu_data_o <= #1 cpu_data_o + 32'h11111111;`
136			`end`
137	101	mohor
138
139
140	139	igorm
141	101	mohor	`endmodule`
142

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] [cpu_behavioral.v] - Blame information for rev 158