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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] [dbg_tb.v] - Blame information for rev 158

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1 2 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  dbg_tb.v                                                    ////
4 
////                                                              ////
5 
////                                                              ////
6 139 igorm 
////  This file is part of the SoC Debug Interface.               ////
7 36 mohor 
////  http://www.opencores.org/projects/DebugInterface/           ////
8 2 mohor 
////                                                              ////
9 
////  Author(s):                                                  ////
10 80 mohor 
////       Igor Mohor (igorm@opencores.org)                       ////
11 2 mohor 
////                                                              ////
12 
////                                                              ////
13 
////  All additional information is avaliable in the README.txt   ////
14 
////  file.                                                       ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 101 mohor 
//// Copyright (C) 2000 - 2004 Authors                            ////
19 2 mohor 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
//
43 
// CVS Revision History
44 
//
45 
// $Log: not supported by cvs2svn $
46 145 igorm 
// Revision 1.44  2004/04/01 09:33:26  igorm
47 
// Typo fixed.
48 
//
49 142 igorm 
// Revision 1.43  2004/03/31 14:34:13  igorm
50 
// data_cnt_lim length changed to reduce number of warnings.
51 
//
52 141 igorm 
// Revision 1.42  2004/03/30 23:10:39  igorm
53 
// CRC checking of incoming CRC added to all tasks.
54 
//
55 140 igorm 
// Revision 1.41  2004/03/28 20:27:40  igorm
56 
// New release of the debug interface (3rd. release).
57 
//
58 139 igorm 
// Revision 1.40  2004/03/22 16:36:06  igorm
59 
// Temp version before changing dbg interface.
60 
//
61 138 igorm 
// Revision 1.39  2004/03/15 16:17:07  igorm
62 
// 'hz changed to 1'hz because Icarus complains.
63 
//
64 135 igorm 
// Revision 1.38  2004/01/30 10:24:02  mohor
65 
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
66 
// turned on.
67 
//
68 128 mohor 
// Revision 1.37  2004/01/25 14:10:25  mohor
69 
// Display for VATS added.
70 
//
71 124 mohor 
// Revision 1.36  2004/01/22 13:58:51  mohor
72 
// Port signals are all set to zero after reset.
73 
//
74 121 mohor 
// Revision 1.35  2004/01/22 11:07:28  mohor
75 
// test stall_test added.
76 
//
77 120 mohor 
// Revision 1.34  2004/01/20 14:24:08  mohor
78 
// Define name changed.
79 
//
80 117 mohor 
// Revision 1.33  2004/01/20 14:05:26  mohor
81 
// Data latching changed when testing WB.
82 
//
83 116 mohor 
// Revision 1.32  2004/01/20 10:23:21  mohor
84 
// More debug data added.
85 
//
86 115 mohor 
// Revision 1.31  2004/01/20 09:07:44  mohor
87 
// CRC generation iand verification in bench changed.
88 
//
89 114 mohor 
// Revision 1.30  2004/01/20 08:03:35  mohor
90 
// IDCODE test improved.
91 
//
92 113 mohor 
// Revision 1.29  2004/01/19 13:13:18  mohor
93 
// Define tap_defines.v added to test bench.
94 
//
95 111 mohor 
// Revision 1.28  2004/01/19 12:38:10  mohor
96 
// Waiting for "ready" improved.
97 
//
98 110 mohor 
// Revision 1.27  2004/01/17 18:01:31  mohor
99 
// New version.
100 
//
101 102 mohor 
// Revision 1.26  2004/01/17 17:01:25  mohor
102 
// Almost finished.
103 
//
104 101 mohor 
// Revision 1.25  2004/01/16 14:51:24  mohor
105 
// cpu registers added.
106 
//
107 99 mohor 
// Revision 1.24  2004/01/15 10:47:13  mohor
108 
// Working.
109 
//
110 96 mohor 
// Revision 1.23  2004/01/14 22:59:01  mohor
111 
// Temp version.
112 
//
113 95 mohor 
// Revision 1.22  2004/01/13 11:28:30  mohor
114 
// tmp version.
115 
//
116 93 mohor 
// Revision 1.21  2004/01/10 07:50:41  mohor
117 
// temp version.
118 
//
119 92 mohor 
// Revision 1.20  2004/01/09 12:49:23  mohor
120 
// tmp version.
121 
//
122 91 mohor 
// Revision 1.19  2004/01/08 17:53:12  mohor
123 
// tmp version.
124 
//
125 90 mohor 
// Revision 1.18  2004/01/07 11:59:48  mohor
126 
// temp4 version.
127 
//
128 89 mohor 
// Revision 1.17  2004/01/06 17:14:59  mohor
129 
// temp3 version.
130 
//
131 88 mohor 
// Revision 1.16  2004/01/05 12:16:50  mohor
132 
// tmp2 version.
133 
//
134 87 mohor 
// Revision 1.15  2003/12/23 14:26:01  mohor
135 
// New version of the debug interface. Not finished, yet.
136 
//
137 80 mohor 
// Revision 1.14  2003/10/23 16:16:30  mohor
138 
// CRC logic changed.
139 
//
140 73 mohor 
// Revision 1.13  2003/08/28 13:54:33  simons
141 
// Three more chains added for cpu debug access.
142 
//
143 63 simons 
// Revision 1.12  2002/05/07 14:44:52  mohor
144 
// mon_cntl_o signals that controls monitor mux added.
145 
//
146 47 mohor 
// Revision 1.11  2002/03/12 14:32:26  mohor
147 
// Few outputs for boundary scan chain added.
148 
//
149 38 mohor 
// Revision 1.10  2002/03/08 15:27:08  mohor
150 
// Structure changed. Hooks for jtag chain added.
151 
//
152 36 mohor 
// Revision 1.9  2001/10/19 11:39:20  mohor
153 
// dbg_timescale.v changed to timescale.v This is done for the simulation of
154 
// few different cores in a single project.
155 
//
156 17 mohor 
// Revision 1.8  2001/10/17 10:39:17  mohor
157 
// bs_chain_o added.
158 
//
159 15 mohor 
// Revision 1.7  2001/10/16 10:10:18  mohor
160 
// Signal names changed to lowercase.
161 
//
162 13 mohor 
// Revision 1.6  2001/10/15 09:52:50  mohor
163 
// Wishbone interface added, few fixes for better performance,
164 
// hooks for boundary scan testing added.
165 
//
166 12 mohor 
// Revision 1.5  2001/09/24 14:06:12  mohor
167 
// Changes connected to the OpenRISC access (SPR read, SPR write).
168 
//
169 11 mohor 
// Revision 1.4  2001/09/20 10:10:29  mohor
170 
// Working version. Few bugs fixed, comments added.
171 
//
172 9 mohor 
// Revision 1.3  2001/09/19 11:54:03  mohor
173 
// Minor changes for simulation.
174 
//
175 6 mohor 
// Revision 1.2  2001/09/18 14:12:43  mohor
176 
// Trace fixed. Some registers changed, trace simplified.
177 
//
178 5 mohor 
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
179 
// Initial official release.
180 
//
181 2 mohor 
// Revision 1.3  2001/06/01 22:23:40  mohor
182 
// This is a backup. It is not a fully working version. Not for use, yet.
183 
//
184 
// Revision 1.2  2001/05/18 13:10:05  mohor
185 
// Headers changed. All additional information is now avaliable in the README.txt file.
186 
//
187 
// Revision 1.1.1.1  2001/05/18 06:35:15  mohor
188 
// Initial release
189 
//
190 
//
191 
 
192 
 
193 17 mohor 
`include "timescale.v"
194 111 mohor 
`include "tap_defines.v"
195 2 mohor 
`include "dbg_defines.v"
196 80 mohor 
`include "dbg_wb_defines.v"
197 99 mohor 
`include "dbg_cpu_defines.v"
198 2 mohor 
 
199 139 igorm 
`define DBG_TEXT(TEXT)   $display("%0s", TEXT);
200 
//  `DBG_TEXT("Bla bla bla")
201 
//  $sformat(dbg_text, "\n\nbla 0x%0x 0x%0x\n\n", 32'h12345678, 16'h543);
202 
//  `DBG_TEXT(dbg_text)
203 
 
204 145 igorm 
// For common cpu routines
205 
`ifdef DBG_CPU0_SUPPORTED
206 
  `define DBG_CPU_SUPPORTED
207 
`else
208 
  `ifdef DBG_CPU1_SUPPORTED
209 
    `define DBG_CPU_SUPPORTED
210 
  `endif
211 
`endif
212 139 igorm 
 
213 2 mohor 
// Test bench
214 
module dbg_tb;
215 
 
216 80 mohor 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
217 2 mohor 
 
218 139 igorm 
reg   [999:0] dbg_text;
219 80 mohor 
reg   tms_pad_i;
220 
reg   tck_pad_i;
221 
reg   trst_pad_i;
222 
reg   tdi_pad_i;
223 
wire  tdo_pad_o;
224 
wire  tdo_padoe_o;
225 2 mohor 
 
226 80 mohor 
wire  shift_dr_o;
227 
wire  pause_dr_o;
228 
wire  update_dr_o;
229 102 mohor 
wire  capture_dr_o;
230 2 mohor 
 
231 80 mohor 
wire  extest_select_o;
232 
wire  sample_preload_select_o;
233 
wire  mbist_select_o;
234 
wire  debug_select_o;
235 2 mohor 
 
236 128 mohor 
reg   rst_i;
237 
 
238 139 igorm 
`ifdef DBG_WISHBONE_SUPPORTED
239 80 mohor 
// WISHBONE common signals
240 
reg   wb_clk_i;
241 
 
242 
// WISHBONE master interface
243 
wire [31:0] wb_adr_o;
244 
wire [31:0] wb_dat_o;
245 
wire [31:0] wb_dat_i;
246 
wire        wb_cyc_o;
247 
wire        wb_stb_o;
248 
wire  [3:0] wb_sel_o;
249 
wire        wb_we_o;
250 
wire        wb_ack_i;
251 
wire        wb_cab_o;
252 
wire        wb_err_i;
253 
wire  [2:0] wb_cti_o;
254 
wire  [1:0] wb_bte_o;
255 128 mohor 
`endif
256 2 mohor 
 
257 145 igorm 
`ifdef DBG_CPU0_SUPPORTED
258 101 mohor 
// CPU signals
259 145 igorm 
wire        cpu0_clk_i;
260 
wire [31:0] cpu0_addr_o;
261 
wire [31:0] cpu0_data_i;
262 
wire [31:0] cpu0_data_o;
263 
wire        cpu0_bp_i;
264 
wire        cpu0_stall_o;
265 
wire        cpu0_stb_o;
266 
wire        cpu0_we_o;
267 
wire        cpu0_ack_i;
268 
wire        cpu0_rst_o;
269 128 mohor 
`endif
270 101 mohor 
 
271 145 igorm 
`ifdef DBG_CPU1_SUPPORTED
272 
// CPU signals
273 
wire        cpu1_clk_i;
274 
wire [31:0] cpu1_addr_o;
275 
wire [31:0] cpu1_data_i;
276 
wire [31:0] cpu1_data_o;
277 
wire        cpu1_bp_i;
278 
wire        cpu1_stall_o;
279 
wire        cpu1_stb_o;
280 
wire        cpu1_we_o;
281 
wire        cpu1_ack_i;
282 
wire        cpu1_rst_o;
283 
`endif
284 
 
285 87 mohor 
// Text used for easier debugging
286 99 mohor 
reg [199:0] test_text;
287 139 igorm 
reg [`DBG_WB_CMD_LEN -1:0]  last_wb_cmd;
288 
reg [`DBG_CPU_CMD_LEN -1:0] last_cpu_cmd;
289 99 mohor 
reg [199:0] last_wb_cmd_text;
290 139 igorm 
reg [199:0] last_cpu_cmd_text;
291 2 mohor 
 
292 116 mohor 
reg  [31:0] wb_data [0:4095];   // Data that is written to (read from) wishbone is stored here.
293 2 mohor 
 
294 12 mohor 
 
295 116 mohor 
 
296 80 mohor 
wire  tdo_o;
297 12 mohor 
 
298 80 mohor 
wire  debug_tdi_i;
299 
wire  bs_chain_tdi_i;
300 
wire  mbist_tdi_i;
301 73 mohor 
 
302 80 mohor 
reg   test_enabled;
303 73 mohor 
 
304 80 mohor 
reg [31:0] result;
305 113 mohor 
reg [31:0] in_data_le, in_data_be;
306 
reg [31:0] id;
307 88 mohor 
 
308 110 mohor 
wire crc_match_in;
309 114 mohor 
reg [31:0] crc_in;
310 
reg [31:0] crc_out;
311 138 igorm 
reg [`DBG_TOP_STATUS_LEN -1:0] status;
312 139 igorm 
reg [`DBG_WB_STATUS_LEN -1:0]  status_wb;
313 
reg [`DBG_CPU_STATUS_LEN -1:0] status_cpu;
314 99 mohor 
 
315 139 igorm 
reg [`DBG_WB_ACC_TYPE_LEN -1:0]  read_acc_type;
316 
reg [`DBG_WB_ADR_LEN -1:0]       read_addr;
317 
reg [`DBG_WB_LEN_LEN -1:0]       read_length;
318 
reg [`DBG_CPU_CTRL_LEN -1:0]     read_ctrl_reg;
319 
 
320 145 igorm 
integer length_global;
321 80 mohor 
wire tdo;
322 73 mohor 
 
323 80 mohor 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
324 73 mohor 
 
325 145 igorm 
 
326 
 
327 80 mohor 
// Connecting TAP module
328 
tap_top i_tap_top (
329 101 mohor 
                    .tms_pad_i        (tms_pad_i),
330 
                    .tck_pad_i        (tck_pad_i),
331 
                    .trst_pad_i       (!trst_pad_i),
332 
                    .tdi_pad_i        (tdi_pad_i),
333 
                    .tdo_pad_o        (tdo_pad_o),
334 
                    .tdo_padoe_o      (tdo_padoe_o),
335 38 mohor 
 
336 80 mohor 
                    // TAP states
337 101 mohor 
                    .shift_dr_o       (shift_dr_o),
338 
                    .pause_dr_o       (pause_dr_o),
339 
                    .update_dr_o      (update_dr_o),
340 102 mohor 
                    .capture_dr_o     (capture_dr_o),
341 38 mohor 
 
342 80 mohor 
                    // Select signals for boundary scan or mbist
343 101 mohor 
                    .extest_select_o  (extest_select_o),
344 80 mohor 
                    .sample_preload_select_o(sample_preload_select_o),
345 101 mohor 
                    .mbist_select_o   (mbist_select_o),
346 
                    .debug_select_o   (debug_select_o),
347 2 mohor 
 
348 80 mohor 
                    // TDO signal that is connected to TDI of sub-modules.
349 101 mohor 
                    .tdo_o            (tdo_o),
350 38 mohor 
 
351 80 mohor 
                    // TDI signals from sub-modules
352 101 mohor 
                    .debug_tdi_i      (debug_tdi_i),        // from debug module
353 
                    .bs_chain_tdi_i   (bs_chain_tdi_i),  // from Boundary Scan Chain
354 
                    .mbist_tdi_i      (mbist_tdi_i)         // from Mbist Chain
355 73 mohor 
 
356 38 mohor 
               );
357 2 mohor 
 
358 
 
359 99 mohor 
// Connecting debug top module
360 80 mohor 
dbg_top i_dbg_top  (
361 101 mohor 
                    .tck_i            (tck_pad_i),
362 
                    .tdi_i            (tdo_o),
363 
                    .tdo_o            (debug_tdi_i),
364 128 mohor 
                    .rst_i            (rst_i),
365 80 mohor 
 
366 
                    // TAP states
367 101 mohor 
                    .shift_dr_i       (shift_dr_o),
368 
                    .pause_dr_i       (pause_dr_o),
369 
                    .update_dr_i      (update_dr_o),
370 80 mohor 
 
371 
                    // Instructions
372 128 mohor 
                    .debug_select_i   (debug_select_o)
373 12 mohor 
 
374 139 igorm 
                    `ifdef DBG_WISHBONE_SUPPORTED
375 80 mohor 
                    // WISHBONE common signals
376 128 mohor 
                    ,
377 101 mohor 
                    .wb_clk_i         (wb_clk_i),
378 80 mohor 
 
379 
                    // WISHBONE master interface
380 101 mohor 
                    .wb_adr_o         (wb_adr_o),
381 
                    .wb_dat_o         (wb_dat_o),
382 
                    .wb_dat_i         (wb_dat_i),
383 
                    .wb_cyc_o         (wb_cyc_o),
384 
                    .wb_stb_o         (wb_stb_o),
385 
                    .wb_sel_o         (wb_sel_o),
386 
                    .wb_we_o          (wb_we_o),
387 
                    .wb_ack_i         (wb_ack_i),
388 
                    .wb_cab_o         (wb_cab_o),
389 
                    .wb_err_i         (wb_err_i),
390 
                    .wb_cti_o         (wb_cti_o),
391 128 mohor 
                    .wb_bte_o         (wb_bte_o)
392 
                    `endif
393 101 mohor 
 
394 145 igorm 
                    `ifdef DBG_CPU0_SUPPORTED
395 101 mohor 
                    // CPU signals
396 128 mohor 
                    ,
397 145 igorm 
                    .cpu0_clk_i        (cpu0_clk_i),
398 
                    .cpu0_addr_o       (cpu0_addr_o),
399 
                    .cpu0_data_i       (cpu0_data_i),
400 
                    .cpu0_data_o       (cpu0_data_o),
401 
                    .cpu0_bp_i         (cpu0_bp_i),
402 
                    .cpu0_stall_o      (cpu0_stall_o),
403 
                    .cpu0_stb_o        (cpu0_stb_o),
404 
                    .cpu0_we_o         (cpu0_we_o),
405 
                    .cpu0_ack_i        (cpu0_ack_i),
406 
                    .cpu0_rst_o        (cpu0_rst_o)
407 128 mohor 
                    `endif
408 101 mohor 
 
409 145 igorm 
                    `ifdef DBG_CPU1_SUPPORTED
410 
                    // CPU signals
411 
                    ,
412 
                    .cpu1_clk_i        (cpu1_clk_i),
413 
                    .cpu1_addr_o       (cpu1_addr_o),
414 
                    .cpu1_data_i       (cpu1_data_i),
415 
                    .cpu1_data_o       (cpu1_data_o),
416 
                    .cpu1_bp_i         (cpu1_bp_i),
417 
                    .cpu1_stall_o      (cpu1_stall_o),
418 
                    .cpu1_stb_o        (cpu1_stb_o),
419 
                    .cpu1_we_o         (cpu1_we_o),
420 
                    .cpu1_ack_i        (cpu1_ack_i),
421 
                    .cpu1_rst_o        (cpu1_rst_o)
422 
                    `endif
423 101 mohor 
 
424 
 
425 145 igorm 
 
426 80 mohor 
                   );
427 12 mohor 
 
428 
 
429 139 igorm 
`ifdef DBG_WISHBONE_SUPPORTED
430 80 mohor 
wb_slave_behavioral wb_slave
431 
                   (
432 101 mohor 
                    .CLK_I            (wb_clk_i),
433 128 mohor 
                    .RST_I            (rst_i),
434 101 mohor 
                    .ACK_O            (wb_ack_i),
435 
                    .ADR_I            (wb_adr_o),
436 
                    .CYC_I            (wb_cyc_o),
437 
                    .DAT_O            (wb_dat_i),
438 
                    .DAT_I            (wb_dat_o),
439 
                    .ERR_O            (wb_err_i),
440 
                    .RTY_O            (),      // NOT USED for now!
441 
                    .SEL_I            (wb_sel_o),
442 
                    .STB_I            (wb_stb_o),
443 
                    .WE_I             (wb_we_o),
444 
                    .CAB_I            (1'b0)
445 80 mohor 
                   );
446 128 mohor 
`endif
447 2 mohor 
 
448 
 
449 145 igorm 
`ifdef DBG_CPU0_SUPPORTED
450 
cpu_behavioral i_cpu0_behavioral
451 101 mohor 
                   (
452 
                    // CPU signals
453 128 mohor 
                    .cpu_rst_i        (rst_i),
454 145 igorm 
                    .cpu_clk_o        (cpu0_clk_i),
455 
                    .cpu_addr_i       (cpu0_addr_o),
456 
                    .cpu_data_o       (cpu0_data_i),
457 
                    .cpu_data_i       (cpu0_data_o),
458 
                    .cpu_bp_o         (cpu0_bp_i),
459 
                    .cpu_stall_i      (cpu0_stall_o),
460 
                    .cpu_stb_i        (cpu0_stb_o),
461 
                    .cpu_we_i         (cpu0_we_o),
462 
                    .cpu_ack_o        (cpu0_ack_i),
463 
                    .cpu_rst_o        (cpu0_rst_o)
464 101 mohor 
                   );
465 128 mohor 
`endif
466 101 mohor 
 
467 
 
468 
 
469 145 igorm 
`ifdef DBG_CPU1_SUPPORTED
470 
cpu_behavioral i_cpu1_behavioral
471 
                   (
472 
                    // CPU signals
473 
                    .cpu_rst_i        (rst_i),
474 
                    .cpu_clk_o        (cpu1_clk_i),
475 
                    .cpu_addr_i       (cpu1_addr_o),
476 
                    .cpu_data_o       (cpu1_data_i),
477 
                    .cpu_data_i       (cpu1_data_o),
478 
                    .cpu_bp_o         (cpu1_bp_i),
479 
                    .cpu_stall_i      (cpu1_stall_o),
480 
                    .cpu_stb_i        (cpu1_stb_o),
481 
                    .cpu_we_i         (cpu1_we_o),
482 
                    .cpu_ack_o        (cpu1_ack_i),
483 
                    .cpu_rst_o        (cpu1_rst_o)
484 
                   );
485 
`endif
486 
 
487 
 
488 
 
489 80 mohor 
// Initial values
490 2 mohor 
initial
491 
begin
492 80 mohor 
  trst_pad_i = 1'b1;
493 
  tms_pad_i = 1'hz;
494 
  tck_pad_i = 1'hz;
495 
  tdi_pad_i = 1'hz;
496 
 
497 
  #100;
498 
  trst_pad_i = 1'b0;
499 
  #100;
500 
  trst_pad_i = 1'b1;
501 2 mohor 
end
502 
 
503 80 mohor 
initial
504 
begin
505 120 mohor 
  test_enabled = 1'b0;
506 128 mohor 
  rst_i = 1'b0;
507 80 mohor 
  #1000;
508 128 mohor 
  rst_i = 1'b1;
509 80 mohor 
  #1000;
510 128 mohor 
  rst_i = 1'b0;
511 2 mohor 
 
512 80 mohor 
  // Initial values for wishbone slave model
513 139 igorm 
  `ifdef DBG_WISHBONE_SUPPORTED
514 
//  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
515 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h35, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
516 128 mohor 
  `endif
517 120 mohor 
  #1 test_enabled<=#1 1'b1;
518 80 mohor 
end
519 
 
520 139 igorm 
`ifdef DBG_WISHBONE_SUPPORTED
521 80 mohor 
initial
522 2 mohor 
begin
523 80 mohor 
  wb_clk_i = 1'b0;
524 
  forever #5 wb_clk_i = ~wb_clk_i;
525 2 mohor 
end
526 128 mohor 
`endif
527 2 mohor 
 
528 80 mohor 
always @ (posedge test_enabled)
529 
begin
530 
  $display("//////////////////////////////////////////////////////////////////");
531 
  $display("//                                                              //");
532 
  $display("//  (%0t) dbg_tb starting                                     //", $time);
533 
  $display("//                                                              //");
534 
  $display("//////////////////////////////////////////////////////////////////");
535 2 mohor 
 
536 124 mohor 
  $display("TEST: DBG_TEST");
537 
 
538 
 
539 80 mohor 
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
540 2 mohor 
 
541 80 mohor 
  reset_tap;
542 95 mohor 
 
543 
  #500;
544 80 mohor 
  goto_run_test_idle;
545 12 mohor 
 
546 145 igorm 
//  `ifdef DBG_CPU0_SUPPORTED
547 139 igorm 
//  // Test stall signal
548 145 igorm 
//  stall_test_cpu0;
549 139 igorm 
//  `endif
550 120 mohor 
 
551 80 mohor 
  // Testing read and write to internal registers
552 
  #10000;
553 111 mohor 
 
554 138 igorm 
  id_test;
555 12 mohor 
 
556 80 mohor 
  set_instruction(`DEBUG);
557 
  #10000;
558 2 mohor 
 
559 138 igorm 
 
560 
 
561 
 
562 
 
563 
 
564 
 
565 
 
566 
 
567 
  #100000;
568 139 igorm 
  `ifdef DBG_WISHBONE_SUPPORTED
569 
  module_select(`DBG_TOP_WISHBONE_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
570 12 mohor 
 
571 80 mohor 
  #10000;
572 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h3, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
573 
//  debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
574 
  debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
575 2 mohor 
 
576 139 igorm 
  #10000;
577 
  test_text = "debug_wishbone_rd_comm";
578 
  debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
579 
  $display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
580 
  debug_wishbone_go(1'b0, 1'b0);
581 
  debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
582 
  $display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
583 
 
584 
  debug_wishbone_go(1'b0, 1'b0);
585 
 
586 138 igorm 
  #100000;
587 139 igorm 
//  debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345224, 16'h7, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
588 
  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345223, 16'h8, 1'b0, "read8 1"); // {command, ready, addr, length, gen_crc_err, text}
589 
  #100000;
590 
  debug_wishbone_go(1'b0, 1'b0);
591 138 igorm 
 
592 139 igorm 
 
593 
/*
594 
//  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
595 
//  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
596 
//  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
597 88 mohor 
//
598 139 igorm 
//  debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
599 
//  debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
600 88 mohor 
//
601 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
602 88 mohor 
//
603 139 igorm 
//  debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
604 2 mohor 
 
605 80 mohor 
  #10000;
606 
 
607 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
608 87 mohor 
 
609 
  #10000;
610 96 mohor 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
611 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 3"); // {command, ready, addr, length, gen_crc_err, text}
612 80 mohor 
 
613 
  #10000;
614 96 mohor 
  wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2);   // (`ERR_RESPONSE, wbs_waits, wbs_retries);
615 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 4"); // {command, ready, addr, length, gen_crc_err, text}
616 80 mohor 
 
617 
  #10000;
618 116 mohor 
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 1"); // {command, ready, addr, length, gen_crc_err, text}
619 80 mohor 
 
620 87 mohor 
  #10000;
621 116 mohor 
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 2"); // {command, ready, addr, length, gen_crc_err, text}
622 80 mohor 
 
623 87 mohor 
  #10000;
624 96 mohor 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
625 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, "read32 5"); // {command, ready, addr, length, gen_crc_err, text}
626 80 mohor 
 
627 87 mohor 
  #10000;
628 139 igorm 
  debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, text}
629 87 mohor 
 
630 
  #10000;
631 139 igorm 
  debug_wishbone(`DBG_WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, text}
632 87 mohor 
 
633 88 mohor 
  #10000;
634 139 igorm 
  debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, text}
635 87 mohor 
 
636 88 mohor 
  #10000;
637 116 mohor 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 1"); // {command, ready, addr, length, gen_crc_err, text}
638 87 mohor 
 
639 89 mohor 
  #10000;
640 139 igorm 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
641 
//  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
642 88 mohor 
 
643 89 mohor 
  #10000;
644 139 igorm 
//  debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
645 
//  debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
646 88 mohor 
 
647 90 mohor 
  #10000;
648 139 igorm 
//  debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
649 
//  debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
650 89 mohor 
 
651 90 mohor 
  #10000;
652 116 mohor 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
653 139 igorm 
*/
654 
  `endif  // DBG_WISHBONE_SUPPORTED
655 89 mohor 
 
656 145 igorm 
  `ifdef DBG_CPU0_SUPPORTED
657 99 mohor 
  #10000;
658 145 igorm 
  module_select(`DBG_TOP_CPU0_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
659 89 mohor 
 
660 101 mohor 
 
661 
 
662 
 
663 
  // Select cpu0
664 139 igorm 
 
665 99 mohor 
  #10000;
666 139 igorm 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
667 90 mohor 
 
668 99 mohor 
  #10000;
669 139 igorm 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
670 101 mohor 
  // Read register
671 
  #10000;
672 
 
673 139 igorm 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
674 
 
675 101 mohor 
  #10000;
676 139 igorm 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
677 
  // Read register
678 
  #10000;
679 90 mohor 
 
680 139 igorm 
  // Reset cpu on
681 145 igorm 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text}
682 101 mohor 
  #10000;
683 99 mohor 
 
684 139 igorm 
  // Reset cpu off
685 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
686 101 mohor 
  #10000;
687 
 
688 139 igorm 
  // Stall cpu
689 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
690 101 mohor 
  #10000;
691 
 
692 139 igorm 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
693 101 mohor 
  #10000;
694 
 
695 139 igorm 
  // Stall cpu0
696 
  debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
697 
  $display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
698 101 mohor 
  #10000;
699 
 
700 139 igorm 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
701 
  // write to cpu 32-bit
702 101 mohor 
  #10000;
703 
 
704 139 igorm 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
705 
 
706 101 mohor 
  #10000;
707 
 
708 139 igorm 
  // read from cpu 32-bit
709 101 mohor 
  #10000;
710 
 
711 
  #10000;
712 
 
713 145 igorm 
  `endif  // DBG_CPU0_SUPPORTED
714 101 mohor 
 
715 110 mohor 
 
716 145 igorm 
  `ifdef DBG_CPU1_SUPPORTED
717 
  #10000;
718 
  module_select(`DBG_TOP_CPU1_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
719 110 mohor 
 
720 
 
721 
 
722 
 
723 145 igorm 
  // Select cpu1
724 110 mohor 
 
725 145 igorm 
  #10000;
726 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
727 110 mohor 
 
728 145 igorm 
  #10000;
729 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
730 
  // Read register
731 
  #10000;
732 
 
733 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
734 
 
735 
  #10000;
736 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
737 
  // Read register
738 
  #10000;
739 
 
740 
  // Reset cpu on
741 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text}
742 
  #10000;
743 
 
744 
  // Reset cpu off
745 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
746 
  #10000;
747 
 
748 
  // Stall cpu
749 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
750 
  #10000;
751 
 
752 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
753 
  #10000;
754 
 
755 
  // Stall cpu1
756 
  debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
757 
  $display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
758 
  #10000;
759 
 
760 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
761 
  // write to cpu 32-bit
762 
  #10000;
763 
 
764 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
765 
 
766 
  #10000;
767 
 
768 
  // read from cpu 32-bit
769 
  #10000;
770 
 
771 
  #10000;
772 
 
773 
  `endif  // DBG_CPU1_SUPPORTED
774 
 
775 
 
776 
 
777 
 
778 
 
779 
 
780 
 
781 
 
782 
 
783 80 mohor 
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
784 124 mohor 
  $display("STATUS: passed");
785 95 mohor 
  $display("\n\nSimulation end.");
786 5 mohor 
  #1000 $stop;
787 80 mohor 
 
788 2 mohor 
end
789 
 
790 80 mohor 
 
791 145 igorm 
`ifdef DBG_CPU0_SUPPORTED
792 
task stall_test_cpu0;
793 120 mohor 
  integer i;
794 
 
795 
  begin
796 145 igorm 
    test_text = "stall_test_cpu0";
797 
    $display("\n\n(%0t) stall_test_cpu0 started", $time);
798 120 mohor 
 
799 
    // Set bp_i active for 1 clock cycle and check is stall is set or not
800 145 igorm 
    check_stall_cpu0(0); // Should not be set at the beginning
801 
    @ (posedge cpu0_clk_i);
802 
    #1 dbg_tb.i_cpu0_behavioral.cpu_bp_o = 1'b1;
803 
    #1 check_stall_cpu0(1); // set?
804 
    @ (posedge cpu0_clk_i);
805 
    #1 dbg_tb.i_cpu0_behavioral.cpu_bp_o = 1'b0;
806 
    #1 check_stall_cpu0(1); // set?
807 120 mohor 
 
808 
    gen_clk(1);
809 145 igorm 
    #1 check_stall_cpu0(1); // set?
810 120 mohor 
 
811 
    // Unstall with register
812 
    set_instruction(`DEBUG);
813 145 igorm 
    module_select(`DBG_TOP_CPU0_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
814 
    #1 check_stall_cpu0(1); // set?
815 139 igorm 
// igor !!!    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
816 145 igorm 
    #1 check_stall_cpu0(1); // set?
817 139 igorm 
    debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
818 145 igorm 
    #1 check_stall_cpu0(0); // reset?
819 120 mohor 
 
820 
    // Set stall with register
821 139 igorm 
// igor !!!    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
822 145 igorm 
    #1 check_stall_cpu0(0); // reset?
823 139 igorm 
    debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
824 145 igorm 
    #1 check_stall_cpu0(1); // set?
825 120 mohor 
 
826 
    // Unstall with register
827 139 igorm 
// igor !!!    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
828 145 igorm 
    #1 check_stall_cpu0(1); // set?
829 139 igorm 
    debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
830 145 igorm 
    #1 check_stall_cpu0(0); // reset?
831 120 mohor 
 
832 145 igorm 
    $display("\n\n(%0t) stall_test_cpu0 passed\n\n", $time);
833 120 mohor 
  end
834 145 igorm 
endtask   // stall_test_cpu0
835 120 mohor 
 
836 
 
837 145 igorm 
task check_stall_cpu0;
838 120 mohor 
  input should_be_set;
839 
  begin
840 145 igorm 
    if (should_be_set && (!cpu0_stall_o))
841 120 mohor 
      begin
842 145 igorm 
        $display ("\t\t(%0t) ERROR: cpu0_stall_o is not set but should be.", $time);
843 120 mohor 
        $stop;
844 
      end
845 145 igorm 
    if ((!should_be_set) && cpu0_stall_o)
846 120 mohor 
      begin
847 145 igorm 
        $display ("\t\t(%0t) ERROR: cpu0_stall_o set but shouldn't be.", $time);
848 120 mohor 
        $stop;
849 
      end
850 
  end
851 145 igorm 
endtask   // check_stall_cpu0
852 
`endif  // DBG_CPU0_SUPPORTED
853 120 mohor 
 
854 
 
855 80 mohor 
task initialize_memory;
856 
  input [31:0] start_addr;
857 
  input [31:0] length;
858 
  integer i;
859 
  reg [31:0] addr;
860 
  begin
861 116 mohor 
    for (i=0; i<length; i=i+4)  // This data will be return from wb slave
862 80 mohor 
      begin
863 
        addr = start_addr + i;
864 139 igorm 
        `ifdef DBG_WISHBONE_SUPPORTED
865 96 mohor 
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
866 128 mohor 
        `endif
867 80 mohor 
      end
868 116 mohor 
    for (i=0; i<4096; i=i+1)  // This data will be written to wb slave
869 
      begin
870 
        wb_data[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
871 
      end
872 80 mohor 
  end
873 
endtask
874 
 
875 
 
876 138 igorm 
task id_test;
877 
  begin
878 
    test_text = "id_test";
879 
    $display("\n\n(%0t) TEST: id_test", $time);
880 80 mohor 
 
881 138 igorm 
    set_instruction(`IDCODE);
882 
    read_id_code(id);
883 
 
884 139 igorm 
    `ifdef DBG_MORE_INFO
885 138 igorm 
      $display("\tRead ID     = 0x%0x", id);
886 
      $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
887 
    `endif
888 
 
889 
    if (id==`IDCODE_VALUE)
890 
      $display("(%0t) STATUS: passed\n", $time);
891 
    else
892 
      $display("(%0t) STATUS: failed (Read ID = 0x%0x, Expected ID = 0x%0x\n", $time, id, `IDCODE_VALUE);
893 
  end
894 
endtask // id_test
895 
 
896 
 
897 2 mohor 
// Generation of the TCLK signal
898 80 mohor 
task gen_clk;
899 
  input [7:0] num;
900 2 mohor 
  integer i;
901 
  begin
902 80 mohor 
    for(i=0; i<num; i=i+1)
903 2 mohor 
      begin
904 80 mohor 
        #TCLK tck_pad_i<=1;
905 
        #TCLK tck_pad_i<=0;
906 2 mohor 
      end
907 
  end
908 
endtask
909 
 
910 
 
911 
// TAP reset
912 80 mohor 
task reset_tap;
913 2 mohor 
  begin
914 80 mohor 
    $display("(%0t) Task reset_tap", $time);
915 
    tms_pad_i<=#1 1'b1;
916 95 mohor 
    gen_clk(5);
917 2 mohor 
  end
918 
endtask
919 
 
920 
 
921 
// Goes to RunTestIdle state
922 80 mohor 
task goto_run_test_idle;
923 2 mohor 
  begin
924 80 mohor 
    $display("(%0t) Task goto_run_test_idle", $time);
925 
    tms_pad_i<=#1 1'b0;
926 
    gen_clk(1);
927 2 mohor 
  end
928 
endtask
929 
 
930 
 
931 115 mohor 
 
932 2 mohor 
// sets the instruction to the IR register and goes to the RunTestIdle state
933 80 mohor 
task set_instruction;
934 
  input [3:0] instr;
935 2 mohor 
  integer i;
936 
 
937 
  begin
938 115 mohor 
    case (instr)
939 139 igorm 
      `ifdef DBG_MORE_INFO
940 138 igorm 
        `EXTEST          : $display("(%0t) Task set_instruction (EXTEST)", $time);
941 
        `SAMPLE_PRELOAD  : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
942 
        `IDCODE          : $display("(%0t) Task set_instruction (IDCODE)", $time);
943 
        `DEBUG           : $display("(%0t) Task set_instruction (DEBUG)", $time);
944 
        `MBIST           : $display("(%0t) Task set_instruction (MBIST)", $time);
945 
        `BYPASS          : $display("(%0t) Task set_instruction (BYPASS)", $time);
946 
      `else
947 
        `EXTEST          : ;
948 
        `SAMPLE_PRELOAD  : ;
949 
        `IDCODE          : ;
950 
        `DEBUG           : ;
951 
        `MBIST           : ;
952 
        `BYPASS          : ;
953 
      `endif
954 
        default
955 
                         begin
956 
                           $display("(*E) (%0t) Task set_instruction: Unsupported instruction !!!", $time);
957 
                           $stop;
958 
                         end
959 115 mohor 
    endcase
960 
 
961 80 mohor 
    tms_pad_i<=#1 1;
962 
    gen_clk(2);
963 
    tms_pad_i<=#1 0;
964 
    gen_clk(2);  // we are in shiftIR
965 2 mohor 
 
966 
    for(i=0; i<`IR_LENGTH-1; i=i+1)
967 
    begin
968 80 mohor 
      tdi_pad_i<=#1 instr[i];
969 
      gen_clk(1);
970 2 mohor 
    end
971 
 
972 80 mohor 
    tdi_pad_i<=#1 instr[i]; // last shift
973 
    tms_pad_i<=#1 1;        // going out of shiftIR
974 
    gen_clk(1);
975 135 igorm 
    tdi_pad_i<=#1 1'hz;    // tri-state
976 80 mohor 
    gen_clk(1);
977 
    tms_pad_i<=#1 0;
978 
    gen_clk(1);       // we are in RunTestIdle
979 2 mohor 
  end
980 
endtask
981 
 
982 
 
983 80 mohor 
// Reads the ID code
984 
task read_id_code;
985 113 mohor 
  output [31:0] code;
986 
  reg    [31:0] code;
987 80 mohor 
  begin
988 139 igorm 
    `ifdef DBG_MORE_INFO
989 138 igorm 
      $display("(%0t) Task read_id_code", $time);
990 
    `endif
991 80 mohor 
    tms_pad_i<=#1 1;
992 
    gen_clk(1);
993 
    tms_pad_i<=#1 0;
994 
    gen_clk(2);  // we are in shiftDR
995 
 
996 
    tdi_pad_i<=#1 0;
997 
    gen_clk(31);
998 
 
999 
    tms_pad_i<=#1 1;        // going out of shiftIR
1000 
    gen_clk(1);
1001 
 
1002 113 mohor 
    code = in_data_le;
1003 
 
1004 135 igorm 
    tdi_pad_i<=#1 1'hz; // tri-state
1005 80 mohor 
    gen_clk(1);
1006 
    tms_pad_i<=#1 0;
1007 
    gen_clk(1);       // we are in RunTestIdle
1008 
  end
1009 
endtask
1010 
 
1011 
 
1012 138 igorm 
// sets the selected module and goes to the RunTestIdle state
1013 
task module_select;
1014 139 igorm 
  input [`DBG_TOP_MODULE_ID_LENGTH -1:0]  data;
1015 138 igorm 
  input                           gen_crc_err;
1016 
  integer                         i;
1017 
 
1018 2 mohor 
  begin
1019 99 mohor 
    case (data)
1020 145 igorm 
      `DBG_TOP_CPU0_DEBUG_MODULE      : $display("(%0t) Task module_select (DBG_TOP_CPU0_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
1021 
      `DBG_TOP_CPU1_DEBUG_MODULE      : $display("(%0t) Task module_select (DBG_TOP_CPU1_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
1022 139 igorm 
      `DBG_TOP_WISHBONE_DEBUG_MODULE : $display("(%0t) Task module_select (DBG_TOP_WISHBONE_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
1023 138 igorm 
      default                : $display("(%0t) Task module_select (ERROR!!! Unknown module selected)", $time);
1024 99 mohor 
    endcase
1025 
 
1026 138 igorm 
    tms_pad_i<=#1 1'b1;
1027 80 mohor 
    gen_clk(1);
1028 138 igorm 
    tms_pad_i<=#1 1'b0;
1029 80 mohor 
    gen_clk(2);  // we are in shiftDR
1030 2 mohor 
 
1031 138 igorm 
    status = {`DBG_TOP_STATUS_LEN{1'b0}};    // Initialize status to all 0's
1032 
    crc_out = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1033 
    tdi_pad_i<=#1 1'b1; // module_select bit
1034 114 mohor 
    calculate_crc(1'b1);
1035 80 mohor 
    gen_clk(1);
1036 
 
1037 139 igorm 
    for(i=`DBG_TOP_MODULE_ID_LENGTH -1; i>=0; i=i-1) // Shifting module ID
1038 2 mohor 
    begin
1039 80 mohor 
      tdi_pad_i<=#1 data[i];
1040 114 mohor 
      calculate_crc(data[i]);
1041 80 mohor 
      gen_clk(1);
1042 2 mohor 
    end
1043 
 
1044 138 igorm 
    for(i=`DBG_TOP_CRC_LEN -1; i>=0; i=i-1)
1045 2 mohor 
    begin
1046 99 mohor 
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
1047 114 mohor 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
1048 99 mohor 
      else
1049 114 mohor 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
1050 99 mohor 
 
1051 80 mohor 
      gen_clk(1);
1052 2 mohor 
    end
1053 
 
1054 135 igorm 
    tdi_pad_i<=#1 1'hz;  // tri-state
1055 99 mohor 
 
1056 138 igorm 
    crc_in = {`DBG_TOP_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1057 80 mohor 
 
1058 138 igorm 
    for(i=`DBG_TOP_STATUS_LEN -1; i>=0; i=i-1)
1059 
      begin
1060 
        gen_clk(1);     // Generating 1 clock to read out a status bit.
1061 
        status[i] = tdo;
1062 
      end
1063 110 mohor 
 
1064 138 igorm 
    for(i=0; i<`DBG_TOP_CRC_LEN -1; i=i+1)
1065 80 mohor 
      gen_clk(1);
1066 
 
1067 138 igorm 
    tms_pad_i<=#1 1'b1;
1068 80 mohor 
    gen_clk(1);         // to exit1_dr
1069 
 
1070 140 igorm 
    if (~crc_match_in)
1071 
      begin
1072 
        $display("(%0t) Incoming CRC failed !!!", $time);
1073 
        $stop;
1074 
      end
1075 
 
1076 138 igorm 
    tms_pad_i<=#1 1'b1;
1077 
    gen_clk(1);         // to update_dr
1078 
    tms_pad_i<=#1 1'b0;
1079 
    gen_clk(1);         // to run_test_idle
1080 
 
1081 
    if (|status)
1082 110 mohor 
      begin
1083 140 igorm 
        $write("(*E) (%0t) Module select error: ", $time);
1084 138 igorm 
        casex (status)
1085 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1086 139 igorm 
          4'bx1xx : $display("Non-existing module selected !!!\n\n", $time);
1087 
          4'bxx1x : $display("Status[1] should be 1'b0 !!!\n\n", $time);
1088 138 igorm 
          4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
1089 
        endcase
1090 110 mohor 
        $stop;
1091 
      end
1092 2 mohor 
  end
1093 138 igorm 
endtask   // module_select
1094 2 mohor 
 
1095 
 
1096 87 mohor 
 
1097 
 
1098 139 igorm 
`ifdef DBG_WISHBONE_SUPPORTED
1099 80 mohor 
task debug_wishbone;
1100 138 igorm 
  input [`DBG_WB_CMD_LEN -1:0]   command;
1101 87 mohor 
  input         ready;
1102 138 igorm 
  input [`DBG_WB_ADR_LEN -1:0]  addr;
1103 
  input [`DBG_WB_LEN_LEN -1:0]  length;
1104 99 mohor 
  input         gen_crc_err;
1105 87 mohor 
  input [99:0]  text;
1106 80 mohor 
  integer i;
1107 
 
1108 2 mohor 
  begin
1109 80 mohor 
   $write("(%0t) Task debug_wishbone: ", $time);
1110 2 mohor 
 
1111 87 mohor 
    test_text = text;
1112 36 mohor 
 
1113 80 mohor 
    case (command)
1114 139 igorm 
      `DBG_WB_READ8    :
1115 80 mohor 
        begin
1116 110 mohor 
          $display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1117 139 igorm 
          debug_wishbone_wr_comm(`DBG_WB_READ8, addr, length, gen_crc_err);
1118 
          last_wb_cmd = `DBG_WB_READ8;  last_wb_cmd_text = "DBG_WB_READ8";
1119 
#10000;
1120 145 igorm 
          length_global = length + 1;
1121 139 igorm 
          debug_wishbone_go(ready, gen_crc_err);
1122 80 mohor 
        end
1123 139 igorm 
      `DBG_WB_READ16   :
1124 80 mohor 
        begin
1125 110 mohor 
          $display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1126 139 igorm 
          debug_wishbone_wr_comm(`DBG_WB_READ16, addr, length, gen_crc_err);
1127 
          last_wb_cmd = `DBG_WB_READ16;  last_wb_cmd_text = "DBG_WB_READ16";
1128 
#10000;
1129 145 igorm 
          length_global = length + 1;
1130 139 igorm 
          debug_wishbone_go(ready, gen_crc_err);
1131 80 mohor 
        end
1132 139 igorm 
      `DBG_WB_READ32   :
1133 80 mohor 
        begin
1134 110 mohor 
          $display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1135 139 igorm 
          debug_wishbone_wr_comm(`DBG_WB_READ32, addr, length, gen_crc_err);
1136 
          last_wb_cmd = `DBG_WB_READ32;  last_wb_cmd_text = "DBG_WB_READ32";
1137 
#10000;
1138 145 igorm 
          length_global = length + 1;
1139 139 igorm 
          debug_wishbone_go(ready, gen_crc_err);
1140 80 mohor 
        end
1141 139 igorm 
      `DBG_WB_WRITE8   :
1142 80 mohor 
        begin
1143 99 mohor 
          $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1144 139 igorm 
          debug_wishbone_wr_comm(`DBG_WB_WRITE8, addr, length, gen_crc_err);
1145 
          last_wb_cmd = `DBG_WB_WRITE8;  last_wb_cmd_text = "DBG_WB_WRITE8";
1146 
#10000;
1147 145 igorm 
          length_global = length + 1;
1148 139 igorm 
          debug_wishbone_go(ready, gen_crc_err);
1149 80 mohor 
        end
1150 139 igorm 
      `DBG_WB_WRITE16  :
1151 80 mohor 
        begin
1152 99 mohor 
          $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1153 139 igorm 
          debug_wishbone_wr_comm(`DBG_WB_WRITE16, addr, length, gen_crc_err);
1154 
          last_wb_cmd = `DBG_WB_WRITE16;  last_wb_cmd_text = "DBG_WB_WRITE16";
1155 
#10000;
1156 145 igorm 
          length_global = length + 1;
1157 139 igorm 
          debug_wishbone_go(ready, gen_crc_err);
1158 80 mohor 
        end
1159 139 igorm 
      `DBG_WB_WRITE32  :
1160 80 mohor 
        begin
1161 99 mohor 
          $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1162 139 igorm 
          debug_wishbone_wr_comm(`DBG_WB_WRITE32, addr, length, gen_crc_err);
1163 
          last_wb_cmd = `DBG_WB_WRITE32;  last_wb_cmd_text = "DBG_WB_WRITE32";
1164 
#10000;
1165 145 igorm 
          length_global = length + 1;
1166 139 igorm 
          debug_wishbone_go(ready, gen_crc_err);
1167 80 mohor 
        end
1168 139 igorm 
      default:
1169 80 mohor 
        begin
1170 139 igorm 
          $display("(*E) debug_wishbone : Unsupported instruction !!!");
1171 
          $stop;
1172 80 mohor 
        end
1173 
    endcase
1174 2 mohor 
  end
1175 87 mohor 
endtask       // debug_wishbone
1176 2 mohor 
 
1177 
 
1178 80 mohor 
 
1179 
 
1180 
 
1181 
 
1182 139 igorm 
task debug_wishbone_wr_comm;
1183 
  input [`DBG_WB_ACC_TYPE_LEN -1:0]   acc_type;
1184 
  input [`DBG_WB_ADR_LEN -1:0]        addr;
1185 
  input [`DBG_WB_LEN_LEN -1:0]        length;
1186 
  input                               gen_crc_err;
1187 
  integer                             i;
1188 
  reg   [`DBG_WB_CMD_LEN -1:0]        command;
1189 80 mohor 
 
1190 
  begin
1191 139 igorm 
    $display("(%0t) Task debug_wishbone_wr_comm: ", $time);
1192 80 mohor 
 
1193 139 igorm 
    command = `DBG_WB_WR_COMM;
1194 138 igorm 
    tms_pad_i<=#1 1'b1;
1195 80 mohor 
    gen_clk(1);
1196 138 igorm 
    tms_pad_i<=#1 1'b0;
1197 80 mohor 
    gen_clk(2);  // we are in shiftDR
1198 
 
1199 138 igorm 
    crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1200 99 mohor 
 
1201 138 igorm 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1202 114 mohor 
    calculate_crc(1'b0);
1203 80 mohor 
    gen_clk(1);
1204 
 
1205 138 igorm 
    for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
1206 80 mohor 
    begin
1207 
      tdi_pad_i<=#1 command[i]; // command
1208 114 mohor 
      calculate_crc(command[i]);
1209 80 mohor 
      gen_clk(1);
1210 
    end
1211 
 
1212 139 igorm 
    for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
1213 
    begin
1214 
      tdi_pad_i<=#1 acc_type[i]; // command
1215 
      calculate_crc(acc_type[i]);
1216 
      gen_clk(1);
1217 
    end
1218 
 
1219 138 igorm 
    for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1)       // address
1220 80 mohor 
    begin
1221 
      tdi_pad_i<=#1 addr[i];
1222 114 mohor 
      calculate_crc(addr[i]);
1223 80 mohor 
      gen_clk(1);
1224 
    end
1225 87 mohor 
 
1226 138 igorm 
    for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1)       // length
1227 80 mohor 
    begin
1228 
      tdi_pad_i<=#1 length[i];
1229 114 mohor 
      calculate_crc(length[i]);
1230 80 mohor 
      gen_clk(1);
1231 
    end
1232 
 
1233 138 igorm 
    for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
1234 80 mohor 
    begin
1235 99 mohor 
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
1236 114 mohor 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
1237 99 mohor 
      else
1238 114 mohor 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
1239 99 mohor 
 
1240 80 mohor 
      gen_clk(1);
1241 
    end
1242 
 
1243 135 igorm 
    tdi_pad_i<=#1 1'hz;
1244 80 mohor 
 
1245 138 igorm 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1246 110 mohor 
 
1247 139 igorm 
    for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
1248 
      begin
1249 
        gen_clk(1);     // Generating clock to read out a status bit.
1250 
        status_wb[i] = tdo;
1251 
      end
1252 
 
1253 
    if (|status_wb)
1254 
      begin
1255 
        $write("(*E) (%0t) debug_wishbone_wr_comm error: ", $time);
1256 
        casex (status_wb)
1257 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1258 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
1259 
          4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
1260 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
1261 
        endcase
1262 
        $stop;
1263 
      end
1264 
 
1265 
 
1266 138 igorm 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
1267 80 mohor 
    begin
1268 
      gen_clk(1);
1269 
    end
1270 
 
1271 138 igorm 
    tms_pad_i<=#1 1'b1;
1272 80 mohor 
    gen_clk(1);         // to exit1_dr
1273 
 
1274 140 igorm 
    if (~crc_match_in)
1275 
      begin
1276 
        $display("(%0t) Incoming CRC failed !!!", $time);
1277 
        $stop;
1278 
      end
1279 
 
1280 138 igorm 
    tms_pad_i<=#1 1'b1;
1281 80 mohor 
    gen_clk(1);         // to update_dr
1282 138 igorm 
    tms_pad_i<=#1 1'b0;
1283 80 mohor 
    gen_clk(1);         // to run_test_idle
1284 
  end
1285 139 igorm 
endtask       // debug_wishbone_wr_comm
1286 80 mohor 
 
1287 
 
1288 
 
1289 
 
1290 
 
1291 139 igorm 
task debug_wishbone_rd_comm;
1292 
  output [`DBG_WB_ACC_TYPE_LEN -1:0]  acc_type;
1293 
  output [`DBG_WB_ADR_LEN -1:0]       addr;
1294 
  output [`DBG_WB_LEN_LEN -1:0]       length;
1295 
  integer                             i;
1296 
  reg   [`DBG_WB_CMD_LEN -1:0]        command;
1297 88 mohor 
 
1298 
  begin
1299 139 igorm 
    $display("(%0t) Task debug_wishbone_rd_comm: ", $time);
1300 80 mohor 
 
1301 139 igorm 
    command = `DBG_WB_RD_COMM;
1302 
    tms_pad_i<=#1 1'b1;
1303 88 mohor 
    gen_clk(1);
1304 139 igorm 
    tms_pad_i<=#1 1'b0;
1305 88 mohor 
    gen_clk(2);  // we are in shiftDR
1306 87 mohor 
 
1307 139 igorm 
    crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1308 99 mohor 
 
1309 138 igorm 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1310 114 mohor 
    calculate_crc(1'b0);
1311 88 mohor 
    gen_clk(1);
1312 87 mohor 
 
1313 139 igorm 
    for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
1314 88 mohor 
    begin
1315 
      tdi_pad_i<=#1 command[i]; // command
1316 114 mohor 
      calculate_crc(command[i]);
1317 88 mohor 
      gen_clk(1);
1318 
    end
1319 87 mohor 
 
1320 139 igorm 
    for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
1321 88 mohor 
    begin
1322 139 igorm 
      tdi_pad_i<=#1 crc_out[i];
1323 88 mohor 
      gen_clk(1);
1324 
    end
1325 
 
1326 92 mohor 
    tdi_pad_i<=#1 1'hz;
1327 110 mohor 
 
1328 139 igorm 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1329 110 mohor 
 
1330 139 igorm 
    for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
1331 
    begin
1332 
      gen_clk(1);
1333 
      acc_type[i] = tdo;
1334 
    end
1335 88 mohor 
 
1336 139 igorm 
    for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1)       // address
1337 88 mohor 
    begin
1338 
      gen_clk(1);
1339 139 igorm 
      addr[i] = tdo;
1340 88 mohor 
    end
1341 139 igorm 
 
1342 
    for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1)       // length
1343 
    begin
1344 
      gen_clk(1);
1345 
      length[i] = tdo;
1346 
    end
1347 88 mohor 
 
1348 139 igorm 
    for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
1349 
      begin
1350 
        gen_clk(1);     // Generating clock to read out a status bit.
1351 
        status_wb[i] = tdo;
1352 
      end
1353 88 mohor 
 
1354 139 igorm 
    if (|status_wb)
1355 110 mohor 
      begin
1356 139 igorm 
        $write("(*E) (%0t) debug_wishbone_rd_comm: ", $time);
1357 
        casex (status_wb)
1358 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1359 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
1360 
          4'bxx1x : $display("Unknown command !!!\n\n", $time);
1361 
          4'bxxx1 : $display("Unknown command !!!\n\n", $time);
1362 
        endcase
1363 110 mohor 
        $stop;
1364 
      end
1365 
 
1366 139 igorm 
 
1367 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
1368 
    begin
1369 
      gen_clk(1);
1370 
    end
1371 
 
1372 
    tms_pad_i<=#1 1'b1;
1373 
    gen_clk(1);         // to exit1_dr
1374 
 
1375 140 igorm 
    if (~crc_match_in)
1376 
      begin
1377 
        $display("(%0t) Incoming CRC failed !!!", $time);
1378 
        $stop;
1379 
      end
1380 
 
1381 139 igorm 
    tms_pad_i<=#1 1'b1;
1382 88 mohor 
    gen_clk(1);         // to update_dr
1383 139 igorm 
    tms_pad_i<=#1 1'b0;
1384 88 mohor 
    gen_clk(1);         // to run_test_idle
1385 
  end
1386 139 igorm 
endtask       // debug_wishbone_rd_comm
1387 88 mohor 
 
1388 
 
1389 
 
1390 
 
1391 139 igorm 
 
1392 88 mohor 
task debug_wishbone_go;
1393 110 mohor 
  input         wait_for_wb_ready;
1394 99 mohor 
  input         gen_crc_err;
1395 90 mohor 
  integer i;
1396 116 mohor 
  reg   [4:0]   bit_pointer;
1397 
  integer       word_pointer;
1398 
  reg  [31:0]   tmp_data;
1399 139 igorm 
  reg [`DBG_WB_CMD_LEN -1:0]        command;
1400 
 
1401 90 mohor 
 
1402 2 mohor 
  begin
1403 88 mohor 
    $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
1404 139 igorm 
    command = `DBG_WB_GO;
1405 116 mohor 
    word_pointer = 0;
1406 88 mohor 
 
1407 139 igorm 
    tms_pad_i<=#1 1'b1;
1408 80 mohor 
    gen_clk(1);
1409 139 igorm 
    tms_pad_i<=#1 1'b0;
1410 80 mohor 
    gen_clk(2);  // we are in shiftDR
1411 2 mohor 
 
1412 139 igorm 
    crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1413 99 mohor 
 
1414 138 igorm 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1415 114 mohor 
    calculate_crc(1'b0);
1416 80 mohor 
    gen_clk(1);
1417 88 mohor 
 
1418 139 igorm 
    for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
1419 88 mohor 
    begin
1420 
      tdi_pad_i<=#1 command[i]; // command
1421 114 mohor 
      calculate_crc(command[i]);
1422 88 mohor 
      gen_clk(1);
1423 
    end
1424 
 
1425 
 
1426 139 igorm 
    if ((last_wb_cmd == `DBG_WB_WRITE8) | (last_wb_cmd == `DBG_WB_WRITE16) | (last_wb_cmd == `DBG_WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
1427 88 mohor 
      begin
1428 145 igorm 
        for (i=0; i<((length_global) << 3); i=i+1)
1429 88 mohor 
          begin
1430 116 mohor 
            tmp_data = wb_data[word_pointer];
1431 
            if ((!(i%32)) && (i>0))
1432 88 mohor 
              begin
1433 116 mohor 
                word_pointer = word_pointer + 1;
1434 88 mohor 
              end
1435 116 mohor 
            bit_pointer = 31-i[4:0];
1436 
            tdi_pad_i<=#1 tmp_data[bit_pointer];
1437 
            calculate_crc(tmp_data[bit_pointer]);
1438 90 mohor 
            gen_clk(1);
1439 
 
1440 88 mohor 
          end
1441 
      end
1442 
 
1443 139 igorm 
    for(i=`DBG_WB_CRC_LEN -1; i>=1; i=i-1)
1444 88 mohor 
    begin
1445 114 mohor 
      tdi_pad_i<=#1 crc_out[i];
1446 88 mohor 
      gen_clk(1);
1447 
    end
1448 
 
1449 110 mohor 
    if (gen_crc_err)  // Generate crc error at last crc bit
1450 114 mohor 
      tdi_pad_i<=#1 ~crc_out[0];   // error crc
1451 110 mohor 
    else
1452 114 mohor 
      tdi_pad_i<=#1 crc_out[0];    // ok crc
1453 99 mohor 
 
1454 110 mohor 
    if (wait_for_wb_ready)
1455 
      begin
1456 139 igorm 
        tms_pad_i<=#1 1'b1;
1457 110 mohor 
        gen_clk(1);       // to exit1_dr. Last CRC is shifted on this clk
1458 139 igorm 
        tms_pad_i<=#1 1'b0;
1459 110 mohor 
        gen_clk(1);       // to pause_dr
1460 90 mohor 
 
1461 110 mohor 
        #2;             // wait a bit for tdo to activate
1462 
        while (tdo)     // waiting for wb to send "ready"
1463 
        begin
1464 
          gen_clk(1);       // staying in pause_dr
1465 
        end
1466 
 
1467 139 igorm 
        tms_pad_i<=#1 1'b1;
1468 110 mohor 
        gen_clk(1);       // to exit2_dr
1469 139 igorm 
        tms_pad_i<=#1 1'b0;
1470 110 mohor 
        gen_clk(1);       // to shift_dr
1471 
      end
1472 
    else
1473 
      begin
1474 
        gen_clk(1);       // Last CRC is shifted on this clk
1475 
      end
1476 90 mohor 
 
1477 
 
1478 110 mohor 
    tdi_pad_i<=#1 1'hz;
1479 139 igorm 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1480 110 mohor 
 
1481 139 igorm 
    if ((last_wb_cmd == `DBG_WB_READ8) | (last_wb_cmd == `DBG_WB_READ16) | (last_wb_cmd == `DBG_WB_READ32))  // When WB_READx was previously activated, data needs to be shifted.
1482 90 mohor 
      begin
1483 145 igorm 
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", length_global<<3, length_global);
1484 116 mohor 
        word_pointer = 0; // Reset pointer
1485 145 igorm 
        for (i=0; i<(length_global<<3); i=i+1)
1486 116 mohor 
          begin
1487 
            gen_clk(1);
1488 
            if (i[4:0] == 31)   // Latching data
1489 
              begin
1490 
                wb_data[word_pointer] = in_data_be;
1491 
                $display("\t\tin_data_be = 0x%x", in_data_be);
1492 
                word_pointer = word_pointer + 1;
1493 
              end
1494 
          end
1495 90 mohor 
      end
1496 
 
1497 
 
1498 139 igorm 
    for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
1499 
      begin
1500 
        gen_clk(1);     // Generating clock to read out a status bit.
1501 
        status_wb[i] = tdo;
1502 
      end
1503 88 mohor 
 
1504 139 igorm 
    if (|status_wb)
1505 
      begin
1506 
        $write("(*E) (%0t) debug_wishbone_go error: ", $time);
1507 
        casex (status_wb)
1508 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1509 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
1510 
          4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
1511 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
1512 
        endcase
1513 
        $stop;
1514 
      end
1515 
 
1516 
 
1517 138 igorm 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
1518 88 mohor 
    begin
1519 
      gen_clk(1);
1520 
    end
1521 
 
1522 139 igorm 
    tms_pad_i<=#1 1'b1;
1523 88 mohor 
    gen_clk(1);         // to exit1_dr
1524 
 
1525 110 mohor 
    if (~crc_match_in)
1526 
      begin
1527 
        $display("(%0t) Incoming CRC failed !!!", $time);
1528 
        $stop;
1529 
      end
1530 
 
1531 139 igorm 
    tms_pad_i<=#1 1'b1;
1532 88 mohor 
    gen_clk(1);         // to update_dr
1533 139 igorm 
    tms_pad_i<=#1 1'b0;
1534 88 mohor 
    gen_clk(1);         // to run_test_idle
1535 2 mohor 
  end
1536 88 mohor 
endtask       // debug_wishbone_go
1537 2 mohor 
 
1538 
 
1539 139 igorm 
`endif // DBG_WISHBONE_SUPPORTED
1540 88 mohor 
 
1541 
 
1542 139 igorm 
`ifdef DBG_CPU_SUPPORTED
1543 99 mohor 
task debug_cpu;
1544 139 igorm 
  input [`DBG_CPU_CMD_LEN -1:0]   command;
1545 
  input                           ready;
1546 
  input [`DBG_CPU_ADR_LEN -1:0]   addr;
1547 
  input [`DBG_CPU_LEN_LEN -1:0]   length;
1548 
  input                           gen_crc_err;
1549 
  input [99:0]                    text;
1550 99 mohor 
  integer i;
1551 
 
1552 
  begin
1553 
   $write("(%0t) Task debug_cpu: ", $time);
1554 88 mohor 
 
1555 99 mohor 
    test_text = text;
1556 
 
1557 
    case (command)
1558 139 igorm 
      `DBG_CPU_READ   :
1559 99 mohor 
        begin
1560 139 igorm 
          $display("cpu_read (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1561 
          debug_cpu_wr_comm(`DBG_CPU_READ, addr, length, gen_crc_err);
1562 
          last_cpu_cmd = `DBG_CPU_READ;  last_cpu_cmd_text = "DBG_CPU_READ";
1563 145 igorm 
          length_global = length + 1;
1564 139 igorm 
#10000;
1565 
          debug_cpu_go(ready, gen_crc_err);
1566 99 mohor 
        end
1567 139 igorm 
      `DBG_CPU_WRITE  :
1568 99 mohor 
        begin
1569 139 igorm 
          $display("cpu_write (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
1570 
          debug_cpu_wr_comm(`DBG_CPU_WRITE, addr, length, gen_crc_err);
1571 
          last_cpu_cmd = `DBG_CPU_WRITE;  last_cpu_cmd_text = "DBG_CPU_WRITE";
1572 
#10000;
1573 145 igorm 
          length_global = length + 1;
1574 139 igorm 
          debug_cpu_go(ready, gen_crc_err);
1575 99 mohor 
        end
1576 139 igorm 
      default:
1577 99 mohor 
        begin
1578 139 igorm 
          $display("(*E) debug_cpu : Unsupported instruction !!!");
1579 99 mohor 
          $stop;
1580 
        end
1581 
    endcase
1582 
  end
1583 
endtask       // debug_cpu
1584 
 
1585 
 
1586 
 
1587 139 igorm 
task debug_cpu_wr_comm;
1588 
  input [`DBG_CPU_ACC_TYPE_LEN -1:0]  acc_type;
1589 
  input [`DBG_CPU_ADR_LEN -1:0]       addr;
1590 
  input [`DBG_CPU_LEN_LEN -1:0]       length;
1591 
  input                               gen_crc_err;
1592 
  integer                             i;
1593 
  reg   [`DBG_CPU_CMD_LEN -1:0]       command;
1594 99 mohor 
 
1595 
  begin
1596 139 igorm 
    $display("(%0t) Task debug_cpu_wr_comm: ", $time);
1597 99 mohor 
 
1598 139 igorm 
    command = `DBG_CPU_WR_COMM;
1599 
    tms_pad_i<=#1 1'b1;
1600 99 mohor 
    gen_clk(1);
1601 139 igorm 
    tms_pad_i<=#1 1'b0;
1602 99 mohor 
    gen_clk(2);  // we are in shiftDR
1603 
 
1604 139 igorm 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1605 99 mohor 
 
1606 138 igorm 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1607 114 mohor 
    calculate_crc(1'b0);
1608 99 mohor 
    gen_clk(1);
1609 
 
1610 139 igorm 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
1611 99 mohor 
    begin
1612 
      tdi_pad_i<=#1 command[i]; // command
1613 114 mohor 
      calculate_crc(command[i]);
1614 99 mohor 
      gen_clk(1);
1615 
    end
1616 
 
1617 139 igorm 
    for(i=`DBG_CPU_ACC_TYPE_LEN -1; i>=0; i=i-1)
1618 99 mohor 
    begin
1619 139 igorm 
      tdi_pad_i<=#1 acc_type[i]; // command
1620 
      calculate_crc(acc_type[i]);
1621 
      gen_clk(1);
1622 
    end
1623 
 
1624 
    for(i=`DBG_CPU_ADR_LEN -1; i>=0; i=i-1)       // address
1625 
    begin
1626 99 mohor 
      tdi_pad_i<=#1 addr[i];
1627 114 mohor 
      calculate_crc(addr[i]);
1628 99 mohor 
      gen_clk(1);
1629 
    end
1630 93 mohor 
 
1631 139 igorm 
    for(i=`DBG_CPU_LEN_LEN -1; i>=0; i=i-1)       // length
1632 99 mohor 
    begin
1633 139 igorm 
      tdi_pad_i<=#1 length[i];
1634 
      calculate_crc(length[i]);
1635 
      gen_clk(1);
1636 
    end
1637 
 
1638 
    for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
1639 
    begin
1640 
      if (gen_crc_err & (i==0))      // Generate crc error at last crc bit
1641 114 mohor 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
1642 99 mohor 
      else
1643 114 mohor 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
1644 99 mohor 
 
1645 
      gen_clk(1);
1646 
    end
1647 
 
1648 135 igorm 
    tdi_pad_i<=#1 1'hz;
1649 110 mohor 
 
1650 139 igorm 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1651 99 mohor 
 
1652 139 igorm 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
1653 
      begin
1654 
        gen_clk(1);     // Generating clock to read out a status bit.
1655 
        status_cpu[i] = tdo;
1656 
      end
1657 
 
1658 
    if (|status_cpu)
1659 
      begin
1660 
        $write("(*E) (%0t) debug_cpu_wr_comm error: ", $time);
1661 
        casex (status_cpu)
1662 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1663 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
1664 
          4'bxx1x : $display("??? error !!!\n\n", $time);
1665 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
1666 
        endcase
1667 
        $stop;
1668 
      end
1669 
 
1670 
 
1671 138 igorm 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
1672 99 mohor 
    begin
1673 
      gen_clk(1);
1674 
    end
1675 
 
1676 139 igorm 
    tms_pad_i<=#1 1'b1;
1677 99 mohor 
    gen_clk(1);         // to exit1_dr
1678 
 
1679 140 igorm 
    if (~crc_match_in)
1680 
      begin
1681 
        $display("(%0t) Incoming CRC failed !!!", $time);
1682 
        $stop;
1683 
      end
1684 
 
1685 139 igorm 
    tms_pad_i<=#1 1'b1;
1686 
    gen_clk(1);         // to update_dr
1687 
    tms_pad_i<=#1 1'b0;
1688 
    gen_clk(1);         // to run_test_idle
1689 
  end
1690 
endtask       // debug_cpu_wr_comm
1691 
 
1692 
 
1693 
 
1694 
task debug_cpu_wr_ctrl;
1695 142 igorm 
  input [`DBG_CPU_CTRL_LEN -1:0]  data;
1696 
  input [99:0]                    text;
1697 
  integer                         i;
1698 
  reg   [`DBG_CPU_CMD_LEN -1:0]   command;
1699 139 igorm 
 
1700 
  begin
1701 
    test_text = text;
1702 
 
1703 
    $display("(%0t) Task debug_cpu_wr_ctrl (data=0x%0x (%0s))", $time, data, text);
1704 
 
1705 
    command = `DBG_CPU_WR_CTRL;
1706 
    tms_pad_i<=#1 1'b1;
1707 
    gen_clk(1);
1708 
    tms_pad_i<=#1 1'b0;
1709 
    gen_clk(2);  // we are in shiftDR
1710 
 
1711 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1712 
 
1713 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1714 
    calculate_crc(1'b0);
1715 
    gen_clk(1);
1716 
 
1717 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
1718 
    begin
1719 
      tdi_pad_i<=#1 command[i]; // command
1720 
      calculate_crc(command[i]);
1721 
      gen_clk(1);
1722 
    end
1723 
 
1724 
    for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)
1725 
    begin
1726 
      tdi_pad_i<=#1 data[i];                                    // data (used cotrol bits
1727 
      calculate_crc(data[i]);
1728 
      gen_clk(1);
1729 
    end
1730 
 
1731 
    for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)  // unused control bits
1732 
    begin
1733 
      tdi_pad_i<=#1 1'b0;
1734 
      calculate_crc(1'b0);
1735 
      gen_clk(1);
1736 
    end
1737 
 
1738 
    for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
1739 
    begin
1740 
      tdi_pad_i<=#1 crc_out[i];    // ok crc
1741 
      gen_clk(1);
1742 
    end
1743 
 
1744 
    tdi_pad_i<=#1 1'hz;
1745 
 
1746 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1747 
 
1748 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
1749 110 mohor 
      begin
1750 139 igorm 
        gen_clk(1);     // Generating clock to read out a status bit.
1751 
        status_cpu[i] = tdo;
1752 
      end
1753 
 
1754 
    if (|status_cpu)
1755 
      begin
1756 
        $write("(*E) (%0t) debug_cpu_wr_ctrl error: ", $time);
1757 
        casex (status_cpu)
1758 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1759 
          4'bx1xx : $display("??? error !!!\n\n", $time);
1760 
          4'bxx1x : $display("??? error !!!\n\n", $time);
1761 
          4'bxxx1 : $display("??? error !!!\n\n", $time);
1762 
        endcase
1763 110 mohor 
        $stop;
1764 
      end
1765 
 
1766 139 igorm 
 
1767 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
1768 
    begin
1769 
      gen_clk(1);
1770 
    end
1771 
 
1772 
    tms_pad_i<=#1 1'b1;
1773 
    gen_clk(1);         // to exit1_dr
1774 
 
1775 140 igorm 
    if (~crc_match_in)
1776 
      begin
1777 
        $display("(%0t) Incoming CRC failed !!!", $time);
1778 
        $stop;
1779 
      end
1780 
 
1781 139 igorm 
    tms_pad_i<=#1 1'b1;
1782 99 mohor 
    gen_clk(1);         // to update_dr
1783 139 igorm 
    tms_pad_i<=#1 1'b0;
1784 99 mohor 
    gen_clk(1);         // to run_test_idle
1785 
  end
1786 139 igorm 
endtask       // debug_cpu_wr_ctrl
1787 99 mohor 
 
1788 
 
1789 
 
1790 139 igorm 
task debug_cpu_rd_ctrl;
1791 
  output [`DBG_CPU_CTRL_LEN -1:0] data;
1792 
  input  [99:0] text;
1793 
  integer                         i;
1794 
  reg   [`DBG_CPU_CMD_LEN -1:0]   command;
1795 
 
1796 
  begin
1797 
    test_text = text;
1798 
    $display("(%0t) Task debug_cpu_rd_ctrl: ", $time);
1799 99 mohor 
 
1800 139 igorm 
    command = `DBG_CPU_RD_CTRL;
1801 
    tms_pad_i<=#1 1'b1;
1802 
    gen_clk(1);
1803 
    tms_pad_i<=#1 1'b0;
1804 
    gen_clk(2);  // we are in shiftDR
1805 
 
1806 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1807 
 
1808 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1809 
    calculate_crc(1'b0);
1810 
    gen_clk(1);
1811 
 
1812 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
1813 
    begin
1814 
      tdi_pad_i<=#1 command[i]; // command
1815 
      calculate_crc(command[i]);
1816 
      gen_clk(1);
1817 
    end
1818 
 
1819 
    for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
1820 
    begin
1821 
      tdi_pad_i<=#1 crc_out[i];
1822 
      gen_clk(1);
1823 
    end
1824 
 
1825 
    tdi_pad_i<=#1 1'hz;
1826 
 
1827 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1828 
 
1829 
    for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)     // data (used control bits)
1830 
    begin
1831 
      gen_clk(1);
1832 
      data[i] = tdo;
1833 
    end
1834 
 
1835 
    for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)       // unused control bits
1836 
    begin
1837 
      gen_clk(1);
1838 
    end
1839 
 
1840 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
1841 
      begin
1842 
        gen_clk(1);     // Generating clock to read out a status bit.
1843 
        status_cpu[i] = tdo;
1844 
      end
1845 
 
1846 
    if (|status_cpu)
1847 
      begin
1848 
        $write("(*E) (%0t) debug_cpu_rd_ctrl: ", $time);
1849 
        casex (status_cpu)
1850 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1851 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
1852 
          4'bxx1x : $display("Unknown command !!!\n\n", $time);
1853 
          4'bxxx1 : $display("Unknown command !!!\n\n", $time);
1854 
        endcase
1855 
        $stop;
1856 
      end
1857 
 
1858 
 
1859 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
1860 
    begin
1861 
      gen_clk(1);
1862 
    end
1863 
 
1864 
    tms_pad_i<=#1 1'b1;
1865 
    gen_clk(1);         // to exit1_dr
1866 
 
1867 140 igorm 
    if (~crc_match_in)
1868 
      begin
1869 
        $display("(%0t) Incoming CRC failed !!!", $time);
1870 
        $stop;
1871 
      end
1872 
 
1873 139 igorm 
    tms_pad_i<=#1 1'b1;
1874 
    gen_clk(1);         // to update_dr
1875 
    tms_pad_i<=#1 1'b0;
1876 
    gen_clk(1);         // to run_test_idle
1877 
  end
1878 
endtask       // debug_cpu_rd_ctrl
1879 
 
1880 
 
1881 
 
1882 99 mohor 
task debug_cpu_go;
1883 139 igorm 
  input         wait_for_cpu_ready;
1884 99 mohor 
  input         gen_crc_err;
1885 139 igorm 
  integer i;
1886 
  reg   [4:0]   bit_pointer;
1887 
  integer       word_pointer;
1888 
  reg  [31:0]   tmp_data;
1889 
  reg [`DBG_CPU_CMD_LEN -1:0]       command;
1890 99 mohor 
 
1891 
 
1892 93 mohor 
  begin
1893 139 igorm 
    $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_cpu_cmd_text);
1894 
    command = `DBG_CPU_GO;
1895 
    word_pointer = 0;
1896 88 mohor 
 
1897 139 igorm 
    tms_pad_i<=#1 1'b1;
1898 93 mohor 
    gen_clk(1);
1899 139 igorm 
    tms_pad_i<=#1 1'b0;
1900 93 mohor 
    gen_clk(2);  // we are in shiftDR
1901 88 mohor 
 
1902 139 igorm 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
1903 
 
1904 138 igorm 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
1905 114 mohor 
    calculate_crc(1'b0);
1906 93 mohor 
    gen_clk(1);
1907 88 mohor 
 
1908 139 igorm 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
1909 93 mohor 
    begin
1910 
      tdi_pad_i<=#1 command[i]; // command
1911 114 mohor 
      calculate_crc(command[i]);
1912 93 mohor 
      gen_clk(1);
1913 
    end
1914 88 mohor 
 
1915 
 
1916 139 igorm 
    if (last_cpu_cmd == `DBG_CPU_WRITE)  // When DBG_CPU_WRITE was previously activated, data needs to be shifted.
1917 93 mohor 
      begin
1918 145 igorm 
        for (i=0; i<((length_global) << 3); i=i+1)
1919 93 mohor 
          begin
1920 139 igorm 
            tmp_data = wb_data[word_pointer];
1921 
            if ((!(i%32)) && (i>0))
1922 
              begin
1923 
                word_pointer = word_pointer + 1;
1924 
              end
1925 
            bit_pointer = 31-i[4:0];
1926 
            tdi_pad_i<=#1 tmp_data[bit_pointer];
1927 
            calculate_crc(tmp_data[bit_pointer]);
1928 93 mohor 
            gen_clk(1);
1929 139 igorm 
 
1930 93 mohor 
          end
1931 
      end
1932 2 mohor 
 
1933 139 igorm 
    for(i=`DBG_CPU_CRC_LEN -1; i>=1; i=i-1)
1934 93 mohor 
    begin
1935 139 igorm 
      tdi_pad_i<=#1 crc_out[i];
1936 93 mohor 
      gen_clk(1);
1937 
    end
1938 
 
1939 139 igorm 
    if (gen_crc_err)  // Generate crc error at last crc bit
1940 
      tdi_pad_i<=#1 ~crc_out[0];   // error crc
1941 
    else
1942 
      tdi_pad_i<=#1 crc_out[0];    // ok crc
1943 93 mohor 
 
1944 139 igorm 
    if (wait_for_cpu_ready)
1945 
      begin
1946 
        tms_pad_i<=#1 1'b1;
1947 
        gen_clk(1);       // to exit1_dr. Last CRC is shifted on this clk
1948 
        tms_pad_i<=#1 1'b0;
1949 
        gen_clk(1);       // to pause_dr
1950 93 mohor 
 
1951 139 igorm 
        #2;             // wait a bit for tdo to activate
1952 
        while (tdo)     // waiting for wb to send "ready"
1953 
        begin
1954 
          gen_clk(1);       // staying in pause_dr
1955 
        end
1956 
 
1957 
        tms_pad_i<=#1 1'b1;
1958 
        gen_clk(1);       // to exit2_dr
1959 
        tms_pad_i<=#1 1'b0;
1960 
        gen_clk(1);       // to shift_dr
1961 
      end
1962 99 mohor 
    else
1963 139 igorm 
      begin
1964 
        gen_clk(1);       // Last CRC is shifted on this clk
1965 
      end
1966 93 mohor 
 
1967 139 igorm 
 
1968 
    tdi_pad_i<=#1 1'hz;
1969 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
1970 
 
1971 
    if (last_cpu_cmd == `DBG_CPU_READ)  // When DBG_CPU_READ was previously activated, data needs to be shifted.
1972 93 mohor 
      begin
1973 145 igorm 
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", length_global<<3, length_global);
1974 139 igorm 
        word_pointer = 0; // Reset pointer
1975 145 igorm 
        for (i=0; i<(length_global<<3); i=i+1)
1976 139 igorm 
          begin
1977 
            gen_clk(1);
1978 
            if (i[4:0] == 31)   // Latching data
1979 
              begin
1980 
                wb_data[word_pointer] = in_data_be;
1981 
                $display("\t\tin_data_be = 0x%x", in_data_be);
1982 
                word_pointer = word_pointer + 1;
1983 
              end
1984 
          end
1985 93 mohor 
      end
1986 
 
1987 
 
1988 139 igorm 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
1989 
      begin
1990 
        gen_clk(1);     // Generating clock to read out a status bit.
1991 
        status_cpu[i] = tdo;
1992 
      end
1993 93 mohor 
 
1994 139 igorm 
    if (|status_cpu)
1995 
      begin
1996 
        $write("(*E) (%0t) debug_cpu_go error: ", $time);
1997 
        casex (status_cpu)
1998 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
1999 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
2000 
          4'bxx1x : $display("??? error !!!\n\n", $time);
2001 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
2002 
        endcase
2003 
        $stop;
2004 
      end
2005 
 
2006 
 
2007 138 igorm 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
2008 93 mohor 
    begin
2009 
      gen_clk(1);
2010 
    end
2011 
 
2012 139 igorm 
    tms_pad_i<=#1 1'b1;
2013 93 mohor 
    gen_clk(1);         // to exit1_dr
2014 
 
2015 110 mohor 
    if (~crc_match_in)
2016 
      begin
2017 
        $display("(%0t) Incoming CRC failed !!!", $time);
2018 
        $stop;
2019 
      end
2020 
 
2021 139 igorm 
    tms_pad_i<=#1 1'b1;
2022 93 mohor 
    gen_clk(1);         // to update_dr
2023 139 igorm 
    tms_pad_i<=#1 1'b0;
2024 93 mohor 
    gen_clk(1);         // to run_test_idle
2025 
  end
2026 99 mohor 
endtask       // debug_cpu_go
2027 139 igorm 
`endif  // DBG_CPU_SUPPORTED
2028 93 mohor 
 
2029 
 
2030 
 
2031 113 mohor 
always @ (posedge tck_pad_i)
2032 
begin
2033 
  in_data_be[31:1] <= #1 in_data_be[30:0];
2034 
  in_data_be[0]    <= #1 tdo;
2035 93 mohor 
 
2036 113 mohor 
  in_data_le[31]   <= #1 tdo;
2037 
  in_data_le[30:0] <= #1 in_data_le[31:1];
2038 
end
2039 93 mohor 
 
2040 
 
2041 
 
2042 114 mohor 
// Calculating outgoing CRC
2043 
task calculate_crc;
2044 
  input data;
2045 
 
2046 
  begin
2047 
    crc_out[0]  <= #1 data          ^ crc_out[31];
2048 
    crc_out[1]  <= #1 data          ^ crc_out[0]  ^ crc_out[31];
2049 
    crc_out[2]  <= #1 data          ^ crc_out[1]  ^ crc_out[31];
2050 
    crc_out[3]  <= #1 crc_out[2];
2051 
    crc_out[4]  <= #1 data          ^ crc_out[3]  ^ crc_out[31];
2052 
    crc_out[5]  <= #1 data          ^ crc_out[4]  ^ crc_out[31];
2053 
    crc_out[6]  <= #1 crc_out[5];
2054 
    crc_out[7]  <= #1 data          ^ crc_out[6]  ^ crc_out[31];
2055 
    crc_out[8]  <= #1 data          ^ crc_out[7]  ^ crc_out[31];
2056 
    crc_out[9]  <= #1 crc_out[8];
2057 
    crc_out[10] <= #1 data         ^ crc_out[9]  ^ crc_out[31];
2058 
    crc_out[11] <= #1 data         ^ crc_out[10] ^ crc_out[31];
2059 
    crc_out[12] <= #1 data         ^ crc_out[11] ^ crc_out[31];
2060 
    crc_out[13] <= #1 crc_out[12];
2061 
    crc_out[14] <= #1 crc_out[13];
2062 
    crc_out[15] <= #1 crc_out[14];
2063 
    crc_out[16] <= #1 data         ^ crc_out[15] ^ crc_out[31];
2064 
    crc_out[17] <= #1 crc_out[16];
2065 
    crc_out[18] <= #1 crc_out[17];
2066 
    crc_out[19] <= #1 crc_out[18];
2067 
    crc_out[20] <= #1 crc_out[19];
2068 
    crc_out[21] <= #1 crc_out[20];
2069 
    crc_out[22] <= #1 data         ^ crc_out[21] ^ crc_out[31];
2070 
    crc_out[23] <= #1 data         ^ crc_out[22] ^ crc_out[31];
2071 
    crc_out[24] <= #1 crc_out[23];
2072 
    crc_out[25] <= #1 crc_out[24];
2073 
    crc_out[26] <= #1 data         ^ crc_out[25] ^ crc_out[31];
2074 
    crc_out[27] <= #1 crc_out[26];
2075 
    crc_out[28] <= #1 crc_out[27];
2076 
    crc_out[29] <= #1 crc_out[28];
2077 
    crc_out[30] <= #1 crc_out[29];
2078 
    crc_out[31] <= #1 crc_out[30];
2079 
  end
2080 
endtask // calculate_crc
2081 93 mohor 
 
2082 
 
2083 114 mohor 
// Calculating and checking input CRC
2084 
always @(posedge tck_pad_i)
2085 
begin
2086 
  crc_in[0]  <= #1 tdo           ^ crc_in[31];
2087 
  crc_in[1]  <= #1 tdo           ^ crc_in[0]  ^ crc_in[31];
2088 
  crc_in[2]  <= #1 tdo           ^ crc_in[1]  ^ crc_in[31];
2089 
  crc_in[3]  <= #1 crc_in[2];
2090 
  crc_in[4]  <= #1 tdo           ^ crc_in[3]  ^ crc_in[31];
2091 
  crc_in[5]  <= #1 tdo           ^ crc_in[4]  ^ crc_in[31];
2092 
  crc_in[6]  <= #1 crc_in[5];
2093 
  crc_in[7]  <= #1 tdo           ^ crc_in[6]  ^ crc_in[31];
2094 
  crc_in[8]  <= #1 tdo           ^ crc_in[7]  ^ crc_in[31];
2095 
  crc_in[9]  <= #1 crc_in[8];
2096 
  crc_in[10] <= #1 tdo          ^ crc_in[9]  ^ crc_in[31];
2097 
  crc_in[11] <= #1 tdo          ^ crc_in[10] ^ crc_in[31];
2098 
  crc_in[12] <= #1 tdo          ^ crc_in[11] ^ crc_in[31];
2099 
  crc_in[13] <= #1 crc_in[12];
2100 
  crc_in[14] <= #1 crc_in[13];
2101 
  crc_in[15] <= #1 crc_in[14];
2102 
  crc_in[16] <= #1 tdo          ^ crc_in[15] ^ crc_in[31];
2103 
  crc_in[17] <= #1 crc_in[16];
2104 
  crc_in[18] <= #1 crc_in[17];
2105 
  crc_in[19] <= #1 crc_in[18];
2106 
  crc_in[20] <= #1 crc_in[19];
2107 
  crc_in[21] <= #1 crc_in[20];
2108 
  crc_in[22] <= #1 tdo          ^ crc_in[21] ^ crc_in[31];
2109 
  crc_in[23] <= #1 tdo          ^ crc_in[22] ^ crc_in[31];
2110 
  crc_in[24] <= #1 crc_in[23];
2111 
  crc_in[25] <= #1 crc_in[24];
2112 
  crc_in[26] <= #1 tdo          ^ crc_in[25] ^ crc_in[31];
2113 
  crc_in[27] <= #1 crc_in[26];
2114 
  crc_in[28] <= #1 crc_in[27];
2115 
  crc_in[29] <= #1 crc_in[28];
2116 
  crc_in[30] <= #1 crc_in[29];
2117 
  crc_in[31] <= #1 crc_in[30];
2118 
end
2119 93 mohor 
 
2120 114 mohor 
assign crc_match_in = crc_in == 32'h0;
2121 
 
2122 
 
2123 
 
2124 2 mohor 
/**********************************************************************************
2125 
*                                                                                 *
2126 
*   Printing the information to the screen                                        *
2127 
*                                                                                 *
2128 
**********************************************************************************/
2129 
 
2130 139 igorm 
`ifdef DBG_MORE_INFO
2131 80 mohor 
always @ (posedge tck_pad_i)
2132 2 mohor 
begin
2133 80 mohor 
  if(dbg_tb.i_tap_top.update_ir)
2134 
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
2135 
      `EXTEST         : $display("\tInstruction EXTEST entered");
2136 
      `SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
2137 
      `IDCODE         : $display("\tInstruction IDCODE entered");
2138 
      `MBIST          : $display("\tInstruction MBIST entered");
2139 
      `DEBUG          : $display("\tInstruction DEBUG entered");
2140 
      `BYPASS         : $display("\tInstruction BYPASS entered");
2141 
                default           :     $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
2142 2 mohor 
    endcase
2143 
end
2144 138 igorm 
`endif
2145 2 mohor 
 
2146 
 
2147 80 mohor 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
2148 
always @ (posedge tck_pad_i)
2149 2 mohor 
begin
2150 80 mohor 
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
2151 2 mohor 
    begin
2152 80 mohor 
      $display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
2153 
      $display("(%0t) Simulation stopped !!!", $time);
2154 
      $stop;
2155 2 mohor 
    end
2156 
end
2157 
 
2158 
 
2159 80 mohor 
 
2160 73 mohor 
 
2161 80 mohor 
endmodule // dbg_tb
2162 
 
2163 
 

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