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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_tb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.39  2004/03/15 16:17:07  igorm
// 'hz changed to 1'hz because Icarus complains.
//
// Revision 1.38  2004/01/30 10:24:02  mohor
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
// turned on.
//
// Revision 1.37  2004/01/25 14:10:25  mohor
// Display for VATS added.
//
// Revision 1.36  2004/01/22 13:58:51  mohor
// Port signals are all set to zero after reset.
//
// Revision 1.35  2004/01/22 11:07:28  mohor
// test stall_test added.
//
// Revision 1.34  2004/01/20 14:24:08  mohor
// Define name changed.
//
// Revision 1.33  2004/01/20 14:05:26  mohor
// Data latching changed when testing WB.
//
// Revision 1.32  2004/01/20 10:23:21  mohor
// More debug data added.
//
// Revision 1.31  2004/01/20 09:07:44  mohor
// CRC generation iand verification in bench changed.
//
// Revision 1.30  2004/01/20 08:03:35  mohor
// IDCODE test improved.
//
// Revision 1.29  2004/01/19 13:13:18  mohor
// Define tap_defines.v added to test bench.
//
// Revision 1.28  2004/01/19 12:38:10  mohor
// Waiting for "ready" improved.
//
// Revision 1.27  2004/01/17 18:01:31  mohor
// New version.
//
// Revision 1.26  2004/01/17 17:01:25  mohor
// Almost finished.
//
// Revision 1.25  2004/01/16 14:51:24  mohor
// cpu registers added.
//
// Revision 1.24  2004/01/15 10:47:13  mohor
// Working.
//
// Revision 1.23  2004/01/14 22:59:01  mohor
// Temp version.
//
// Revision 1.22  2004/01/13 11:28:30  mohor
// tmp version.
//
// Revision 1.21  2004/01/10 07:50:41  mohor
// temp version.
//
// Revision 1.20  2004/01/09 12:49:23  mohor
// tmp version.
//
// Revision 1.19  2004/01/08 17:53:12  mohor
// tmp version.
//
// Revision 1.18  2004/01/07 11:59:48  mohor
// temp4 version.
//
// Revision 1.17  2004/01/06 17:14:59  mohor
// temp3 version.
//
// Revision 1.16  2004/01/05 12:16:50  mohor
// tmp2 version.
//
// Revision 1.15  2003/12/23 14:26:01  mohor
// New version of the debug interface. Not finished, yet.
//
// Revision 1.14  2003/10/23 16:16:30  mohor
// CRC logic changed.
//
// Revision 1.13  2003/08/28 13:54:33  simons
// Three more chains added for cpu debug access.
//
// Revision 1.12  2002/05/07 14:44:52  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.11  2002/03/12 14:32:26  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.10  2002/03/08 15:27:08  mohor
// Structure changed. Hooks for jtag chain added.
//
// Revision 1.9  2001/10/19 11:39:20  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8  2001/10/17 10:39:17  mohor
// bs_chain_o added.
//
// Revision 1.7  2001/10/16 10:10:18  mohor
// Signal names changed to lowercase.
//
// Revision 1.6  2001/10/15 09:52:50  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5  2001/09/24 14:06:12  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4  2001/09/20 10:10:29  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:54:03  mohor
// Minor changes for simulation.
//
// Revision 1.2  2001/09/18 14:12:43  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:23:40  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:05  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:15  mohor
// Initial release
//
//
 
 
`include "timescale.v"
`include "tap_defines.v"
`include "dbg_defines.v"
`include "dbg_wb_defines.v"
`include "dbg_cpu_defines.v"
 
// Test bench
module dbg_tb;
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
reg   tms_pad_i;
reg   tck_pad_i;
reg   trst_pad_i;
reg   tdi_pad_i;
wire  tdo_pad_o;
wire  tdo_padoe_o;
 
wire  shift_dr_o;
wire  pause_dr_o;
wire  update_dr_o;
wire  capture_dr_o;
 
wire  extest_select_o;
wire  sample_preload_select_o;
wire  mbist_select_o;
wire  debug_select_o;
 
reg   rst_i;
 
`ifdef WISHBONE_SUPPORTED
// WISHBONE common signals
reg   wb_clk_i;
 
// WISHBONE master interface
wire [31:0] wb_adr_o;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
wire        wb_cyc_o;
wire        wb_stb_o;
wire  [3:0] wb_sel_o;
wire        wb_we_o;
wire        wb_ack_i;
wire        wb_cab_o;
wire        wb_err_i;
wire  [2:0] wb_cti_o;
wire  [1:0] wb_bte_o;
`endif
 
`ifdef CPU_SUPPORTED
// CPU signals
wire        cpu_clk_i;
wire [31:0] cpu_addr_o;
wire [31:0] cpu_data_i;
wire [31:0] cpu_data_o;
wire        cpu_bp_i;
wire        cpu_stall_o;
wire        cpu_stall_all_o;
wire        cpu_stb_o;
wire  [`CPU_NUM -1:0]  cpu_sel_o;
wire        cpu_we_o;
wire        cpu_ack_i;
wire        cpu_rst_o;
`endif
 
// Text used for easier debugging
reg [199:0] test_text;
reg   [2:0] last_wb_cmd;
reg [199:0] last_wb_cmd_text;
 
reg  [31:0] wb_data [0:4095];   // Data that is written to (read from) wishbone is stored here. 
 
 
 
wire  tdo_o;
 
wire  debug_tdi_i;
wire  bs_chain_tdi_i;
wire  mbist_tdi_i;
 
reg   test_enabled;
 
reg [31:0] result;
reg [31:0] in_data_le, in_data_be;
reg [31:0] id;
 
wire crc_match_in;
reg [31:0] crc_in;
reg [31:0] crc_out;
reg [`DBG_TOP_STATUS_LEN -1:0] status;
 
wire tdo;
 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
 
// Connecting TAP module
tap_top i_tap_top (
                    .tms_pad_i        (tms_pad_i),
                    .tck_pad_i        (tck_pad_i),
                    .trst_pad_i       (!trst_pad_i),
                    .tdi_pad_i        (tdi_pad_i),
                    .tdo_pad_o        (tdo_pad_o),
                    .tdo_padoe_o      (tdo_padoe_o),
 
                    // TAP states
                    .shift_dr_o       (shift_dr_o),
                    .pause_dr_o       (pause_dr_o),
                    .update_dr_o      (update_dr_o),
                    .capture_dr_o     (capture_dr_o),
 
                    // Select signals for boundary scan or mbist
                    .extest_select_o  (extest_select_o),
                    .sample_preload_select_o(sample_preload_select_o),
                    .mbist_select_o   (mbist_select_o),
                    .debug_select_o   (debug_select_o),
 
                    // TDO signal that is connected to TDI of sub-modules.
                    .tdo_o            (tdo_o),
 
                    // TDI signals from sub-modules
                    .debug_tdi_i      (debug_tdi_i),        // from debug module
                    .bs_chain_tdi_i   (bs_chain_tdi_i),  // from Boundary Scan Chain
                    .mbist_tdi_i      (mbist_tdi_i)         // from Mbist Chain
 
               );
 
 
// Connecting debug top module
dbg_top i_dbg_top  (
                    .tck_i            (tck_pad_i),
                    .tdi_i            (tdo_o),
                    .tdo_o            (debug_tdi_i),
                    .rst_i            (rst_i),
 
                    // TAP states
                    .shift_dr_i       (shift_dr_o),
                    .pause_dr_i       (pause_dr_o),
                    .update_dr_i      (update_dr_o),
 
                    // Instructions
                    .debug_select_i   (debug_select_o)
 
                    `ifdef WISHBONE_SUPPORTED
                    // WISHBONE common signals
                    ,
                    .wb_clk_i         (wb_clk_i),
 
                    // WISHBONE master interface
                    .wb_adr_o         (wb_adr_o),
                    .wb_dat_o         (wb_dat_o),
                    .wb_dat_i         (wb_dat_i),
                    .wb_cyc_o         (wb_cyc_o),
                    .wb_stb_o         (wb_stb_o),
                    .wb_sel_o         (wb_sel_o),
                    .wb_we_o          (wb_we_o),
                    .wb_ack_i         (wb_ack_i),
                    .wb_cab_o         (wb_cab_o),
                    .wb_err_i         (wb_err_i),
                    .wb_cti_o         (wb_cti_o),
                    .wb_bte_o         (wb_bte_o)
                    `endif
 
                    `ifdef CPU_SUPPORTED
                    // CPU signals
                    ,
                    .cpu_clk_i        (cpu_clk_i),
                    .cpu_addr_o       (cpu_addr_o),
                    .cpu_data_i       (cpu_data_i),
                    .cpu_data_o       (cpu_data_o),
                    .cpu_bp_i         (cpu_bp_i),
                    .cpu_stall_o      (cpu_stall_o),
                    .cpu_stall_all_o  (cpu_stall_all_o),
                    .cpu_stb_o        (cpu_stb_o),
                    .cpu_sel_o        (cpu_sel_o),
                    .cpu_we_o         (cpu_we_o),
                    .cpu_ack_i        (cpu_ack_i),
                    .cpu_rst_o        (cpu_rst_o)
                    `endif
 
 
 
                   );
 
 
`ifdef WISHBONE_SUPPORTED
wb_slave_behavioral wb_slave
                   (
                    .CLK_I            (wb_clk_i),
                    .RST_I            (rst_i),
                    .ACK_O            (wb_ack_i),
                    .ADR_I            (wb_adr_o),
                    .CYC_I            (wb_cyc_o),
                    .DAT_O            (wb_dat_i),
                    .DAT_I            (wb_dat_o),
                    .ERR_O            (wb_err_i),
                    .RTY_O            (),      // NOT USED for now!
                    .SEL_I            (wb_sel_o),
                    .STB_I            (wb_stb_o),
                    .WE_I             (wb_we_o),
                    .CAB_I            (1'b0)
                   );
`endif
 
 
`ifdef CPU_SUPPORTED
cpu_behavioral i_cpu_behavioral
                   (
                    // CPU signals
                    .cpu_rst_i        (rst_i),
                    .cpu_clk_o        (cpu_clk_i),
                    .cpu_addr_i       (cpu_addr_o),
                    .cpu_data_o       (cpu_data_i),
                    .cpu_data_i       (cpu_data_o),
                    .cpu_bp_o         (cpu_bp_i),
                    .cpu_stall_i      (cpu_stall_o),
                    .cpu_stall_all_i  (cpu_stall_all_o),
                    .cpu_stb_i        (cpu_stb_o),
                    .cpu_sel_i        (cpu_sel_o),
                    .cpu_we_i         (cpu_we_o),
                    .cpu_ack_o        (cpu_ack_i),
                    .cpu_rst_o        (cpu_rst_o)
                   );
`endif
 
 
 
// Initial values
initial
begin
  trst_pad_i = 1'b1;
  tms_pad_i = 1'hz;
  tck_pad_i = 1'hz;
  tdi_pad_i = 1'hz;
 
  #100;
  trst_pad_i = 1'b0;
  #100;
  trst_pad_i = 1'b1;
end
 
initial
begin
  test_enabled = 1'b0;
  rst_i = 1'b0;
  #1000;
  rst_i = 1'b1;
  #1000;
  rst_i = 1'b0;
 
  // Initial values for wishbone slave model
  `ifdef WISHBONE_SUPPORTED
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  `endif
  #1 test_enabled<=#1 1'b1;
end
 
`ifdef WISHBONE_SUPPORTED
initial
begin
  wb_clk_i = 1'b0;
  forever #5 wb_clk_i = ~wb_clk_i;
end
`endif
 
always @ (posedge test_enabled)
begin
  $display("//////////////////////////////////////////////////////////////////");
  $display("//                                                              //");
  $display("//  (%0t) dbg_tb starting                                     //", $time);
  $display("//                                                              //");
  $display("//////////////////////////////////////////////////////////////////");
 
  $display("TEST: DBG_TEST");
 
 
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
 
  reset_tap;
 
  #500;
  goto_run_test_idle;
 
  `ifdef CPU_SUPPORTED
  // Test stall signal
  stall_test;
  `endif
 
  // Testing read and write to internal registers
  #10000;
 
  id_test;
 
  set_instruction(`DEBUG);
  #10000;
 
 
 
 
 
 
 
 
 
 
 
  #100000;
  `ifdef WISHBONE_SUPPORTED
  module_select(`WISHBONE_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
  #10000;
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  #100000;
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
//  debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
//
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
//  debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
//
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
//
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 3"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2);   // (`ERR_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 4"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
  debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, "read32 5"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
//  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
//  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
//  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}  
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
  `endif  // WISHBONE_SUPPORTED
 
  `ifdef CPU_SUPPORTED
  #10000;
  module_select(`CPU_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
 
 
 
  // Select cpu0
  #10000;
  debug_cpu(`CPU_WRITE_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "select cpu 0"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  // Read register
  #10000;
  debug_cpu(`CPU_READ_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "cpu_read_reg"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  // Stall cpu0
  #10000;
  debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "stall cpu0"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  // write to cpu 32-bit
  #10000;
  debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  // read from cpu 32-bit
  #10000;
  debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  // write to cpu 8-bit
  #10000;
  debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  // read from cpu 8-bit
  #10000;
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
 
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
  `endif
 
 
 
 
 
 
 
 
 
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
  $display("STATUS: passed");
  $display("\n\nSimulation end.");
  #1000 $stop;
 
end
 
 
`ifdef CPU_SUPPORTED
task stall_test;
  integer i;
 
  begin
    test_text = "stall_test";
    $display("\n\n(%0t) stall_test started", $time);
 
    // Set bp_i active for 1 clock cycle and check is stall is set or not
    check_stall(0); // Should not be set at the beginning
    @ (posedge cpu_clk_i);
    #1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b1;
    #1 check_stall(1); // set?
    @ (posedge cpu_clk_i);
    #1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b0;
    #1 check_stall(1); // set?
 
    gen_clk(1);
    #1 check_stall(1); // set?
 
    // Unstall with register
    set_instruction(`DEBUG);
    module_select(`CPU_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
    #1 check_stall(1); // set?
    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
    #1 check_stall(1); // set?
    debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
    #1 check_stall(0); // reset?
 
    // Set stall with register
    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
    #1 check_stall(0); // reset?
    debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
    #1 check_stall(1); // set?
 
    // Unstall with register
    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
    #1 check_stall(1); // set?
    debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
    #1 check_stall(0); // reset?
 
    $display("\n\n(%0t) stall_test passed\n\n", $time);
  end
endtask   // stall_test
 
 
task check_stall;
  input should_be_set;
  begin
    if (should_be_set && (!cpu_stall_o))
      begin
        $display ("\t\t(%0t) ERROR: cpu_stall_o is not set but should be.", $time);
        $stop;
      end
    if ((!should_be_set) && cpu_stall_o)
      begin
        $display ("\t\t(%0t) ERROR: cpu_stall_o set but shouldn't be.", $time);
        $stop;
      end
  end
endtask   // check_stall
`endif
 
 
task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin
    for (i=0; i<length; i=i+4)  // This data will be return from wb slave
      begin
        addr = start_addr + i;
        `ifdef WISHBONE_SUPPORTED
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
        `endif
      end
    for (i=0; i<4096; i=i+1)  // This data will be written to wb slave
      begin
        wb_data[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
      end
  end
endtask
 
 
task id_test;
  begin
    test_text = "id_test";
    $display("\n\n(%0t) TEST: id_test", $time);
 
    set_instruction(`IDCODE);
    read_id_code(id);
 
    `ifdef MORE_DBG_INFO
      $display("\tRead ID     = 0x%0x", id);
      $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
    `endif
 
    if (id==`IDCODE_VALUE)
      $display("(%0t) STATUS: passed\n", $time);
    else
      $display("(%0t) STATUS: failed (Read ID = 0x%0x, Expected ID = 0x%0x\n", $time, id, `IDCODE_VALUE);
  end
endtask // id_test
 
 
// Generation of the TCLK signal
task gen_clk;
  input [7:0] num;
  integer i;
  begin
    for(i=0; i<num; i=i+1)
      begin
        #TCLK tck_pad_i<=1;
        #TCLK tck_pad_i<=0;
      end
  end
endtask
 
 
// TAP reset
task reset_tap;
  begin
    $display("(%0t) Task reset_tap", $time);
    tms_pad_i<=#1 1'b1;
    gen_clk(5);
  end
endtask
 
 
// Goes to RunTestIdle state
task goto_run_test_idle;
  begin
    $display("(%0t) Task goto_run_test_idle", $time);
    tms_pad_i<=#1 1'b0;
    gen_clk(1);
  end
endtask
 
 
 
// sets the instruction to the IR register and goes to the RunTestIdle state
task set_instruction;
  input [3:0] instr;
  integer i;
 
  begin
    case (instr)
      `ifdef MORE_DBG_INFO
        `EXTEST          : $display("(%0t) Task set_instruction (EXTEST)", $time);
        `SAMPLE_PRELOAD  : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
        `IDCODE          : $display("(%0t) Task set_instruction (IDCODE)", $time);
        `DEBUG           : $display("(%0t) Task set_instruction (DEBUG)", $time);
        `MBIST           : $display("(%0t) Task set_instruction (MBIST)", $time);
        `BYPASS          : $display("(%0t) Task set_instruction (BYPASS)", $time);
      `else
        `EXTEST          : ;
        `SAMPLE_PRELOAD  : ;
        `IDCODE          : ;
        `DEBUG           : ;
        `MBIST           : ;
        `BYPASS          : ;
      `endif
        default
                         begin
                           $display("(*E) (%0t) Task set_instruction: Unsupported instruction !!!", $time);
                           $stop;
                         end
    endcase
 
    tms_pad_i<=#1 1;
    gen_clk(2);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftIR
 
    for(i=0; i<`IR_LENGTH-1; i=i+1)
    begin
      tdi_pad_i<=#1 instr[i];
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 instr[i]; // last shift
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
    tdi_pad_i<=#1 1'hz;    // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// Reads the ID code
task read_id_code;
  output [31:0] code;
  reg    [31:0] code;
  begin
    `ifdef MORE_DBG_INFO
      $display("(%0t) Task read_id_code", $time);
    `endif
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    tdi_pad_i<=#1 0;
    gen_clk(31);
 
    tms_pad_i<=#1 1;        // going out of shiftIR
    gen_clk(1);
 
    code = in_data_le;
 
    tdi_pad_i<=#1 1'hz; // tri-state
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(1);       // we are in RunTestIdle
  end
endtask
 
 
// sets the selected module and goes to the RunTestIdle state
task module_select;
  input [`MODULE_ID_LENGTH -1:0]  data;
  input                           gen_crc_err;
  integer                         i;
 
  begin
    case (data)
      `CPU_DEBUG_MODULE      : $display("(%0t) Task module_select (CPU_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
      `WISHBONE_DEBUG_MODULE : $display("(%0t) Task module_select (WISHBONE_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
      default                : $display("(%0t) Task module_select (ERROR!!! Unknown module selected)", $time);
    endcase
 
    tms_pad_i<=#1 1'b1;
    gen_clk(1);
    tms_pad_i<=#1 1'b0;
    gen_clk(2);  // we are in shiftDR
 
    status = {`DBG_TOP_STATUS_LEN{1'b0}};    // Initialize status to all 0's
    crc_out = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
    tdi_pad_i<=#1 1'b1; // module_select bit
    calculate_crc(1'b1);
    gen_clk(1);
 
    for(i=`MODULE_ID_LENGTH -1; i>=0; i=i-1) // Shifting module ID
    begin
      tdi_pad_i<=#1 data[i];
      calculate_crc(data[i]);
      gen_clk(1);
    end
 
    for(i=`DBG_TOP_CRC_LEN -1; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
      else
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;  // tri-state
 
    crc_in = {`DBG_TOP_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
    for(i=`DBG_TOP_STATUS_LEN -1; i>=0; i=i-1)
      begin
        gen_clk(1);     // Generating 1 clock to read out a status bit.
        status[i] = tdo;
      end
 
    for(i=0; i<`DBG_TOP_CRC_LEN -1; i=i+1)
      gen_clk(1);
 
    tms_pad_i<=#1 1'b1;
    gen_clk(1);         // to exit1_dr
 
    tms_pad_i<=#1 1'b1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 1'b0;
    gen_clk(1);         // to run_test_idle
 
    if (|status)
      begin
        $write("(*E) (%0t) Chain select error: ", $time);
        casex (status)
          4'b1xxx : $display("CRC error !!!\n\n", $time);
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
          4'bxx1x : $display("Non-existing module selected !!!\n\n", $time);
          4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
        endcase
        $stop;
      end
  end
endtask   // module_select
 
 
 
 
`ifdef WISHBONE_SUPPORTED
task debug_wishbone;
  input [`DBG_WB_CMD_LEN -1:0]   command;
  input         ready;
  input [`DBG_WB_ADR_LEN -1:0]  addr;
  input [`DBG_WB_LEN_LEN -1:0]  length;
  input         gen_crc_err;
  input [99:0]  text;
  integer i;
 
  begin
   $write("(%0t) Task debug_wishbone: ", $time);
 
    test_text = text;
 
    case (command)
      `WB_READ8    :
        begin
          $display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
          last_wb_cmd = `WB_READ8;  last_wb_cmd_text = "WB_READ8";
        end
      `WB_READ16   :
        begin
          $display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
          last_wb_cmd = `WB_READ16;  last_wb_cmd_text = "WB_READ16";
        end
      `WB_READ32   :
        begin
          $display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
          last_wb_cmd = `WB_READ32;  last_wb_cmd_text = "WB_READ32";
        end
      `WB_WRITE8   :
        begin
          $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
          last_wb_cmd = `WB_WRITE8;  last_wb_cmd_text = "WB_WRITE8";
        end
      `WB_WRITE16  :
        begin
          $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
          last_wb_cmd = `WB_WRITE16;  last_wb_cmd_text = "WB_WRITE16";
        end
      `WB_WRITE32  :
        begin
          $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
          last_wb_cmd = `WB_WRITE32;  last_wb_cmd_text = "WB_WRITE32";
        end
      `WB_GO       :
        begin
          $display("wb_go, ready=%0d, gen_crc_err=%0d (%0s))", ready, gen_crc_err, text);
          debug_wishbone_go(command, ready, gen_crc_err);
//          $display("wb_go_tmp, gen_crc_err=0x%0x (%0s))", gen_crc_err, text);
//          debug_wishbone_go_tmp(command, crc);
          last_wb_cmd = `WB_GO;  last_wb_cmd_text = "WB_GO";
        end
    endcase
  end
endtask       // debug_wishbone
 
 
 
 
 
 
task debug_wishbone_set_addr;
  input [`DBG_WB_CMD_LEN -1:0]  command;
  input [`DBG_WB_ADR_LEN -1:0]  addr;
  input [`DBG_WB_LEN_LEN -1:0]  length;
  input                         gen_crc_err;
  integer i;
 
  begin
    $display("(%0t) Task debug_wishbone_set_addr: ", $time);
 
    tms_pad_i<=#1 1'b1;
    gen_clk(1);
    tms_pad_i<=#1 1'b0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
    calculate_crc(1'b0);
    gen_clk(1);
 
    for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      calculate_crc(command[i]);
      gen_clk(1);
    end
 
    for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      calculate_crc(addr[i]);
      gen_clk(1);
    end
 
    for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1)       // length
    begin
      tdi_pad_i<=#1 length[i];
      calculate_crc(length[i]);
      gen_clk(1);
    end
 
    for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
      else
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
    gen_clk(`DBG_WB_STATUS_LEN);       // Generating 4 clocks to read out status.
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1'b1;
    gen_clk(1);         // to exit1_dr
 
    if (~crc_match_in)
      begin
        $display("(%0t) Incoming CRC failed !!!", $time);
        $stop;
      end
 
    tms_pad_i<=#1 1'b1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 1'b0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_set_addr
 
 
 
 
 
task debug_wishbone_status;
  input [2:0]   command;
  input         gen_crc_err;
  integer i;
 
  begin
    $display("(%0t) Task debug_wishbone_status: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
    calculate_crc(1'b0);
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      calculate_crc(command[i]);
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
      else
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    gen_clk(`DBG_WB_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    if (~crc_match_in)
      begin
        $display("(%0t) Incoming CRC failed !!!", $time);
        $stop;
      end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_status
 
 
 
 
task debug_wishbone_go;
  input [2:0]   command;
  input         wait_for_wb_ready;
  input         gen_crc_err;
  integer i;
  reg   [4:0]   bit_pointer;
  integer       word_pointer;
  reg  [31:0]   tmp_data;
 
  begin
    $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
    word_pointer = 0;
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
    calculate_crc(1'b0);
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      calculate_crc(command[i]);
      gen_clk(1);
    end
 
 
    if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
          begin
            tmp_data = wb_data[word_pointer];
            if ((!(i%32)) && (i>0))
              begin
                word_pointer = word_pointer + 1;
              end
            bit_pointer = 31-i[4:0];
            tdi_pad_i<=#1 tmp_data[bit_pointer];
            calculate_crc(tmp_data[bit_pointer]);
            gen_clk(1);
 
          end
      end
 
    for(i=31; i>=1; i=i-1)
    begin
      tdi_pad_i<=#1 crc_out[i];
      gen_clk(1);
    end
 
    if (gen_crc_err)  // Generate crc error at last crc bit
      tdi_pad_i<=#1 ~crc_out[0];   // error crc
    else
      tdi_pad_i<=#1 crc_out[0];    // ok crc
 
    if (wait_for_wb_ready)
      begin
        tms_pad_i<=#1 1;
        gen_clk(1);       // to exit1_dr. Last CRC is shifted on this clk
        tms_pad_i<=#1 0;
        gen_clk(1);       // to pause_dr
 
        #2;             // wait a bit for tdo to activate
        while (tdo)     // waiting for wb to send "ready"
        begin
          gen_clk(1);       // staying in pause_dr
        end
 
        tms_pad_i<=#1 1;
        gen_clk(1);       // to exit2_dr
        tms_pad_i<=#1 0;
        gen_clk(1);       // to shift_dr
      end
    else
      begin
        gen_clk(1);       // Last CRC is shifted on this clk
      end
 
 
    tdi_pad_i<=#1 1'hz;
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_READx was previously activated, data needs to be shifted.
      begin
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
        word_pointer = 0; // Reset pointer
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
          begin
            gen_clk(1);
            if (i[4:0] == 31)   // Latching data
              begin
                wb_data[word_pointer] = in_data_be;
                $display("\t\tin_data_be = 0x%x", in_data_be);
                word_pointer = word_pointer + 1;
              end
          end
      end
 
 
    gen_clk(`DBG_WB_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    if (~crc_match_in)
      begin
        $display("(%0t) Incoming CRC failed !!!", $time);
        $stop;
      end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_wishbone_go
 
 
`endif // WISHBONE_SUPPORTED
 
 
`ifdef CPU_SUPPORTED
task debug_cpu;
  input [2:0]   command;
  input [31:0]  addr;
  input [31:0]  data;
  input         gen_crc_err;
  output [31:0] result;
  input [199:0]  text;
  integer i;
 
  begin
   $write("(%0t) Task debug_cpu: ", $time);
 
    test_text = text;
 
    case (command)
//      `WB_STATUS   : 
//        begin
//          $display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text);
//          debug_wishbone_status(command, gen_crc_err);
//          last_wb_cmd = `WB_STATUS;  last_wb_cmd_text = "WB_STATUS";
//        end 
      `CPU_READ_REG   :
        begin
          $display("cpu_read_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_READ_REG;  last_wb_cmd_text = "CPU_READ_REG";
        end
      `CPU_WRITE_REG  :
        begin
          $display("cpu_write_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_WRITE_REG;  last_wb_cmd_text = "CPU_WRITE_REG";
        end
      `CPU_READ8      :
        begin
          $display("cpu_read8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_READ8;  last_wb_cmd_text = "CPU_READ8";
        end
      `CPU_READ32     :
        begin
          $display("cpu_read32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_READ32;  last_wb_cmd_text = "CPU_READ32";
        end
      `CPU_WRITE8     :
        begin
          $display("cpu_write8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_WRITE8;  last_wb_cmd_text = "CPU_WRITE8";
        end
      `CPU_WRITE32    :
        begin
          $display("cpu_write32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
          debug_cpu_set_addr(command, addr, gen_crc_err);
          last_wb_cmd = `CPU_WRITE32;  last_wb_cmd_text = "CPU_WRITE32";
        end
      `CPU_GO         :
        begin
          $display("cpu_go, data = 0x%0x, gen_crc_err=%0d (%0s))", data, gen_crc_err, text);
          debug_cpu_go(command, data, gen_crc_err);
          last_wb_cmd = `CPU_GO;  last_wb_cmd_text = "CPU_GO";
        end
      default     :
        begin
          $display("\t\tERROR: Non-existing command while debugging %0s", gen_crc_err, text);
          $stop;
        end
    endcase
  end
endtask       // debug_cpu
 
 
 
task debug_cpu_set_addr;
  input [2:0]   command;
  input [31:0]  addr;
  input         gen_crc_err;
  integer i;
 
  begin
    $display("(%0t) Task debug_cpu_set_addr: ", $time);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
    calculate_crc(1'b0);
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      calculate_crc(command[i]);
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)       // address
    begin
      tdi_pad_i<=#1 addr[i];
      calculate_crc(addr[i]);
      gen_clk(1);
    end
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
      else
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
    gen_clk(`DBG_CPU_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    if (~crc_match_in)
      begin
        $display("(%0t) Incoming CRC failed !!!", $time);
        $stop;
      end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_cpu_set_addr
 
 
 
 
task debug_cpu_go;
  input [2:0]   command;
  input [31:0]  data;
  input         gen_crc_err;
  integer i, len;
 
 
  begin
    $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
    tms_pad_i<=#1 1;
    gen_clk(1);
    tms_pad_i<=#1 0;
    gen_clk(2);  // we are in shiftDR
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
    calculate_crc(1'b0);
    gen_clk(1);
 
    for(i=2; i>=0; i=i-1)
    begin
      tdi_pad_i<=#1 command[i]; // command
      calculate_crc(command[i]);
      gen_clk(1);
    end
 
 
    if (last_wb_cmd == `CPU_WRITE32)
      begin
        len = 31;
        $display("\t\tdata = 0x%x", data);
      end
    else if ((last_wb_cmd == `CPU_WRITE8) | (last_wb_cmd == `CPU_WRITE_REG))
      begin
        len = 7;
        $display("\t\tdata = 0x%x", data[7:0]);
      end
    else
      len = 0;
 
    if (len>0)  // When CPU_WRITEx was previously activated, data needs to be shifted.
      begin
        for (i=len; i>=0; i=i-1)
          begin
            tdi_pad_i<=#1 data[i];
            calculate_crc(data[i]);
            gen_clk(1);
          end
      end
 
    for(i=31; i>=0; i=i-1)
    begin
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
      else
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
      gen_clk(1);
    end
 
    tdi_pad_i<=#1 1'hz;
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    if (last_wb_cmd == `CPU_READ32)
      len = 32;
    else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
      len = 8;
    else
      len = 0;
 
    if (len>0)    // When CPU_READx was previously activated, data needs to be shifted.
      begin
        $display("\t\tGenerating %0d clocks to read out the data.", len);
        for (i=0; i<len; i=i+1)
          gen_clk(1);
      end
 
 
    gen_clk(`DBG_CPU_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
    begin
      gen_clk(1);
    end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to exit1_dr
 
    if (~crc_match_in)
      begin
        $display("(%0t) Incoming CRC failed !!!", $time);
        $stop;
      end
 
    tms_pad_i<=#1 1;
    gen_clk(1);         // to update_dr
    tms_pad_i<=#1 0;
    gen_clk(1);         // to run_test_idle
  end
endtask       // debug_cpu_go
`endif  // CPU_SUPPORTED
 
 
 
always @ (posedge tck_pad_i)
begin
  in_data_be[31:1] <= #1 in_data_be[30:0];
  in_data_be[0]    <= #1 tdo;
 
  in_data_le[31]   <= #1 tdo;
  in_data_le[30:0] <= #1 in_data_le[31:1];
end
 
 
 
// Calculating outgoing CRC
task calculate_crc;
  input data;
 
  begin
    crc_out[0]  <= #1 data          ^ crc_out[31];
    crc_out[1]  <= #1 data          ^ crc_out[0]  ^ crc_out[31];
    crc_out[2]  <= #1 data          ^ crc_out[1]  ^ crc_out[31];
    crc_out[3]  <= #1 crc_out[2];
    crc_out[4]  <= #1 data          ^ crc_out[3]  ^ crc_out[31];
    crc_out[5]  <= #1 data          ^ crc_out[4]  ^ crc_out[31];
    crc_out[6]  <= #1 crc_out[5];
    crc_out[7]  <= #1 data          ^ crc_out[6]  ^ crc_out[31];
    crc_out[8]  <= #1 data          ^ crc_out[7]  ^ crc_out[31];
    crc_out[9]  <= #1 crc_out[8];
    crc_out[10] <= #1 data         ^ crc_out[9]  ^ crc_out[31];
    crc_out[11] <= #1 data         ^ crc_out[10] ^ crc_out[31];
    crc_out[12] <= #1 data         ^ crc_out[11] ^ crc_out[31];
    crc_out[13] <= #1 crc_out[12];
    crc_out[14] <= #1 crc_out[13];
    crc_out[15] <= #1 crc_out[14];
    crc_out[16] <= #1 data         ^ crc_out[15] ^ crc_out[31];
    crc_out[17] <= #1 crc_out[16];
    crc_out[18] <= #1 crc_out[17];
    crc_out[19] <= #1 crc_out[18];
    crc_out[20] <= #1 crc_out[19];
    crc_out[21] <= #1 crc_out[20];
    crc_out[22] <= #1 data         ^ crc_out[21] ^ crc_out[31];
    crc_out[23] <= #1 data         ^ crc_out[22] ^ crc_out[31];
    crc_out[24] <= #1 crc_out[23];
    crc_out[25] <= #1 crc_out[24];
    crc_out[26] <= #1 data         ^ crc_out[25] ^ crc_out[31];
    crc_out[27] <= #1 crc_out[26];
    crc_out[28] <= #1 crc_out[27];
    crc_out[29] <= #1 crc_out[28];
    crc_out[30] <= #1 crc_out[29];
    crc_out[31] <= #1 crc_out[30];
  end
endtask // calculate_crc
 
 
// Calculating and checking input CRC
always @(posedge tck_pad_i)
begin
  crc_in[0]  <= #1 tdo           ^ crc_in[31];
  crc_in[1]  <= #1 tdo           ^ crc_in[0]  ^ crc_in[31];
  crc_in[2]  <= #1 tdo           ^ crc_in[1]  ^ crc_in[31];
  crc_in[3]  <= #1 crc_in[2];
  crc_in[4]  <= #1 tdo           ^ crc_in[3]  ^ crc_in[31];
  crc_in[5]  <= #1 tdo           ^ crc_in[4]  ^ crc_in[31];
  crc_in[6]  <= #1 crc_in[5];
  crc_in[7]  <= #1 tdo           ^ crc_in[6]  ^ crc_in[31];
  crc_in[8]  <= #1 tdo           ^ crc_in[7]  ^ crc_in[31];
  crc_in[9]  <= #1 crc_in[8];
  crc_in[10] <= #1 tdo          ^ crc_in[9]  ^ crc_in[31];
  crc_in[11] <= #1 tdo          ^ crc_in[10] ^ crc_in[31];
  crc_in[12] <= #1 tdo          ^ crc_in[11] ^ crc_in[31];
  crc_in[13] <= #1 crc_in[12];
  crc_in[14] <= #1 crc_in[13];
  crc_in[15] <= #1 crc_in[14];
  crc_in[16] <= #1 tdo          ^ crc_in[15] ^ crc_in[31];
  crc_in[17] <= #1 crc_in[16];
  crc_in[18] <= #1 crc_in[17];
  crc_in[19] <= #1 crc_in[18];
  crc_in[20] <= #1 crc_in[19];
  crc_in[21] <= #1 crc_in[20];
  crc_in[22] <= #1 tdo          ^ crc_in[21] ^ crc_in[31];
  crc_in[23] <= #1 tdo          ^ crc_in[22] ^ crc_in[31];
  crc_in[24] <= #1 crc_in[23];
  crc_in[25] <= #1 crc_in[24];
  crc_in[26] <= #1 tdo          ^ crc_in[25] ^ crc_in[31];
  crc_in[27] <= #1 crc_in[26];
  crc_in[28] <= #1 crc_in[27];
  crc_in[29] <= #1 crc_in[28];
  crc_in[30] <= #1 crc_in[29];
  crc_in[31] <= #1 crc_in[30];
end
 
assign crc_match_in = crc_in == 32'h0;
 
 
 
/**********************************************************************************
*                                                                                 *
*   Printing the information to the screen                                        *
*                                                                                 *
**********************************************************************************/
 
`ifdef MORE_DBG_INFO
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.update_ir)
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
      `EXTEST         : $display("\tInstruction EXTEST entered");
      `SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
      `IDCODE         : $display("\tInstruction IDCODE entered");
      `MBIST          : $display("\tInstruction MBIST entered");
      `DEBUG          : $display("\tInstruction DEBUG entered");
      `BYPASS         : $display("\tInstruction BYPASS entered");
                default           :     $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
    endcase
end
`endif
 
 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
always @ (posedge tck_pad_i)
begin
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
    begin
      $display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
      $display("(%0t) Simulation stopped !!!", $time);
      $stop;
    end
end
 
 
 
 
// Detecting CRC error
/*
always @ (
           posedge dbg_tb.i_dbg_top.module_latch_en
           `ifdef WISHBONE_SUPPORTED
           or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
           `endif
           `ifdef CPU_SUPPORTED
           or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
           `endif
         )
 
 
begin
  #2;
  if (~dbg_tb.i_dbg_top.crc_match)
    begin
      $display("\t\tCRC ERROR !!!");
      $stop;
    end
end
*/
 
 
endmodule // dbg_tb
 
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_tb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7	36	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	80	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	101	mohor	`//// Copyright (C) 2000 - 2004 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	138	igorm	`// Revision 1.39 2004/03/15 16:17:07 igorm`
47			`// 'hz changed to 1'hz because Icarus complains.`
48			`//`
49	135	igorm	`// Revision 1.38 2004/01/30 10:24:02 mohor`
50			`// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are`
51			`// turned on.`
52			`//`
53	128	mohor	`// Revision 1.37 2004/01/25 14:10:25 mohor`
54			`// Display for VATS added.`
55			`//`
56	124	mohor	`// Revision 1.36 2004/01/22 13:58:51 mohor`
57			`// Port signals are all set to zero after reset.`
58			`//`
59	121	mohor	`// Revision 1.35 2004/01/22 11:07:28 mohor`
60			`// test stall_test added.`
61			`//`
62	120	mohor	`// Revision 1.34 2004/01/20 14:24:08 mohor`
63			`// Define name changed.`
64			`//`
65	117	mohor	`// Revision 1.33 2004/01/20 14:05:26 mohor`
66			`// Data latching changed when testing WB.`
67			`//`
68	116	mohor	`// Revision 1.32 2004/01/20 10:23:21 mohor`
69			`// More debug data added.`
70			`//`
71	115	mohor	`// Revision 1.31 2004/01/20 09:07:44 mohor`
72			`// CRC generation iand verification in bench changed.`
73			`//`
74	114	mohor	`// Revision 1.30 2004/01/20 08:03:35 mohor`
75			`// IDCODE test improved.`
76			`//`
77	113	mohor	`// Revision 1.29 2004/01/19 13:13:18 mohor`
78			`// Define tap_defines.v added to test bench.`
79			`//`
80	111	mohor	`// Revision 1.28 2004/01/19 12:38:10 mohor`
81			`// Waiting for "ready" improved.`
82			`//`
83	110	mohor	`// Revision 1.27 2004/01/17 18:01:31 mohor`
84			`// New version.`
85			`//`
86	102	mohor	`// Revision 1.26 2004/01/17 17:01:25 mohor`
87			`// Almost finished.`
88			`//`
89	101	mohor	`// Revision 1.25 2004/01/16 14:51:24 mohor`
90			`// cpu registers added.`
91			`//`
92	99	mohor	`// Revision 1.24 2004/01/15 10:47:13 mohor`
93			`// Working.`
94			`//`
95	96	mohor	`// Revision 1.23 2004/01/14 22:59:01 mohor`
96			`// Temp version.`
97			`//`
98	95	mohor	`// Revision 1.22 2004/01/13 11:28:30 mohor`
99			`// tmp version.`
100			`//`
101	93	mohor	`// Revision 1.21 2004/01/10 07:50:41 mohor`
102			`// temp version.`
103			`//`
104	92	mohor	`// Revision 1.20 2004/01/09 12:49:23 mohor`
105			`// tmp version.`
106			`//`
107	91	mohor	`// Revision 1.19 2004/01/08 17:53:12 mohor`
108			`// tmp version.`
109			`//`
110	90	mohor	`// Revision 1.18 2004/01/07 11:59:48 mohor`
111			`// temp4 version.`
112			`//`
113	89	mohor	`// Revision 1.17 2004/01/06 17:14:59 mohor`
114			`// temp3 version.`
115			`//`
116	88	mohor	`// Revision 1.16 2004/01/05 12:16:50 mohor`
117			`// tmp2 version.`
118			`//`
119	87	mohor	`// Revision 1.15 2003/12/23 14:26:01 mohor`
120			`// New version of the debug interface. Not finished, yet.`
121			`//`
122	80	mohor	`// Revision 1.14 2003/10/23 16:16:30 mohor`
123			`// CRC logic changed.`
124			`//`
125	73	mohor	`// Revision 1.13 2003/08/28 13:54:33 simons`
126			`// Three more chains added for cpu debug access.`
127			`//`
128	63	simons	`// Revision 1.12 2002/05/07 14:44:52 mohor`
129			`// mon_cntl_o signals that controls monitor mux added.`
130			`//`
131	47	mohor	`// Revision 1.11 2002/03/12 14:32:26 mohor`
132			`// Few outputs for boundary scan chain added.`
133			`//`
134	38	mohor	`// Revision 1.10 2002/03/08 15:27:08 mohor`
135			`// Structure changed. Hooks for jtag chain added.`
136			`//`
137	36	mohor	`// Revision 1.9 2001/10/19 11:39:20 mohor`
138			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
139			`// few different cores in a single project.`
140			`//`
141	17	mohor	`// Revision 1.8 2001/10/17 10:39:17 mohor`
142			`// bs_chain_o added.`
143			`//`
144	15	mohor	`// Revision 1.7 2001/10/16 10:10:18 mohor`
145			`// Signal names changed to lowercase.`
146			`//`
147	13	mohor	`// Revision 1.6 2001/10/15 09:52:50 mohor`
148			`// Wishbone interface added, few fixes for better performance,`
149			`// hooks for boundary scan testing added.`
150			`//`
151	12	mohor	`// Revision 1.5 2001/09/24 14:06:12 mohor`
152			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
153			`//`
154	11	mohor	`// Revision 1.4 2001/09/20 10:10:29 mohor`
155			`// Working version. Few bugs fixed, comments added.`
156			`//`
157	9	mohor	`// Revision 1.3 2001/09/19 11:54:03 mohor`
158			`// Minor changes for simulation.`
159			`//`
160	6	mohor	`// Revision 1.2 2001/09/18 14:12:43 mohor`
161			`// Trace fixed. Some registers changed, trace simplified.`
162			`//`
163	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
164			`// Initial official release.`
165			`//`
166	2	mohor	`// Revision 1.3 2001/06/01 22:23:40 mohor`
167			`// This is a backup. It is not a fully working version. Not for use, yet.`
168			`//`
169			`// Revision 1.2 2001/05/18 13:10:05 mohor`
170			`// Headers changed. All additional information is now avaliable in the README.txt file.`
171			`//`
172			`// Revision 1.1.1.1 2001/05/18 06:35:15 mohor`
173			`// Initial release`
174			`//`
175			`//`
176
177
178	17	mohor	`include "timescale.v"
179	111	mohor	`include "tap_defines.v"
180	2	mohor	`include "dbg_defines.v"
181	80	mohor	`include "dbg_wb_defines.v"
182	99	mohor	`include "dbg_cpu_defines.v"
183	2	mohor
184			`// Test bench`
185			`module dbg_tb;`
186
187	80	mohor	`parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)`
188	2	mohor
189	80	mohor	`reg tms_pad_i;`
190			`reg tck_pad_i;`
191			`reg trst_pad_i;`
192			`reg tdi_pad_i;`
193			`wire tdo_pad_o;`
194			`wire tdo_padoe_o;`
195	2	mohor
196	80	mohor	`wire shift_dr_o;`
197			`wire pause_dr_o;`
198			`wire update_dr_o;`
199	102	mohor	`wire capture_dr_o;`
200	2	mohor
201	80	mohor	`wire extest_select_o;`
202			`wire sample_preload_select_o;`
203			`wire mbist_select_o;`
204			`wire debug_select_o;`
205	2	mohor
206	128	mohor	`reg rst_i;`
207
208			`ifdef WISHBONE_SUPPORTED
209	80	mohor	`// WISHBONE common signals`
210			`reg wb_clk_i;`
211
212			`// WISHBONE master interface`
213			`wire [31:0] wb_adr_o;`
214			`wire [31:0] wb_dat_o;`
215			`wire [31:0] wb_dat_i;`
216			`wire wb_cyc_o;`
217			`wire wb_stb_o;`
218			`wire [3:0] wb_sel_o;`
219			`wire wb_we_o;`
220			`wire wb_ack_i;`
221			`wire wb_cab_o;`
222			`wire wb_err_i;`
223			`wire [2:0] wb_cti_o;`
224			`wire [1:0] wb_bte_o;`
225	128	mohor	`endif
226	2	mohor
227	128	mohor	`ifdef CPU_SUPPORTED
228	101	mohor	`// CPU signals`
229			`wire cpu_clk_i;`
230			`wire [31:0] cpu_addr_o;`
231			`wire [31:0] cpu_data_i;`
232			`wire [31:0] cpu_data_o;`
233			`wire cpu_bp_i;`
234			`wire cpu_stall_o;`
235			`wire cpu_stall_all_o;`
236			`wire cpu_stb_o;`
237			wire [`CPU_NUM -1:0] cpu_sel_o;
238			`wire cpu_we_o;`
239			`wire cpu_ack_i;`
240			`wire cpu_rst_o;`
241	128	mohor	`endif
242	101	mohor
243	87	mohor	`// Text used for easier debugging`
244	99	mohor	`reg [199:0] test_text;`
245	88	mohor	`reg [2:0] last_wb_cmd;`
246	99	mohor	`reg [199:0] last_wb_cmd_text;`
247	2	mohor
248	116	mohor	`reg [31:0] wb_data [0:4095]; // Data that is written to (read from) wishbone is stored here.`
249	2	mohor
250	12	mohor
251	116	mohor
252	80	mohor	`wire tdo_o;`
253	12	mohor
254	80	mohor	`wire debug_tdi_i;`
255			`wire bs_chain_tdi_i;`
256			`wire mbist_tdi_i;`
257	73	mohor
258	80	mohor	`reg test_enabled;`
259	73	mohor
260	80	mohor	`reg [31:0] result;`
261	113	mohor	`reg [31:0] in_data_le, in_data_be;`
262			`reg [31:0] id;`
263	88	mohor
264	110	mohor	`wire crc_match_in;`
265	114	mohor	`reg [31:0] crc_in;`
266			`reg [31:0] crc_out;`
267	138	igorm	reg [`DBG_TOP_STATUS_LEN -1:0] status;
268	99	mohor
269	80	mohor	`wire tdo;`
270	73	mohor
271	80	mohor	`assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;`
272	73	mohor
273	80	mohor	`// Connecting TAP module`
274			`tap_top i_tap_top (`
275	101	mohor	`.tms_pad_i (tms_pad_i),`
276			`.tck_pad_i (tck_pad_i),`
277			`.trst_pad_i (!trst_pad_i),`
278			`.tdi_pad_i (tdi_pad_i),`
279			`.tdo_pad_o (tdo_pad_o),`
280			`.tdo_padoe_o (tdo_padoe_o),`
281	38	mohor
282	80	mohor	`// TAP states`
283	101	mohor	`.shift_dr_o (shift_dr_o),`
284			`.pause_dr_o (pause_dr_o),`
285			`.update_dr_o (update_dr_o),`
286	102	mohor	`.capture_dr_o (capture_dr_o),`
287	38	mohor
288	80	mohor	`// Select signals for boundary scan or mbist`
289	101	mohor	`.extest_select_o (extest_select_o),`
290	80	mohor	`.sample_preload_select_o(sample_preload_select_o),`
291	101	mohor	`.mbist_select_o (mbist_select_o),`
292			`.debug_select_o (debug_select_o),`
293	2	mohor
294	80	mohor	`// TDO signal that is connected to TDI of sub-modules.`
295	101	mohor	`.tdo_o (tdo_o),`
296	38	mohor
297	80	mohor	`// TDI signals from sub-modules`
298	101	mohor	`.debug_tdi_i (debug_tdi_i), // from debug module`
299			`.bs_chain_tdi_i (bs_chain_tdi_i), // from Boundary Scan Chain`
300			`.mbist_tdi_i (mbist_tdi_i) // from Mbist Chain`
301	73	mohor
302	38	mohor	`);`
303	2	mohor
304
305	99	mohor	`// Connecting debug top module`
306	80	mohor	`dbg_top i_dbg_top (`
307	101	mohor	`.tck_i (tck_pad_i),`
308			`.tdi_i (tdo_o),`
309			`.tdo_o (debug_tdi_i),`
310	128	mohor	`.rst_i (rst_i),`
311	80	mohor
312			`// TAP states`
313	101	mohor	`.shift_dr_i (shift_dr_o),`
314			`.pause_dr_i (pause_dr_o),`
315			`.update_dr_i (update_dr_o),`
316	80	mohor
317			`// Instructions`
318	128	mohor	`.debug_select_i (debug_select_o)`
319	12	mohor
320	128	mohor	`ifdef WISHBONE_SUPPORTED
321	80	mohor	`// WISHBONE common signals`
322	128	mohor	`,`
323	101	mohor	`.wb_clk_i (wb_clk_i),`
324	80	mohor
325			`// WISHBONE master interface`
326	101	mohor	`.wb_adr_o (wb_adr_o),`
327			`.wb_dat_o (wb_dat_o),`
328			`.wb_dat_i (wb_dat_i),`
329			`.wb_cyc_o (wb_cyc_o),`
330			`.wb_stb_o (wb_stb_o),`
331			`.wb_sel_o (wb_sel_o),`
332			`.wb_we_o (wb_we_o),`
333			`.wb_ack_i (wb_ack_i),`
334			`.wb_cab_o (wb_cab_o),`
335			`.wb_err_i (wb_err_i),`
336			`.wb_cti_o (wb_cti_o),`
337	128	mohor	`.wb_bte_o (wb_bte_o)`
338			`endif
339	101	mohor
340	128	mohor	`ifdef CPU_SUPPORTED
341	101	mohor	`// CPU signals`
342	128	mohor	`,`
343	101	mohor	`.cpu_clk_i (cpu_clk_i),`
344			`.cpu_addr_o (cpu_addr_o),`
345			`.cpu_data_i (cpu_data_i),`
346			`.cpu_data_o (cpu_data_o),`
347			`.cpu_bp_i (cpu_bp_i),`
348			`.cpu_stall_o (cpu_stall_o),`
349			`.cpu_stall_all_o (cpu_stall_all_o),`
350			`.cpu_stb_o (cpu_stb_o),`
351			`.cpu_sel_o (cpu_sel_o),`
352			`.cpu_we_o (cpu_we_o),`
353			`.cpu_ack_i (cpu_ack_i),`
354			`.cpu_rst_o (cpu_rst_o)`
355	128	mohor	`endif
356	101	mohor
357
358
359	80	mohor	`);`
360	12	mohor
361
362	128	mohor	`ifdef WISHBONE_SUPPORTED
363	80	mohor	`wb_slave_behavioral wb_slave`
364			`(`
365	101	mohor	`.CLK_I (wb_clk_i),`
366	128	mohor	`.RST_I (rst_i),`
367	101	mohor	`.ACK_O (wb_ack_i),`
368			`.ADR_I (wb_adr_o),`
369			`.CYC_I (wb_cyc_o),`
370			`.DAT_O (wb_dat_i),`
371			`.DAT_I (wb_dat_o),`
372			`.ERR_O (wb_err_i),`
373			`.RTY_O (), // NOT USED for now!`
374			`.SEL_I (wb_sel_o),`
375			`.STB_I (wb_stb_o),`
376			`.WE_I (wb_we_o),`
377			`.CAB_I (1'b0)`
378	80	mohor	`);`
379	128	mohor	`endif
380	2	mohor
381
382	128	mohor	`ifdef CPU_SUPPORTED
383	101	mohor	`cpu_behavioral i_cpu_behavioral`
384			`(`
385			`// CPU signals`
386	128	mohor	`.cpu_rst_i (rst_i),`
387	101	mohor	`.cpu_clk_o (cpu_clk_i),`
388			`.cpu_addr_i (cpu_addr_o),`
389			`.cpu_data_o (cpu_data_i),`
390			`.cpu_data_i (cpu_data_o),`
391			`.cpu_bp_o (cpu_bp_i),`
392			`.cpu_stall_i (cpu_stall_o),`
393			`.cpu_stall_all_i (cpu_stall_all_o),`
394			`.cpu_stb_i (cpu_stb_o),`
395			`.cpu_sel_i (cpu_sel_o),`
396			`.cpu_we_i (cpu_we_o),`
397			`.cpu_ack_o (cpu_ack_i),`
398			`.cpu_rst_o (cpu_rst_o)`
399			`);`
400	128	mohor	`endif
401	101	mohor
402
403
404	80	mohor	`// Initial values`
405	2	mohor	`initial`
406			`begin`
407	80	mohor	`trst_pad_i = 1'b1;`
408			`tms_pad_i = 1'hz;`
409			`tck_pad_i = 1'hz;`
410			`tdi_pad_i = 1'hz;`
411
412			`#100;`
413			`trst_pad_i = 1'b0;`
414			`#100;`
415			`trst_pad_i = 1'b1;`
416	2	mohor	`end`
417
418	80	mohor	`initial`
419			`begin`
420	120	mohor	`test_enabled = 1'b0;`
421	128	mohor	`rst_i = 1'b0;`
422	80	mohor	`#1000;`
423	128	mohor	`rst_i = 1'b1;`
424	80	mohor	`#1000;`
425	128	mohor	`rst_i = 1'b0;`
426	2	mohor
427	80	mohor	`// Initial values for wishbone slave model`
428	128	mohor	`ifdef WISHBONE_SUPPORTED
429	96	mohor	wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
430	128	mohor	`endif
431	120	mohor	`#1 test_enabled<=#1 1'b1;`
432	80	mohor	`end`
433
434	128	mohor	`ifdef WISHBONE_SUPPORTED
435	80	mohor	`initial`
436	2	mohor	`begin`
437	80	mohor	`wb_clk_i = 1'b0;`
438			`forever #5 wb_clk_i = ~wb_clk_i;`
439	2	mohor	`end`
440	128	mohor	`endif
441	2	mohor
442	80	mohor	`always @ (posedge test_enabled)`
443			`begin`
444			`$display("//////////////////////////////////////////////////////////////////");`
445			`$display("// //");`
446			`$display("// (%0t) dbg_tb starting //", $time);`
447			`$display("// //");`
448			`$display("//////////////////////////////////////////////////////////////////");`
449	2	mohor
450	124	mohor	`$display("TEST: DBG_TEST");`
451
452
453	80	mohor	`initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000`
454	2	mohor
455	80	mohor	`reset_tap;`
456	95	mohor
457			`#500;`
458	80	mohor	`goto_run_test_idle;`
459	12	mohor
460	128	mohor	`ifdef CPU_SUPPORTED
461	120	mohor	`// Test stall signal`
462			`stall_test;`
463	128	mohor	`endif
464	120	mohor
465	80	mohor	`// Testing read and write to internal registers`
466			`#10000;`
467	111	mohor
468	138	igorm	`id_test;`
469	12	mohor
470	80	mohor	set_instruction(`DEBUG);
471			`#10000;`
472	2	mohor
473	138	igorm
474
475
476
477
478
479
480
481
482
483			`#100000;`
484	128	mohor	`ifdef WISHBONE_SUPPORTED
485	138	igorm	module_select(`WISHBONE_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
486	12	mohor
487	80	mohor	`#10000;`
488	138	igorm	debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
489	2	mohor
490	138	igorm	`#100000;`
491
492	116	mohor	// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
493			// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
494			// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
495	88	mohor	`//`
496	116	mohor	// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
497			// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
498	88	mohor	`//`
499	116	mohor	debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
500	88	mohor	`//`

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