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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Blame information for rev 158

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu_defines.v                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2004/03/31 14:34:09  igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.4  2004/03/28 20:27:02  igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3  2004/03/22 16:35:46  igorm
// Temp version before changing dbg interface.
//
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:33  mohor
// *** empty log message ***
//
//
//
 
 
 
// Defining length of the command
`define DBG_CPU_CMD_LEN          3'd4
`define DBG_CPU_CMD_CNT_WIDTH    3
 
// Defining length of the access_type field
`define DBG_CPU_ACC_TYPE_LEN     3'd4
 
// Defining length of the address
`define DBG_CPU_ADR_LEN          6'd32
 
// Defining length of the length register
`define DBG_CPU_LEN_LEN          5'd16
 
// Defining total length of the DR needed
`define DBG_CPU_DR_LEN           (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
 
// Defining length of the CRC
`define DBG_CPU_CRC_LEN          6'd32
`define DBG_CPU_CRC_CNT_WIDTH    6
 
// Defining length of status
`define DBG_CPU_STATUS_LEN       3'd4
`define DBG_CPU_STATUS_CNT_WIDTH 3
 
// Defining length of the data
`define DBG_CPU_DATA_CNT_WIDTH      (`DBG_CPU_LEN_LEN + 3)
`define DBG_CPU_DATA_CNT_LIM_WIDTH   `DBG_CPU_LEN_LEN
 
// Defining length of the control register
`define DBG_CPU_CTRL_LEN         2
 
//Defining commands
`define DBG_CPU_GO               4'h0
`define DBG_CPU_RD_COMM          4'h1
`define DBG_CPU_WR_COMM          4'h2
`define DBG_CPU_RD_CTRL          4'h3
`define DBG_CPU_WR_CTRL          4'h4
 
// Defining access types for wishbone
`define DBG_CPU_WRITE            4'h2
`define DBG_CPU_READ             4'h6
 
 

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu_defines.v ////`
4			`//// ////`
5			`//// ////`
6	139	igorm	`//// This file is part of the SoC Debug Interface. ////`
7	100	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	147	igorm	`// Revision 1.5 2004/03/31 14:34:09 igorm`
47			`// data_cnt_lim length changed to reduce number of warnings.`
48			`//`
49	141	igorm	`// Revision 1.4 2004/03/28 20:27:02 igorm`
50			`// New release of the debug interface (3rd. release).`
51			`//`
52	139	igorm	`// Revision 1.3 2004/03/22 16:35:46 igorm`
53			`// Temp version before changing dbg interface.`
54			`//`
55	138	igorm	`// Revision 1.2 2004/01/17 17:01:14 mohor`
56			`// Almost finished.`
57			`//`
58	101	mohor	`// Revision 1.1 2004/01/16 14:53:33 mohor`
59			`// * empty log message *`
60	100	mohor	`//`
61			`//`
62	101	mohor	`//`
63	139	igorm
64
65	100	mohor
66	139	igorm	`// Defining length of the command`
67			`define DBG_CPU_CMD_LEN 3'd4
68			`define DBG_CPU_CMD_CNT_WIDTH 3
69	100	mohor
70	139	igorm	`// Defining length of the access_type field`
71			`define DBG_CPU_ACC_TYPE_LEN 3'd4
72	100	mohor
73	139	igorm	`// Defining length of the address`
74			`define DBG_CPU_ADR_LEN 6'd32
75	100	mohor
76	139	igorm	`// Defining length of the length register`
77			`define DBG_CPU_LEN_LEN 5'd16
78	100	mohor
79	139	igorm	`// Defining total length of the DR needed`
80			`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
81	100	mohor
82	139	igorm	`// Defining length of the CRC`
83			`define DBG_CPU_CRC_LEN 6'd32
84			`define DBG_CPU_CRC_CNT_WIDTH 6
85	100	mohor
86	139	igorm	`// Defining length of status`
87			`define DBG_CPU_STATUS_LEN 3'd4
88			`define DBG_CPU_STATUS_CNT_WIDTH 3
89	100	mohor
90	139	igorm	`// Defining length of the data`
91	141	igorm	`define DBG_CPU_DATA_CNT_WIDTH (`DBG_CPU_LEN_LEN + 3)
92			`define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN
93	100	mohor
94	139	igorm	`// Defining length of the control register`
95			`define DBG_CPU_CTRL_LEN 2
96	100	mohor
97	139	igorm	`//Defining commands`
98			`define DBG_CPU_GO 4'h0
99			`define DBG_CPU_RD_COMM 4'h1
100			`define DBG_CPU_WR_COMM 4'h2
101	147	igorm	`define DBG_CPU_RD_CTRL 4'h3
102			`define DBG_CPU_WR_CTRL 4'h4
103	100	mohor
104	139	igorm	`// Defining access types for wishbone`
105			`define DBG_CPU_WRITE 4'h2
106			`define DBG_CPU_READ 4'h6
107	138	igorm
108	139	igorm

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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Blame information for rev 158