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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Blame information for rev 101

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu_defines.v                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2004/01/16 14:53:33  mohor
// *** empty log message ***
//
//
//
 
 
// Defining commands for cpu module
//`define CPU_STATUS     3'h0
`define CPU_WRITE8     3'h1
`define CPU_WRITE32    3'h2
`define CPU_WRITE_REG  3'h3
`define CPU_GO         3'h4
`define CPU_READ8      3'h5
`define CPU_READ32     3'h6
`define CPU_READ_REG   3'h7
 
 
 
 
 
// Number of supported cpus
`define CPU_NUM        2
 
 
// Registers addresses
`define CPU_OP_ADR     2'd0
`define CPU_SEL_ADR    2'd1
 
 

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	101	mohor	`// Revision 1.1 2004/01/16 14:53:33 mohor`
47			`// * empty log message *`
48	100	mohor	`//`
49			`//`
50	101	mohor	`//`
51	100	mohor
52
53			`// Defining commands for cpu module`
54			//`define CPU_STATUS 3'h0
55			`define CPU_WRITE8 3'h1
56			`define CPU_WRITE32 3'h2
57			`define CPU_WRITE_REG 3'h3
58			`define CPU_GO 3'h4
59			`define CPU_READ8 3'h5
60			`define CPU_READ32 3'h6
61			`define CPU_READ_REG 3'h7
62
63
64
65
66
67			`// Number of supported cpus`
68			`define CPU_NUM 2
69
70
71			`// Registers addresses`
72	101	mohor	`define CPU_OP_ADR 2'd0
73			`define CPU_SEL_ADR 2'd1
74	100	mohor
75

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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Blame information for rev 101