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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 139

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18  2004/03/22 16:35:46  igorm
// Temp version before changing dbg interface.
//
// Revision 1.17  2004/01/30 10:24:30  mohor
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
// turned on.
//
// Revision 1.16  2004/01/20 14:23:45  mohor
// Define name changed.
//
// Revision 1.15  2003/12/23 15:07:34  mohor
// New directory structure. New version of the debug interface.
// Files that are not needed removed.
//
// Revision 1.14  2003/10/23 16:17:00  mohor
// CRC logic changed.
//
// Revision 1.13  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.12  2003/09/17 14:38:57  simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.11  2003/08/28 13:55:21  simons
// Three more chains added for cpu debug access.
//
// Revision 1.10  2003/07/31 12:19:49  simons
// Multiple cpu support added.
//
// Revision 1.9  2002/05/07 14:43:59  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.8  2002/01/25 07:58:34  mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.7  2001/12/06 10:08:06  mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.6  2001/11/28 09:38:30  mohor
// Trace disabled by default.
//
// Revision 1.5  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:08  mohor
// Initial release
//
//
 
 
// Length of the MODULE ID register
`define DBG_TOP_MODULE_ID_LENGTH        4
 
// Length of data
`define DBG_TOP_MODULE_DATA_LEN  `DBG_TOP_MODULE_ID_LENGTH + 1
`define DBG_TOP_DATA_CNT          3
 
// Length of status
`define DBG_TOP_STATUS_LEN        3'd4
`define DBG_TOP_STATUS_CNT_WIDTH  3
 
// Length of the CRC
`define DBG_TOP_CRC_LEN           32
`define DBG_TOP_CRC_CNT           6
 
// Chains
`define DBG_TOP_CPU_DEBUG_MODULE      4'b0000
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'b0001
 
// If WISHBONE debugging is supported uncomment the folowing line
`define DBG_WISHBONE_SUPPORTED
 
// If CPU_DEBUG is supported uncomment the folowing line
`define DBG_CPU_SUPPORTED
 
// If more debug info is needed, uncomment the follofing line
//`define DBG_MORE_INFO
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6	139	igorm	`//// This file is part of the SoC Debug Interface. ////`
7	81	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	81	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	139	igorm	`//// Copyright (C) 2000 - 2004 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	139	igorm	`// Revision 1.18 2004/03/22 16:35:46 igorm`
47			`// Temp version before changing dbg interface.`
48			`//`
49	138	igorm	`// Revision 1.17 2004/01/30 10:24:30 mohor`
50			`// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are`
51			`// turned on.`
52			`//`
53	128	mohor	`// Revision 1.16 2004/01/20 14:23:45 mohor`
54			`// Define name changed.`
55			`//`
56	117	mohor	`// Revision 1.15 2003/12/23 15:07:34 mohor`
57			`// New directory structure. New version of the debug interface.`
58			`// Files that are not needed removed.`
59			`//`
60	81	mohor	`// Revision 1.14 2003/10/23 16:17:00 mohor`
61			`// CRC logic changed.`
62			`//`
63	73	mohor	`// Revision 1.13 2003/10/21 09:48:31 simons`
64			`// Mbist support added.`
65			`//`
66	71	simons	`// Revision 1.12 2003/09/17 14:38:57 simons`
67			`// WB_CNTL register added, some syncronization fixes.`
68			`//`
69	65	simons	`// Revision 1.11 2003/08/28 13:55:21 simons`
70			`// Three more chains added for cpu debug access.`
71			`//`
72	63	simons	`// Revision 1.10 2003/07/31 12:19:49 simons`
73			`// Multiple cpu support added.`
74			`//`
75	57	simons	`// Revision 1.9 2002/05/07 14:43:59 mohor`
76			`// mon_cntl_o signals that controls monitor mux added.`
77			`//`
78	47	mohor	`// Revision 1.8 2002/01/25 07:58:34 mohor`
79			`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`
80			`// not filled-in. Tested in hw.`
81			`//`
82	30	mohor	`// Revision 1.7 2001/12/06 10:08:06 mohor`
83			`// Warnings from synthesys tools fixed.`
84			`//`
85	27	mohor	`// Revision 1.6 2001/11/28 09:38:30 mohor`
86			`// Trace disabled by default.`
87			`//`
88	23	mohor	`// Revision 1.5 2001/10/15 09:55:47 mohor`
89			`// Wishbone interface added, few fixes for better performance,`
90			`// hooks for boundary scan testing added.`
91			`//`
92	12	mohor	`// Revision 1.4 2001/09/24 14:06:42 mohor`
93			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
94			`//`
95	11	mohor	`// Revision 1.3 2001/09/20 10:11:25 mohor`
96			`// Working version. Few bugs fixed, comments added.`
97			`//`
98	9	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
99			`// Trace fixed. Some registers changed, trace simplified.`
100			`//`
101	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
102			`// Initial official release.`
103			`//`
104	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
105			`// This is a backup. It is not a fully working version. Not for use, yet.`
106			`//`
107			`// Revision 1.2 2001/05/18 13:10:00 mohor`
108			`// Headers changed. All additional information is now avaliable in the README.txt file.`
109			`//`
110			`// Revision 1.1.1.1 2001/05/18 06:35:08 mohor`
111			`// Initial release`
112			`//`
113			`//`
114
115
116	138	igorm	`// Length of the MODULE ID register`
117	139	igorm	`define DBG_TOP_MODULE_ID_LENGTH 4
118	2	mohor
119	81	mohor	`// Length of data`
120	139	igorm	`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
121			`define DBG_TOP_DATA_CNT 3
122	2	mohor
123	81	mohor	`// Length of status`
124	139	igorm	`define DBG_TOP_STATUS_LEN 3'd4
125			`define DBG_TOP_STATUS_CNT_WIDTH 3
126	2	mohor
127			`// Length of the CRC`
128	139	igorm	`define DBG_TOP_CRC_LEN 32
129			`define DBG_TOP_CRC_CNT 6
130	2	mohor
131			`// Chains`
132	139	igorm	`define DBG_TOP_CPU_DEBUG_MODULE 4'b0000
133			`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'b0001
134	2	mohor
135	128	mohor	`// If WISHBONE debugging is supported uncomment the folowing line`
136	139	igorm	`define DBG_WISHBONE_SUPPORTED
137	128	mohor
138			`// If CPU_DEBUG is supported uncomment the folowing line`
139	139	igorm	`define DBG_CPU_SUPPORTED
140	128	mohor
141	138	igorm	`// If more debug info is needed, uncomment the follofing line`
142	139	igorm	//`define DBG_MORE_INFO
143	138	igorm

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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 139