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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.33  2003/10/23 16:17:01  mohor
// CRC logic changed.
//
// Revision 1.32  2003/09/18 14:00:47  simons
// Lower two address lines must be always zero.
//
// Revision 1.31  2003/09/17 14:38:57  simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.30  2003/08/28 13:55:22  simons
// Three more chains added for cpu debug access.
//
// Revision 1.29  2003/07/31 12:19:49  simons
// Multiple cpu support added.
//
// Revision 1.28  2002/11/06 14:22:41  mohor
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
//
// Revision 1.27  2002/10/10 02:42:55  mohor
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). 
// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, 
// wb_cyc_o is negated.
//
// Revision 1.26  2002/05/07 14:43:59  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.25  2002/04/22 12:54:11  mohor
// Signal names changed to lower case.
//
// Revision 1.24  2002/04/17 13:17:01  mohor
// Intentional error removed.
//
// Revision 1.23  2002/04/17 11:16:33  mohor
// A block for checking possible simulation/synthesis missmatch added.
//
// Revision 1.22  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.21  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
// Revision 1.20  2002/02/06 12:23:09  mohor
// latched_jtag_ir used when muxing TDO instead of JTAG_IR.
//
// Revision 1.19  2002/02/05 13:34:51  mohor
// Stupid bug that was entered by previous update fixed.
//
// Revision 1.18  2002/02/05 12:41:01  mohor
// trst synchronization is not needed and was removed.
//
// Revision 1.17  2002/01/25 07:58:35  mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.16  2001/12/20 11:17:26  mohor
// TDO and TDO Enable signal are separated into two signals.
//
// Revision 1.15  2001/12/05 13:28:21  mohor
// trst signal is synchronized to wb_clk_i.
//
// Revision 1.14  2001/11/28 09:36:15  mohor
// Register length fixed.
//
// Revision 1.13  2001/11/27 13:37:43  mohor
// CRC is returned when chain selection data is transmitted.
//
// Revision 1.12  2001/11/26 10:47:09  mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.11  2001/11/14 10:10:41  mohor
// Wishbone data latched on wb_clk_i instead of risc_clk.
//
// Revision 1.10  2001/11/12 01:11:27  mohor
// Reset signals are not combined any more.
//
// Revision 1.9  2001/10/19 11:40:01  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8  2001/10/17 10:39:03  mohor
// bs_chain_o added.
//
// Revision 1.7  2001/10/16 10:09:56  mohor
// Signal names changed to lowercase.
//
//
// Revision 1.6  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:55:13  mohor
// Asynchronous set/reset not used in trace any more.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
// Initial release
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module dbg_top(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                // Instructions
                debug_select_i,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
              );
 
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
// Instructions
input   debug_select_i;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
 
reg     cpu_debug_scan_chain;
reg     wishbone_scan_chain;
 
reg [`DATA_CNT -1:0]        data_cnt;
reg [`CRC_CNT -1:0]         crc_cnt;
reg [`STATUS_CNT -1:0]      status_cnt;
reg [`CHAIN_DATA_LEN -1:0]  chain_dr;
reg [`CHAIN_ID_LENGTH -1:0] chain;
 
wire data_cnt_end;
wire crc_cnt_end;
wire status_cnt_end;
reg  crc_cnt_end_q;
reg  crc_cnt_end_q2;
reg  crc_cnt_end_q3;
reg  chain_select;
reg  chain_select_error;
wire crc_out;
wire crc_match;
wire crc_en_wb;
wire shift_crc_wb;
 
wire data_shift_en;
wire selecting_command;
 
reg tdo_o;
reg wishbone_ce;
 
// data counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    data_cnt <= #1 'h0;
  else if(shift_dr_i & (~data_cnt_end))
    data_cnt <= #1 data_cnt + 1'b1;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
end
 
 
assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
 
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign crc_cnt_end = crc_cnt == `CRC_LEN;
 
 
always @ (posedge tck_i)
  begin
    crc_cnt_end_q  <= #1 crc_cnt_end;
    crc_cnt_end_q2 <= #1 crc_cnt_end_q;
    crc_cnt_end_q3 <= #1 crc_cnt_end_q2;
  end
 
 
// status counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt <= #1 'h0;
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
    status_cnt <= #1 'h0;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
 
 
assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    chain_select <= #1 1'b0;
  else if(selecting_command & tdi_i)       // Chain select
    chain_select <= #1 1'b1;
  else if (update_dr_i)
    chain_select <= #1 1'b0;
end
 
 
always @ (chain)
begin
  cpu_debug_scan_chain  <= #1 1'b0;
  wishbone_scan_chain   <= #1 1'b0;
  chain_select_error    <= #1 1'b0;
 
  case (chain)                /* synthesis parallel_case */
    `CPU_DEBUG_CHAIN      :   cpu_debug_scan_chain  <= #1 1'b1;
    `WISHBONE_SCAN_CHAIN  :   wishbone_scan_chain   <= #1 1'b1;
    default               :   chain_select_error    <= #1 1'b1;
  endcase
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    chain <= `CHAIN_ID_LENGTH'b111;
  else if(chain_select & crc_cnt_end & (~crc_cnt_end_q) & crc_match)
    chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
end
 
 
assign data_shift_en = shift_dr_i & (~data_cnt_end);
 
 
always @ (posedge tck_i)
begin
  if (data_shift_en)
    chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]};
end
 
 
// Calculating crc for input data
dbg_crc32_d1 i_dbg_crc32_d1_in
             (
              .data       (tdi_i),
              .enable     (shift_dr_i),
              .shift      (1'b0),
              .rst        (trst_i),
              .sync_rst   (update_dr_i),
              .crc_out    (),
              .clk        (tck_i),
              .crc_match  (crc_match)
             );
 
 
reg tdo_chain_select;
wire crc_en;
wire crc_en_dbg;
reg crc_started;
assign crc_en = crc_en_dbg | crc_en_wb;
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
 
always @ (posedge tck_i)
begin
  if (crc_en)
    crc_started <= #1 1'b1;
  else if (update_dr_i)
    crc_started <= #1 1'b0;
end
 
 
reg tdo_tmp;
 
 
// Calculating crc for input data
dbg_crc32_d1 i_dbg_crc32_d1_out
             (
              .data       (tdo_tmp),
              .enable     (crc_en), // enable has priority
//              .shift      (1'b0),
              .shift      (shift_dr_i & crc_started & (~crc_en)),
              .rst        (trst_i),
              .sync_rst   (update_dr_i),
              .crc_out    (crc_out),
              .clk        (tck_i),
              .crc_match  ()
             );
 
// Following status is shifted out: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 if command is "chain select", else 0
// 3. bit:          1 if non-existing chain is selected else 0
// 4. bit:          always 1
 
reg [799:0] current_on_tdo;
 
always @ (status_cnt or chain_select or crc_match or chain_select_error or crc_out)
begin
  case (status_cnt)                   /* synthesis full_case parallel_case */
    `STATUS_CNT'd0  : begin
                        tdo_chain_select = crc_match;
                        current_on_tdo = "crc_match";
                      end
    `STATUS_CNT'd1  : begin
                        tdo_chain_select = chain_select;
                        current_on_tdo = "chain_select";
                      end
    `STATUS_CNT'd2  : begin
                        tdo_chain_select = chain_select_error;
                        current_on_tdo = "chain_select_error";
                      end
    `STATUS_CNT'd3  : begin
                        tdo_chain_select = 1'b1;
                        current_on_tdo = "one 1";
                      end
    `STATUS_CNT'd4  : begin
                        tdo_chain_select = crc_out;
                  //      tdo_chain_select = 1'hz;
                        current_on_tdo = "crc_out";
                      end
  endcase
end
 
 
wire tdi_wb;
wire tdo_wb;
 
always @ (shift_crc_wb or crc_out or wishbone_ce or tdo_wb or tdo_chain_select)
begin
  if (shift_crc_wb)       // shifting crc
    tdo_tmp = crc_out;
  else if (wishbone_ce)   //  shifting data from wb
    tdo_tmp = tdo_wb;
  else
    tdo_tmp = tdo_chain_select;
end
 
 
always @ (negedge tck_i)
begin
  tdo_o <= #1 tdo_tmp;
end
 
 
 
 
// Signals for WISHBONE module
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    wishbone_ce <= #1 1'b0;
  else if(selecting_command & (~tdi_i) & wishbone_scan_chain) // wishbone CE
    wishbone_ce <= #1 1'b1;
  else if (update_dr_i)   // igor !!! This needs to be changed?
    wishbone_ce <= #1 1'b0;
end
 
 
assign tdi_wb = wishbone_ce & tdi_i;
 
// Connecting wishbone module
dbg_wb i_dbg_wb (
                  // JTAG signals
                  .trst_i        (trst_i), // trst_i is active high (inverted on higher layers)
                  .tck_i         (tck_i),
                  .tdi_i         (tdi_wb),
                  .tdo_o         (tdo_wb),
 
                  // TAP states
                  .shift_dr_i    (shift_dr_i),
                  .pause_dr_i    (pause_dr_i),
                  .update_dr_i   (update_dr_i),
 
                  .wishbone_ce_i (wishbone_ce),
                  .crc_match_i   (crc_match),
                  .crc_en_o      (crc_en_wb),
                  .shift_crc_o   (shift_crc_wb),
 
                  // WISHBONE common signals
                  .wb_rst_i      (wb_rst_i),
                  .wb_clk_i      (wb_clk_i),
 
                  // WISHBONE master interface
                  .wb_adr_o      (wb_adr_o),
                  .wb_dat_o      (wb_dat_o),
                  .wb_dat_i      (wb_dat_i),
                  .wb_cyc_o      (wb_cyc_o),
                  .wb_stb_o      (wb_stb_o),
                  .wb_sel_o      (wb_sel_o),
                  .wb_we_o       (wb_we_o),
                  .wb_ack_i      (wb_ack_i),
                  .wb_cab_o      (wb_cab_o),
                  .wb_err_i      (wb_err_i),
                  .wb_cti_o      (wb_cti_o),
                  .wb_bte_o      (wb_bte_o)
 
            );
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7	36	mohor	`//// http://www.opencores.org/projects/DebugInterface/ ////`
8	2	mohor	`//// ////`
9			`//// Author(s): ////`
10	81	mohor	`//// Igor Mohor (igorm@opencores.org) ////`
11	2	mohor	`//// ////`
12			`//// ////`
13	81	mohor	`//// All additional information is avaliable in the README.txt ////`
14	2	mohor	`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18	81	mohor	`//// Copyright (C) 2000 - 2003 Authors ////`
19	2	mohor	`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	81	mohor	`// Revision 1.33 2003/10/23 16:17:01 mohor`
47			`// CRC logic changed.`
48			`//`
49	73	mohor	`// Revision 1.32 2003/09/18 14:00:47 simons`
50			`// Lower two address lines must be always zero.`
51			`//`
52	67	simons	`// Revision 1.31 2003/09/17 14:38:57 simons`
53			`// WB_CNTL register added, some syncronization fixes.`
54			`//`
55	65	simons	`// Revision 1.30 2003/08/28 13:55:22 simons`
56			`// Three more chains added for cpu debug access.`
57			`//`
58	63	simons	`// Revision 1.29 2003/07/31 12:19:49 simons`
59			`// Multiple cpu support added.`
60			`//`
61	57	simons	`// Revision 1.28 2002/11/06 14:22:41 mohor`
62			`// Trst signal is not inverted here any more. Inverted on higher layer !!!.`
63			`//`
64	52	mohor	`// Revision 1.27 2002/10/10 02:42:55 mohor`
65	73	mohor	`// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).`
66			`// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,`
67			`// wb_cyc_o is negated.`
68	52	mohor	`//`
69	51	mohor	`// Revision 1.26 2002/05/07 14:43:59 mohor`
70			`// mon_cntl_o signals that controls monitor mux added.`
71			`//`
72	47	mohor	`// Revision 1.25 2002/04/22 12:54:11 mohor`
73			`// Signal names changed to lower case.`
74			`//`
75	44	mohor	`// Revision 1.24 2002/04/17 13:17:01 mohor`
76			`// Intentional error removed.`
77			`//`
78	43	mohor	`// Revision 1.23 2002/04/17 11:16:33 mohor`
79			`// A block for checking possible simulation/synthesis missmatch added.`
80			`//`
81	42	mohor	`// Revision 1.22 2002/03/12 10:31:53 mohor`
82			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
83			`// contains only tap state machine and related logic. dbg_top contains all`
84			`// logic necessery for debugging.`
85			`//`
86	37	mohor	`// Revision 1.21 2002/03/08 15:28:16 mohor`
87			`// Structure changed. Hooks for jtag chain added.`
88			`//`
89	36	mohor	`// Revision 1.20 2002/02/06 12:23:09 mohor`
90	81	mohor	`// latched_jtag_ir used when muxing TDO instead of JTAG_IR.`
91	36	mohor	`//`
92	33	mohor	`// Revision 1.19 2002/02/05 13:34:51 mohor`
93			`// Stupid bug that was entered by previous update fixed.`
94			`//`
95	32	mohor	`// Revision 1.18 2002/02/05 12:41:01 mohor`
96			`// trst synchronization is not needed and was removed.`
97			`//`
98	31	mohor	`// Revision 1.17 2002/01/25 07:58:35 mohor`
99			`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`
100			`// not filled-in. Tested in hw.`
101			`//`
102	30	mohor	`// Revision 1.16 2001/12/20 11:17:26 mohor`
103			`// TDO and TDO Enable signal are separated into two signals.`
104			`//`
105	28	mohor	`// Revision 1.15 2001/12/05 13:28:21 mohor`
106			`// trst signal is synchronized to wb_clk_i.`
107			`//`
108	25	mohor	`// Revision 1.14 2001/11/28 09:36:15 mohor`
109			`// Register length fixed.`
110			`//`
111	22	mohor	`// Revision 1.13 2001/11/27 13:37:43 mohor`
112			`// CRC is returned when chain selection data is transmitted.`
113			`//`
114	21	mohor	`// Revision 1.12 2001/11/26 10:47:09 mohor`
115			`// Crc generation is different for read or write commands. Small synthesys fixes.`
116			`//`
117	20	mohor	`// Revision 1.11 2001/11/14 10:10:41 mohor`
118			`// Wishbone data latched on wb_clk_i instead of risc_clk.`
119			`//`
120	19	mohor	`// Revision 1.10 2001/11/12 01:11:27 mohor`
121			`// Reset signals are not combined any more.`
122			`//`
123	18	mohor	`// Revision 1.9 2001/10/19 11:40:01 mohor`
124			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
125			`// few different cores in a single project.`
126			`//`
127	17	mohor	`// Revision 1.8 2001/10/17 10:39:03 mohor`
128			`// bs_chain_o added.`
129			`//`
130	15	mohor	`// Revision 1.7 2001/10/16 10:09:56 mohor`
131			`// Signal names changed to lowercase.`
132	13	mohor	`//`
133	15	mohor	`//`
134	13	mohor	`// Revision 1.6 2001/10/15 09:55:47 mohor`
135			`// Wishbone interface added, few fixes for better performance,`
136			`// hooks for boundary scan testing added.`
137			`//`
138	12	mohor	`// Revision 1.5 2001/09/24 14:06:42 mohor`
139			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
140			`//`
141	11	mohor	`// Revision 1.4 2001/09/20 10:11:25 mohor`
142			`// Working version. Few bugs fixed, comments added.`
143			`//`
144	9	mohor	`// Revision 1.3 2001/09/19 11:55:13 mohor`
145			`// Asynchronous set/reset not used in trace any more.`
146			`//`
147	8	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
148			`// Trace fixed. Some registers changed, trace simplified.`
149			`//`
150	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
151			`// Initial official release.`
152			`//`
153	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
154			`// This is a backup. It is not a fully working version. Not for use, yet.`
155			`//`
156			`// Revision 1.2 2001/05/18 13:10:00 mohor`
157			`// Headers changed. All additional information is now avaliable in the README.txt file.`
158			`//`
159			`// Revision 1.1.1.1 2001/05/18 06:35:02 mohor`
160			`// Initial release`
161			`//`
162			`//`
163
164	20	mohor	`// synopsys translate_off`
165	17	mohor	`include "timescale.v"
166	20	mohor	`// synopsys translate_on`
167	2	mohor	`include "dbg_defines.v"
168
169			`// Top module`
170	9	mohor	`module dbg_top(`
171	81	mohor	`// JTAG signals`
172			`trst_i, // trst_i is active high (inverted on higher layers)`
173			`tck_i,`
174			`tdi_i,`
175			`tdo_o,`
176	57	simons
177	81	mohor	`// TAP states`
178			`shift_dr_i,`
179			`pause_dr_i,`
180			`update_dr_i,`
181
182			`// Instructions`
183			`debug_select_i,`
184
185	12	mohor	`// WISHBONE common signals`
186	81	mohor	`wb_rst_i, wb_clk_i,`
187
188	12	mohor	`// WISHBONE master interface`
189			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
190	81	mohor	`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
191	2	mohor	`);`
192
193
194	81	mohor	`// JTAG signals`
195			`input trst_i;`
196			`input tck_i;`
197			`input tdi_i;`
198			`output tdo_o;`
199	2	mohor
200	81	mohor	`// TAP states`
201			`input shift_dr_i;`
202			`input pause_dr_i;`
203			`input update_dr_i;`
204	2	mohor
205	81	mohor	`// Instructions`
206			`input debug_select_i;`
207	2	mohor
208	12	mohor	`// WISHBONE common signals`
209	9	mohor	`input wb_rst_i; // WISHBONE reset`
210	12	mohor	`input wb_clk_i; // WISHBONE clock`
211	81	mohor
212	12	mohor	`// WISHBONE master interface`
213			`output [31:0] wb_adr_o;`
214			`output [31:0] wb_dat_o;`
215			`input [31:0] wb_dat_i;`
216			`output wb_cyc_o;`
217			`output wb_stb_o;`
218			`output [3:0] wb_sel_o;`
219			`output wb_we_o;`
220			`input wb_ack_i;`
221			`output wb_cab_o;`
222			`input wb_err_i;`
223	81	mohor	`output [2:0] wb_cti_o;`
224			`output [1:0] wb_bte_o;`
225	9	mohor
226	2	mohor
227	81	mohor	`reg cpu_debug_scan_chain;`
228			`reg wishbone_scan_chain;`
229	2	mohor
230	81	mohor	reg [`DATA_CNT -1:0] data_cnt;
231			reg [`CRC_CNT -1:0] crc_cnt;
232			reg [`STATUS_CNT -1:0] status_cnt;
233			reg [`CHAIN_DATA_LEN -1:0] chain_dr;
234			reg [`CHAIN_ID_LENGTH -1:0] chain;
235	9	mohor
236	81	mohor	`wire data_cnt_end;`
237			`wire crc_cnt_end;`
238			`wire status_cnt_end;`
239			`reg crc_cnt_end_q;`
240			`reg crc_cnt_end_q2;`
241			`reg crc_cnt_end_q3;`
242			`reg chain_select;`
243			`reg chain_select_error;`
244			`wire crc_out;`
245			`wire crc_match;`
246			`wire crc_en_wb;`
247			`wire shift_crc_wb;`
248	36	mohor
249	81	mohor	`wire data_shift_en;`
250			`wire selecting_command;`
251	2	mohor
252	81	mohor	`reg tdo_o;`
253			`reg wishbone_ce;`
254	73	mohor
255	81	mohor	`// data counter`
256			`always @ (posedge tck_i or posedge trst_i)`
257			`begin`
258			`if (trst_i)`
259			`data_cnt <= #1 'h0;`
260			`else if(shift_dr_i & (~data_cnt_end))`
261			`data_cnt <= #1 data_cnt + 1'b1;`
262			`else if (update_dr_i)`
263			`data_cnt <= #1 'h0;`
264			`end`
265	9	mohor
266	11	mohor
267	81	mohor	assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
268	2	mohor
269
270	81	mohor	`// crc counter`
271			`always @ (posedge tck_i or posedge trst_i)`
272	2	mohor	`begin`
273	81	mohor	`if (trst_i)`
274			`crc_cnt <= #1 'h0;`
275			`else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)`
276			`crc_cnt <= #1 crc_cnt + 1'b1;`
277			`else if (update_dr_i)`
278			`crc_cnt <= #1 'h0;`
279	2	mohor	`end`
280
281	81	mohor	assign crc_cnt_end = crc_cnt == `CRC_LEN;
282	2	mohor
283	12	mohor
284	81	mohor	`always @ (posedge tck_i)`
285	73	mohor	`begin`
286	81	mohor	`crc_cnt_end_q <= #1 crc_cnt_end;`
287			`crc_cnt_end_q2 <= #1 crc_cnt_end_q;`
288			`crc_cnt_end_q3 <= #1 crc_cnt_end_q2;`
289	73	mohor	`end`
290	20	mohor
291	2	mohor
292	81	mohor	`// status counter`
293			`always @ (posedge tck_i or posedge trst_i)`
294	2	mohor	`begin`
295	81	mohor	`if (trst_i)`
296			`status_cnt <= #1 'h0;`
297			`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
298			`status_cnt <= #1 status_cnt + 1'b1;`
299			`else if (update_dr_i)`
300			`status_cnt <= #1 'h0;`
301	2	mohor	`end`
302
303	81	mohor	assign status_cnt_end = status_cnt == `STATUS_LEN;
304	42	mohor
305
306	81	mohor	assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
307	42	mohor
308
309	81	mohor	`always @ (posedge tck_i or posedge trst_i)`
310	2	mohor	`begin`
311	81	mohor	`if (trst_i)`
312			`chain_select <= #1 1'b0;`
313			`else if(selecting_command & tdi_i) // Chain select`
314			`chain_select <= #1 1'b1;`
315			`else if (update_dr_i)`
316			`chain_select <= #1 1'b0;`
317	2	mohor	`end`
318
319
320	81	mohor	`always @ (chain)`
321	2	mohor	`begin`
322	81	mohor	`cpu_debug_scan_chain <= #1 1'b0;`
323			`wishbone_scan_chain <= #1 1'b0;`
324			`chain_select_error <= #1 1'b0;`
325
326			`case (chain) /* synthesis parallel_case */`
327			`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1;
328			`WISHBONE_SCAN_CHAIN : wishbone_scan_chain <= #1 1'b1;
329			`default : chain_select_error <= #1 1'b1;`
330			`endcase`
331	2	mohor	`end`
332
333	20	mohor
334	81	mohor	`always @ (posedge tck_i or posedge trst_i)`
335	67	simons	`begin`
336	81	mohor	`if (trst_i)`
337			chain <= `CHAIN_ID_LENGTH'b111;
338			`else if(chain_select & crc_cnt_end & (~crc_cnt_end_q) & crc_match)`
339			chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
340	67	simons	`end`
341
342	2	mohor
343	81	mohor	`assign data_shift_en = shift_dr_i & (~data_cnt_end);`
344	2	mohor
345
346	81	mohor	`always @ (posedge tck_i)`
347	2	mohor	`begin`
348	81	mohor	`if (data_shift_en)`
349			chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]};
350	2	mohor	`end`
351
352
353	81	mohor	`// Calculating crc for input data`
354			`dbg_crc32_d1 i_dbg_crc32_d1_in`
355			`(`
356			`.data (tdi_i),`
357			`.enable (shift_dr_i),`
358			`.shift (1'b0),`
359			`.rst (trst_i),`
360			`.sync_rst (update_dr_i),`
361			`.crc_out (),`
362			`.clk (tck_i),`
363			`.crc_match (crc_match)`
364			`);`
365	2	mohor
366	12	mohor
367	81	mohor	`reg tdo_chain_select;`
368			`wire crc_en;`
369			`wire crc_en_dbg;`
370			`reg crc_started;`
371			`assign crc_en = crc_en_dbg \| crc_en_wb;`
372			`assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);`
373	12	mohor
374	81	mohor	`always @ (posedge tck_i)`
375	12	mohor	`begin`
376	81	mohor	`if (crc_en)`
377			`crc_started <= #1 1'b1;`
378			`else if (update_dr_i)`
379			`crc_started <= #1 1'b0;`
380	12	mohor	`end`
381
382
383	81	mohor	`reg tdo_tmp;`
384	12	mohor
385	51	mohor
386	81	mohor	`// Calculating crc for input data`
387			`dbg_crc32_d1 i_dbg_crc32_d1_out`
388			`(`
389			`.data (tdo_tmp),`
390			`.enable (crc_en), // enable has priority`
391			`// .shift (1'b0),`
392			`.shift (shift_dr_i & crc_started & (~crc_en)),`
393			`.rst (trst_i),`
394			`.sync_rst (update_dr_i),`
395			`.crc_out (crc_out),`
396			`.clk (tck_i),`
397			`.crc_match ()`
398			`);`
399	51	mohor
400	81	mohor	`// Following status is shifted out:`
401			`// 1. bit: 1 if crc is OK, else 0`
402			`// 2. bit: 1 if command is "chain select", else 0`
403			`// 3. bit: 1 if non-existing chain is selected else 0`
404			`// 4. bit: always 1`
405	51	mohor
406	81	mohor	`reg [799:0] current_on_tdo;`
407	51	mohor
408	81	mohor	`always @ (status_cnt or chain_select or crc_match or chain_select_error or crc_out)`
409	51	mohor	`begin`
410	81	mohor	`case (status_cnt) /* synthesis full_case parallel_case */`
411			`STATUS_CNT'd0 : begin
412			`tdo_chain_select = crc_match;`
413			`current_on_tdo = "crc_match";`
414			`end`
415			`STATUS_CNT'd1 : begin
416			`tdo_chain_select = chain_select;`
417			`current_on_tdo = "chain_select";`
418			`end`
419			`STATUS_CNT'd2 : begin
420			`tdo_chain_select = chain_select_error;`
421			`current_on_tdo = "chain_select_error";`
422			`end`
423			`STATUS_CNT'd3 : begin
424			`tdo_chain_select = 1'b1;`
425			`current_on_tdo = "one 1";`
426			`end`
427			`STATUS_CNT'd4 : begin
428			`tdo_chain_select = crc_out;`
429			`// tdo_chain_select = 1'hz;`
430			`current_on_tdo = "crc_out";`
431			`end`
432			`endcase`
433	51	mohor	`end`
434
435
436	81	mohor	`wire tdi_wb;`
437			`wire tdo_wb;`
438	5	mohor
439	81	mohor	`always @ (shift_crc_wb or crc_out or wishbone_ce or tdo_wb or tdo_chain_select)`
440	11	mohor	`begin`
441	81	mohor	`if (shift_crc_wb) // shifting crc`
442			`tdo_tmp = crc_out;`
443			`else if (wishbone_ce) // shifting data from wb`
444			`tdo_tmp = tdo_wb;`
445	11	mohor	`else`
446	81	mohor	`tdo_tmp = tdo_chain_select;`
447	11	mohor	`end`
448	9	mohor
449	11	mohor
450	81	mohor	`always @ (negedge tck_i)`
451	2	mohor	`begin`
452	81	mohor	`tdo_o <= #1 tdo_tmp;`
453	2	mohor	`end`
454
455
456
457
458	81	mohor	`// Signals for WISHBONE module`
459	9	mohor
460
461	81	mohor	`always @ (posedge tck_i or posedge trst_i)`
462	2	mohor	`begin`
463	81	mohor	`if (trst_i)`
464			`wishbone_ce <= #1 1'b0;`
465			`else if(selecting_command & (~tdi_i) & wishbone_scan_chain) // wishbone CE`
466			`wishbone_ce <= #1 1'b1;`
467			`else if (update_dr_i) // igor !!! This needs to be changed?`
468			`wishbone_ce <= #1 1'b0;`
469	2	mohor	`end`
470
471
472	81	mohor	`assign tdi_wb = wishbone_ce & tdi_i;`
473	2	mohor
474	81	mohor	`// Connecting wishbone module`
475			`dbg_wb i_dbg_wb (`
476			`// JTAG signals`
477			`.trst_i (trst_i), // trst_i is active high (inverted on higher layers)`
478			`.tck_i (tck_i),`
479			`.tdi_i (tdi_wb),`
480			`.tdo_o (tdo_wb),`
481	2	mohor
482	81	mohor	`// TAP states`
483			`.shift_dr_i (shift_dr_i),`
484			`.pause_dr_i (pause_dr_i),`
485			`.update_dr_i (update_dr_i),`
486	2	mohor
487	81	mohor	`.wishbone_ce_i (wishbone_ce),`
488			`.crc_match_i (crc_match),`
489			`.crc_en_o (crc_en_wb),`
490			`.shift_crc_o (shift_crc_wb),`
491	2	mohor
492	81	mohor	`// WISHBONE common signals`
493			`.wb_rst_i (wb_rst_i),`
494			`.wb_clk_i (wb_clk_i),`
495	5	mohor
496	81	mohor	`// WISHBONE master interface`
497			`.wb_adr_o (wb_adr_o),`
498			`.wb_dat_o (wb_dat_o),`
499			`.wb_dat_i (wb_dat_i),`
500			`.wb_cyc_o (wb_cyc_o),`

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