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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2004/01/16 14:51:33  mohor
// cpu registers added.
//
// Revision 1.13  2004/01/15 12:09:43  mohor
// Working.
//
// Revision 1.12  2004/01/14 22:59:18  mohor
// Temp version.
//
// Revision 1.11  2004/01/14 12:29:40  mohor
// temp version. Resets will be changed in next version.
//
// Revision 1.10  2004/01/13 11:28:14  mohor
// tmp version.
//
// Revision 1.9  2004/01/10 07:50:24  mohor
// temp version.
//
// Revision 1.8  2004/01/09 12:48:44  mohor
// tmp version.
//
// Revision 1.7  2004/01/08 17:53:36  mohor
// tmp version.
//
// Revision 1.6  2004/01/07 11:58:56  mohor
// temp4 version.
//
// Revision 1.5  2004/01/06 17:15:19  mohor
// temp3 version.
//
// Revision 1.4  2004/01/05 12:16:00  mohor
// tmp2 version.
//
// Revision 1.3  2003/12/23 16:22:46  mohor
// Tmp version.
//
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
 
                // WISHBONE common signals
                wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input         tck_i;
input         tdi_i;
output        tdo_o;
 
// TAP states
input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;
 
input         wishbone_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;
// WISHBONE common signals
input         wb_clk_i;
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg    [31:0] wb_dat_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg    [50:0] dr;
wire          enable;
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_len_cnt_en;
reg     [5:0] addr_len_cnt;
reg     [5:0] addr_len_cnt_limit;
wire          addr_len_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg    [18:0] data_cnt;
reg    [18:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
reg           status_reset_en;
 
reg           crc_match_reg;
 
reg     [2:0] cmd, cmd_old, dr_cmd_latched;
reg    [31:0] adr;
reg    [15:0] len;
reg           start_rd_tck;
reg           rd_tck_started;
reg           start_rd_sync1;
reg           start_wb_rd;
reg           start_wb_rd_q;
reg           start_wr_tck;
reg           start_wr_sync1;
reg           start_wb_wr;
reg           start_wb_wr_q;
 
wire          dr_read;
wire          dr_write;
wire          dr_go;
 
reg           dr_write_latched;
reg           dr_read_latched;
reg           dr_go_latched;
 
wire          status_cnt_end;
 
wire          byte, half, long;
reg           byte_q, half_q, long_q;
reg           byte_q2, half_q2, long_q2;
reg           cmd_read;
reg           cmd_write;
reg           cmd_go;
 
reg           status_cnt1, status_cnt2, status_cnt3, status_cnt4;
 
reg [`STATUS_LEN -1:0] status;
 
reg           wb_error, wb_error_sync, wb_error_tck;
reg           wb_overrun, wb_overrun_sync, wb_overrun_tck;
reg           underrun_tck;
 
reg           busy_wb;
reg           busy_tck;
reg           wb_end;
reg           wb_end_rst;
reg           wb_end_rst_sync;
reg           wb_end_sync;
reg           wb_end_tck, wb_end_tck_q;
reg           busy_sync;
reg   [799:0] tdo_text;
reg   [399:0] latching_data_text;
reg           latch_data;
reg   [199:0] status_text;
 
reg           set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
reg           read_cycle;
reg           write_cycle;
reg     [2:0] rw_type;
wire   [31:0] input_data;
 
wire          len_eq_0;
wire          crc_cnt_31;
 
reg     [1:0] ptr;
reg     [2:0] fifo_cnt;
wire          fifo_full;
wire          fifo_empty;
reg     [7:0] mem [0:3];
reg     [2:0] mem_ptr;
reg           wishbone_ce_sync;
reg           wishbone_ce_rst;
wire          go_prelim;
 
 
 
assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
// Selecting where to take the data from 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    ptr <= #1 2'h0;
  else if (read_cycle & crc_cnt_31) // first latch
    ptr <= #1 ptr + 1'b1;
  else if (read_cycle & byte & (~byte_q))
    ptr <= ptr + 1'd1;
end
 
 
// Shift register for shifting in and out the data
always @ (posedge tck_i)
begin
  if (read_cycle & crc_cnt_31)
    begin
      dr[31:0] <= #1 input_data[31:0];
      latch_data <= #1 1'b1;
      latching_data_text <= #1 "First latch";
    end
  else if (read_cycle & crc_cnt_end)
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : begin
                      if(byte & (~byte_q))
                        begin
                          case (ptr)    // synthesis parallel_case
                            2'b00 : dr[31:24] <= #1 input_data[31:24];
                            2'b01 : dr[31:24] <= #1 input_data[23:16];
                            2'b10 : dr[31:24] <= #1 input_data[15:8];
                            2'b11 : dr[31:24] <= #1 input_data[7:0];
                          endcase
                          latch_data <= #1 1'b1;
                          latching_data_text <= #1 "8 bit latched";
                        end
                      else
                        begin
                          dr[31:24] <= #1 {dr[30:24], 1'b0};
                          latch_data <= #1 1'b0;
                          latching_data_text <= #1 "8 bit shifted";
                        end
                    end
        `WB_READ16: begin
                      if(half & (~half_q))
                        begin
                          if (ptr[1])
                            dr[31:16] <= #1 input_data[15:0];
                          else
                            dr[31:16] <= #1 input_data[31:16];
                          latching_data_text <= #1 "16 bit latched";
                          latch_data <= #1 1'b1;
                        end
                      else
                        begin
                          dr[31:16] <= #1 {dr[30:16], 1'b0};
                          latch_data <= #1 1'b0;
                          latching_data_text <= #1 "16 bit shifted";
                        end
                    end
        `WB_READ32: begin
                      if(long & (~long_q))
                        begin
                          dr[31:0] <= #1 input_data[31:0];
                          latch_data <= #1 1'b1;
                          latching_data_text <= #1 "32 bit latched";
                        end
                      else
                        begin
                          dr[31:0] <= #1 {dr[30:0], 1'b0};
                          latch_data <= #1 1'b0;
                          latching_data_text <= #1 "32 bit shifted";
                        end
                    end
      endcase
    end
  else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
    begin
      dr <= #1 {dr[49:0], tdi_i};
      latch_data <= #1 1'b0;
      latching_data_text <= #1 "tdi shifted in";
    end
  else
    latching_data_text <= #1 "nothing";
end
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_len_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_len_cnt <= #1 'h0;
  else if (addr_len_cnt_en)
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
 
assign byte = data_cnt[2:0] == 3'd7;
assign half = data_cnt[3:0] == 4'd15;
assign long = data_cnt[4:0] == 5'd31;
 
 
always @ (posedge tck_i)
begin
  byte_q <= #1 byte;
  half_q <= #1 half;
  long_q <= #1 long;
  byte_q2 <= #1 byte_q;
  half_q2 <= #1 half_q;
  long_q2 <= #1 long_q;
end
 
 
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
assign dr_go = dr[2:0] == `WB_GO;
 
 
// Latching instruction
always @ (posedge tck_i)
begin
  if (update_dr_i)
    begin
      dr_cmd_latched <= #1 3'h0;
      dr_read_latched  <= #1 1'b0;
      dr_write_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_cmd_latched <= #1 dr[2:0];
      dr_read_latched <= #1 dr_read;
      dr_write_latched <= #1 dr_write;
      dr_go_latched <= #1 dr_go;
    end
end
 
 
// Upper limit. Address/length counter counts until this value is reached
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))                                   // (current command is WB_STATUS or WB_GO)
        addr_len_cnt_limit <= #1 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_len_cnt_limit <= #1 6'd48;
    end
end
 
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i)
begin
  if (update_dr_i)
    data_cnt_limit <= #1 {len, 3'b000};
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end  & (~write_cycle) | (data_cnt_end & write_cycle));
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <= #1 'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign crc_cnt_31 = crc_cnt  == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q  <= #1 crc_cnt_end;
  cmd_cnt_end_q  <= #1 cmd_cnt_end;
  data_cnt_end_q <= #1 data_cnt_end;
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & read_cycle |
           crc_cnt_end & (~read_cycle)
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
assign status_cnt_end = status_cnt4;
 
 
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
    status <= #1 'h0;
    status_text <= #1 "reset";
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
    begin
    status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
    status_text <= #1 "!!!READ";
    end
  else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
    begin
    status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
    status_text <= #1 "READ";
    end
  else if (shift_dr_i & (~status_cnt_end))
    begin
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
    status_text <= #1 "shift";
    end
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if overrun occured during write (data couldn't be written fast enough)
//                    or underrun occured during read (data couldn't be read fast enough)
// 4. bit:          1 if WB error occured, else 0
 
 
// TDO multiplexer
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or crc_match_i or
          data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    tdo_text = "busy_tck";
    end
  else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
    begin
      tdo_o = crc_match_i;
      tdo_text = "crc_match_i";
    end
  else if (read_cycle & crc_cnt_end & (~data_cnt_end))
    begin
    tdo_o = dr[31];
    tdo_text = "read data";
    end
  else if (read_cycle & data_cnt_end & (~data_cnt_end_q))     // cmd is already updated
    begin
      tdo_o = crc_match_reg;
      tdo_text = "crc_match_reg";
    end
  else if (crc_cnt_end & data_cnt_end)  // cmd is already updated
    begin
      tdo_o = status[0];
      tdo_text = "status";
    end
  else
    begin
      tdo_o = 1'b0;
      tdo_text = "zero while CRC is shifted in";
    end
end
 
 
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <= #1 crc_match_i;
end
 
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cmd <= #1 'h0;
      cmd_old <= #1 'h0;
      cmd_read <= #1 1'b0;
      cmd_write <= #1 1'b0;
      cmd_go <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd <= #1 dr_cmd_latched;
      cmd_old <= #1 cmd;
      cmd_read <= #1 dr_read_latched;
      cmd_write <= #1 dr_write_latched;
      cmd_go <= #1 dr_go_latched;
    end
end
 
 
// Latching address
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (dr_write_latched | dr_read_latched)
        begin
          adr <= #1 dr[47:16];
          set_addr <= #1 1'b1;
        end
    end
  else
    set_addr <= #1 1'b0;
end
 
 
// Length counter
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
    len <= #1 dr[15:0];
  else if (start_rd_tck)
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : len <= #1 len - 1'd1;
        `WB_READ16: len <= #1 len - 2'd2;
        `WB_READ32: len <= #1 len - 3'd4;
      endcase
    end
end
 
 
assign len_eq_0 = len == 16'h0;
 
 
// Start wishbone read cycle
always @ (posedge tck_i)
begin
  if (read_cycle & (~dr_go_latched) & (~len_eq_0))              // First read after cmd is entered
    start_rd_tck <= #1 1'b1;
  else if ((~start_rd_tck) & read_cycle & (~len_eq_0) & (~fifo_full) & (~rd_tck_started))
    start_rd_tck <= #1 1'b1;
  else
    start_rd_tck <= #1 1'b0;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    rd_tck_started <= #1 1'b0;
  else if (start_rd_tck)
    rd_tck_started <= #1 1'b1;
  else if (wb_end_tck & (~wb_end_tck_q))
    rd_tck_started <= #1 1'b0;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle <= #1 1'b0;
  else if (cmd_read & go_prelim)
    read_cycle <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if ((cmd_read | cmd_write) & go_prelim)
    rw_type <= #1 cmd;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle <= #1 1'b0;
  else if (cmd_write & go_prelim)
    write_cycle <= #1 1'b1;
end
 
 
// Start wishbone write cycle
always @ (posedge tck_i)
begin
  if (write_cycle)
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_WRITE8  : begin
                        if (byte_q & (~byte_q2))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE16 : begin
                        if (half_q & (~half_q2))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE32 : begin
                        if (long_q & (~long_q2))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 dr[31:0];
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
      endcase
    end
  else
    start_wr_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_rd_sync1  <= #1 start_rd_tck;
  start_wb_rd     <= #1 start_rd_sync1;
  start_wb_rd_q   <= #1 start_wb_rd;
 
  start_wr_sync1  <= #1 start_wr_tck;
  start_wb_wr     <= #1 start_wr_sync1;
  start_wb_wr_q   <= #1 start_wb_wr;
 
  set_addr_sync   <= #1 set_addr;
  set_addr_wb     <= #1 set_addr_sync;
  set_addr_wb_q   <= #1 set_addr_wb;
end
 
 
// wb_cyc_o
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_cyc_o <= #1 1'b0;
  else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i)
    wb_cyc_o <= #1 1'b0;
end
 
 
// wb_adr_o logic
always @ (posedge wb_clk_i)
begin
  if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((rw_type == `WB_WRITE16) | (rw_type == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
 
//    adr   byte  |  short  |  long
//     0    1000     1100      1111
//     1    0100     err       err
//     2    0010     0011      err
//     3    0001     err       err
// wb_sel_o logic
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_sel_o[3:0] <= #1 4'h0;
  else
    begin
      wb_sel_o[0] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                        (rw_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[1] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1] ^ rw_type[0]) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[2] <= #1 (rw_type[1]) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
      wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
    end
end
 
 
assign wb_we_o = write_cycle;
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
 
// Logic for detecting end of transaction
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
      wb_end_tck_q<= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
      wb_end_tck_q<= #1 wb_end_tck;
    end
end
 
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
// Detecting WB error
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
    wb_error <= #1 1'b0;
end
 
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
// Detecting overrun when write operation.
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_overrun <= #1 1'b0;
  else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
    wb_overrun <= #1 1'b1;
  else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
    wb_overrun <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_overrun_sync <= #1 wb_overrun;
  wb_overrun_tck  <= #1 wb_overrun_sync;
end
 
 
// Detecting underrun when read operation
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    underrun_tck <= #1 1'b0;
  else if(latch_data & fifo_empty & (~data_cnt_end))
    underrun_tck <= #1 1'b1;
  else if(read_cycle & status_reset_en) // error remains active until STATUS read is performed
    underrun_tck <= #1 1'b0;
end
 
 
 
// wb_error is locked until WB_STATUS is performed
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_reset_en <= 1'b0;
  else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
    status_reset_en <= #1 1'b1;
  else
    status_reset_en <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  wishbone_ce_sync <= #1  wishbone_ce_i;
  wishbone_ce_rst  <= #1 ~wishbone_ce_sync;
end
 
 
// Logic for latching data that is read from wishbone
always @ (posedge wb_clk_i)
begin
  if(wishbone_ce_rst)
    mem_ptr <= #1 'h0;
  else if (wb_ack_i)
    begin
      if (rw_type == `WB_READ8)
        mem_ptr <= #1 mem_ptr + 1'd1;
      else if (rw_type == `WB_READ16)
        mem_ptr <= #1 mem_ptr + 2'd2;
    end
end
 
 
// Logic for latching data that is read from wishbone
always @ (posedge wb_clk_i)
begin
  if (wb_ack_i)
    begin
      case (wb_sel_o)    // synthesis parallel_case full_case 
        4'b1000  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24];            // byte 
        4'b0100  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16];            // byte
        4'b0010  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08];            // byte
        4'b0001  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:00];            // byte
 
        4'b1100  :                                                      // half
                    begin
                      mem[mem_ptr[1:0]]      <= #1 wb_dat_i[31:24];
                      mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16];
                    end
        4'b0011  :                                                      // half
                    begin
                      mem[mem_ptr[1:0]]      <= #1 wb_dat_i[15:08];
                      mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:00];
                    end
        4'b1111  :                                                      // long
                    begin
                      mem[0] <= #1 wb_dat_i[31:24];
                      mem[1] <= #1 wb_dat_i[23:16];
                      mem[2] <= #1 wb_dat_i[15:08];
                      mem[3] <= #1 wb_dat_i[07:00];
                    end
      endcase
    end
end
 
 
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
 
 
// Fifo counter and empty/full detection
always @ (posedge tck_i)
begin
  if (update_dr_i)
    fifo_cnt <= #1 'h0;
  else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data))  // incrementing
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
        `WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
        `WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4;
      endcase
    end
  else if (~(wb_end_tck & (~wb_end_tck_q)) & latch_data)  // decrementing
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1;
        `WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2;
        `WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4;
      endcase
    end
end
 
 
assign fifo_full = fifo_cnt == 3'h4;
assign fifo_empty = fifo_cnt == 3'h0;
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	102	mohor	`// Revision 1.14 2004/01/16 14:51:33 mohor`
47			`// cpu registers added.`
48			`//`
49	99	mohor	`// Revision 1.13 2004/01/15 12:09:43 mohor`
50			`// Working.`
51			`//`
52	97	mohor	`// Revision 1.12 2004/01/14 22:59:18 mohor`
53			`// Temp version.`
54			`//`
55	95	mohor	`// Revision 1.11 2004/01/14 12:29:40 mohor`
56			`// temp version. Resets will be changed in next version.`
57			`//`
58	94	mohor	`// Revision 1.10 2004/01/13 11:28:14 mohor`
59			`// tmp version.`
60			`//`
61	93	mohor	`// Revision 1.9 2004/01/10 07:50:24 mohor`
62			`// temp version.`
63			`//`
64	92	mohor	`// Revision 1.8 2004/01/09 12:48:44 mohor`
65			`// tmp version.`
66			`//`
67	91	mohor	`// Revision 1.7 2004/01/08 17:53:36 mohor`
68			`// tmp version.`
69			`//`
70	90	mohor	`// Revision 1.6 2004/01/07 11:58:56 mohor`
71			`// temp4 version.`
72			`//`
73	89	mohor	`// Revision 1.5 2004/01/06 17:15:19 mohor`
74			`// temp3 version.`
75			`//`
76	88	mohor	`// Revision 1.4 2004/01/05 12:16:00 mohor`
77			`// tmp2 version.`
78			`//`
79	87	mohor	`// Revision 1.3 2003/12/23 16:22:46 mohor`
80			`// Tmp version.`
81			`//`
82	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
83			`// Small fix.`
84			`//`
85	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
86			`// New directory structure. New version of the debug interface.`
87	82	mohor	`//`
88			`//`
89	83	mohor	`//`
90	82	mohor
91			`// synopsys translate_off`
92			`include "timescale.v"
93			`// synopsys translate_on`
94			`include "dbg_wb_defines.v"
95
96			`// Top module`
97			`module dbg_wb(`
98			`// JTAG signals`
99			`tck_i,`
100			`tdi_i,`
101			`tdo_o,`
102
103			`// TAP states`
104			`shift_dr_i,`
105			`pause_dr_i,`
106			`update_dr_i,`
107
108			`wishbone_ce_i,`
109			`crc_match_i,`
110			`crc_en_o,`
111			`shift_crc_o,`
112	95	mohor	`rst_i,`
113	82	mohor
114			`// WISHBONE common signals`
115	95	mohor	`wb_clk_i,`
116	82	mohor
117			`// WISHBONE master interface`
118			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
119			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
120
121			`);`
122
123			`// JTAG signals`
124	97	mohor	`input tck_i;`
125			`input tdi_i;`
126			`output tdo_o;`
127	82	mohor
128			`// TAP states`
129	97	mohor	`input shift_dr_i;`
130			`input pause_dr_i;`
131			`input update_dr_i;`
132	82	mohor
133	97	mohor	`input wishbone_ce_i;`
134			`input crc_match_i;`
135			`output crc_en_o;`
136			`output shift_crc_o;`
137			`input rst_i;`
138	82	mohor	`// WISHBONE common signals`
139	97	mohor	`input wb_clk_i;`
140	82	mohor
141			`// WISHBONE master interface`
142			`output [31:0] wb_adr_o;`
143			`output [31:0] wb_dat_o;`
144			`input [31:0] wb_dat_i;`
145			`output wb_cyc_o;`
146			`output wb_stb_o;`
147			`output [3:0] wb_sel_o;`
148			`output wb_we_o;`
149			`input wb_ack_i;`
150			`output wb_cab_o;`
151			`input wb_err_i;`
152			`output [2:0] wb_cti_o;`
153			`output [1:0] wb_bte_o;`
154
155			`reg wb_cyc_o;`
156			`reg [31:0] wb_adr_o;`
157	88	mohor	`reg [31:0] wb_dat_o;`
158	82	mohor	`reg [3:0] wb_sel_o;`
159
160			`reg tdo_o;`
161
162	88	mohor	`reg [50:0] dr;`
163			`wire enable;`
164	90	mohor	`wire cmd_cnt_en;`
165	88	mohor	`reg [1:0] cmd_cnt;`
166			`wire cmd_cnt_end;`
167			`reg cmd_cnt_end_q;`
168	90	mohor	`wire addr_len_cnt_en;`
169	88	mohor	`reg [5:0] addr_len_cnt;`
170			`reg [5:0] addr_len_cnt_limit;`
171			`wire addr_len_cnt_end;`
172	90	mohor	`wire crc_cnt_en;`
173	88	mohor	`reg [5:0] crc_cnt;`
174			`wire crc_cnt_end;`
175			`reg crc_cnt_end_q;`
176	90	mohor	`wire data_cnt_en;`
177	88	mohor	`reg [18:0] data_cnt;`
178			`reg [18:0] data_cnt_limit;`
179			`wire data_cnt_end;`
180	90	mohor	`reg data_cnt_end_q;`
181	88	mohor	`reg status_reset_en;`
182	82	mohor
183	90	mohor	`reg crc_match_reg;`
184	82	mohor
185	92	mohor	`reg [2:0] cmd, cmd_old, dr_cmd_latched;`
186			`reg [31:0] adr;`
187			`reg [15:0] len;`
188			`reg start_rd_tck;`
189	97	mohor	`reg rd_tck_started;`
190	92	mohor	`reg start_rd_sync1;`
191			`reg start_wb_rd;`
192			`reg start_wb_rd_q;`
193			`reg start_wr_tck;`
194			`reg start_wr_sync1;`
195			`reg start_wb_wr;`
196			`reg start_wb_wr_q;`
197	88	mohor
198	92	mohor	`wire dr_read;`
199			`wire dr_write;`
200			`wire dr_go;`
201	88	mohor
202	92	mohor	`reg dr_write_latched;`
203			`reg dr_read_latched;`
204			`reg dr_go_latched;`
205	82	mohor
206	92	mohor	`wire status_cnt_end;`
207	89	mohor
208	92	mohor	`wire byte, half, long;`
209			`reg byte_q, half_q, long_q;`
210	94	mohor	`reg byte_q2, half_q2, long_q2;`
211	92	mohor	`reg cmd_read;`
212			`reg cmd_write;`
213			`reg cmd_go;`
214	90	mohor
215	92	mohor	`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
216	90	mohor
217	92	mohor	reg [`STATUS_LEN -1:0] status;
218
219	97	mohor	`reg wb_error, wb_error_sync, wb_error_tck;`
220			`reg wb_overrun, wb_overrun_sync, wb_overrun_tck;`
221			`reg underrun_tck;`
222	92	mohor
223	97	mohor	`reg busy_wb;`
224			`reg busy_tck;`
225			`reg wb_end;`
226			`reg wb_end_rst;`
227			`reg wb_end_rst_sync;`
228			`reg wb_end_sync;`
229			`reg wb_end_tck, wb_end_tck_q;`
230			`reg busy_sync;`
231			`reg [799:0] tdo_text;`
232			`reg [399:0] latching_data_text;`
233			`reg latch_data;`
234			`reg [199:0] status_text;`
235	92	mohor
236	97	mohor	`reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;`
237			`reg read_cycle;`
238			`reg write_cycle;`
239			`reg [2:0] rw_type;`
240			`wire [31:0] input_data;`
241	92	mohor
242	97	mohor	`wire len_eq_0;`
243			`wire crc_cnt_31;`
244	93	mohor
245	97	mohor	`reg [1:0] ptr;`
246			`reg [2:0] fifo_cnt;`
247			`wire fifo_full;`
248			`wire fifo_empty;`
249			`reg [7:0] mem [0:3];`
250			`reg [2:0] mem_ptr;`
251			`reg wishbone_ce_sync;`
252			`reg wishbone_ce_rst;`
253			`wire go_prelim;`
254
255
256
257	82	mohor	`assign enable = wishbone_ce_i & shift_dr_i;`
258	90	mohor	`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
259	89	mohor	`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
260	82	mohor
261
262	97	mohor	`// Selecting where to take the data from`
263	82	mohor	`always @ (posedge tck_i)`
264			`begin`
265	93	mohor	`if (update_dr_i)`
266			`ptr <= #1 2'h0;`
267	95	mohor	`else if (read_cycle & crc_cnt_31) // first latch`
268	93	mohor	`ptr <= #1 ptr + 1'b1;`
269	95	mohor	`else if (read_cycle & byte & (~byte_q))`
270	93	mohor	`ptr <= ptr + 1'd1;`
271			`end`
272
273
274	97	mohor	`// Shift register for shifting in and out the data`
275	93	mohor	`always @ (posedge tck_i)`
276			`begin`
277	95	mohor	`if (read_cycle & crc_cnt_31)`
278	90	mohor	`begin`
279	93	mohor	`dr[31:0] <= #1 input_data[31:0];`
280	97	mohor	`latch_data <= #1 1'b1;`
281	99	mohor	`latching_data_text <= #1 "First latch";`
282	93	mohor	`end`
283			`else if (read_cycle & crc_cnt_end)`
284			`begin`
285	95	mohor	`case (rw_type) // synthesis parallel_case full_case`
286	90	mohor	`WB_READ8 : begin
287			`if(byte & (~byte_q))`
288	92	mohor	`begin`
289	93	mohor	`case (ptr) // synthesis parallel_case`
290			`2'b00 : dr[31:24] <= #1 input_data[31:24];`
291			`2'b01 : dr[31:24] <= #1 input_data[23:16];`
292			`2'b10 : dr[31:24] <= #1 input_data[15:8];`
293			`2'b11 : dr[31:24] <= #1 input_data[7:0];`
294			`endcase`
295	97	mohor	`latch_data <= #1 1'b1;`
296	99	mohor	`latching_data_text <= #1 "8 bit latched";`
297	92	mohor	`end`
298	90	mohor	`else`
299	92	mohor	`begin`
300	93	mohor	`dr[31:24] <= #1 {dr[30:24], 1'b0};`
301	97	mohor	`latch_data <= #1 1'b0;`
302	99	mohor	`latching_data_text <= #1 "8 bit shifted";`
303	92	mohor	`end`
304	90	mohor	`end`
305			`WB_READ16: begin
306			`if(half & (~half_q))`
307	92	mohor	`begin`
308	93	mohor	`if (ptr[1])`
309	97	mohor	`dr[31:16] <= #1 input_data[15:0];`
310			`else`
311	93	mohor	`dr[31:16] <= #1 input_data[31:16];`
312	99	mohor	`latching_data_text <= #1 "16 bit latched";`
313	97	mohor	`latch_data <= #1 1'b1;`
314	92	mohor	`end`
315	90	mohor	`else`
316	92	mohor	`begin`
317	93	mohor	`dr[31:16] <= #1 {dr[30:16], 1'b0};`
318	97	mohor	`latch_data <= #1 1'b0;`
319	99	mohor	`latching_data_text <= #1 "16 bit shifted";`
320	92	mohor	`end`
321	90	mohor	`end`
322			`WB_READ32: begin
323			`if(long & (~long_q))`
324	92	mohor	`begin`
325	93	mohor	`dr[31:0] <= #1 input_data[31:0];`
326	97	mohor	`latch_data <= #1 1'b1;`
327	99	mohor	`latching_data_text <= #1 "32 bit latched";`
328	92	mohor	`end`
329	90	mohor	`else`
330	92	mohor	`begin`
331	93	mohor	`dr[31:0] <= #1 {dr[30:0], 1'b0};`
332	97	mohor	`latch_data <= #1 1'b0;`
333	99	mohor	`latching_data_text <= #1 "32 bit shifted";`
334	92	mohor	`end`
335	90	mohor	`end`
336			`endcase`
337			`end`
338	94	mohor	`else if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle)))`
339	92	mohor	`begin`
340	99	mohor	`dr <= #1 {dr[49:0], tdi_i};`
341			`latch_data <= #1 1'b0;`
342			`latching_data_text <= #1 "tdi shifted in";`
343	92	mohor	`end`
344	94	mohor	`else`
345	99	mohor	`latching_data_text <= #1 "nothing";`
346	82	mohor	`end`
347
348
349	90	mohor	`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
350	88	mohor
351	97	mohor
352			`// Command counter`
353	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
354	82	mohor	`begin`
355	95	mohor	`if (rst_i)`
356	87	mohor	`cmd_cnt <= #1 'h0;`
357	82	mohor	`else if (update_dr_i)`
358	87	mohor	`cmd_cnt <= #1 'h0;`
359	90	mohor	`else if (cmd_cnt_en)`
360	87	mohor	`cmd_cnt <= #1 cmd_cnt + 1'b1;`
361	82	mohor	`end`
362
363
364	90	mohor	`assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);`
365
366	97	mohor
367			`// Address/length counter`
368	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
369	87	mohor	`begin`
370	95	mohor	`if (rst_i)`
371	88	mohor	`addr_len_cnt <= #1 'h0;`
372			`else if (update_dr_i)`
373			`addr_len_cnt <= #1 'h0;`
374	90	mohor	`else if (addr_len_cnt_en)`
375	88	mohor	`addr_len_cnt <= #1 addr_len_cnt + 1'b1;`
376			`end`
377
378
379	95	mohor	`assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle \| crc_cnt_end & read_cycle);`
380	90	mohor
381	97	mohor
382			`// Data counter`
383	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
384	88	mohor	`begin`
385	95	mohor	`if (rst_i)`
386	87	mohor	`data_cnt <= #1 'h0;`
387			`else if (update_dr_i)`
388			`data_cnt <= #1 'h0;`
389	90	mohor	`else if (data_cnt_en)`
390	87	mohor	`data_cnt <= #1 data_cnt + 1'b1;`
391			`end`
392	82	mohor
393	87	mohor
394	88	mohor
395	93	mohor	`assign byte = data_cnt[2:0] == 3'd7;`
396			`assign half = data_cnt[3:0] == 4'd15;`
397			`assign long = data_cnt[4:0] == 5'd31;`
398	88	mohor
399
400			`always @ (posedge tck_i)`
401			`begin`
402	95	mohor	`byte_q <= #1 byte;`
403			`half_q <= #1 half;`
404			`long_q <= #1 long;`
405			`byte_q2 <= #1 byte_q;`
406			`half_q2 <= #1 half_q;`
407			`long_q2 <= #1 long_q;`
408	88	mohor	`end`
409
410
411	89	mohor	assign dr_read = (dr[2:0] == `WB_READ8) \| (dr[2:0] == `WB_READ16) \| (dr[2:0] == `WB_READ32);
412			assign dr_write = (dr[2:0] == `WB_WRITE8) \| (dr[2:0] == `WB_WRITE16) \| (dr[2:0] == `WB_WRITE32);
413			assign dr_go = dr[2:0] == `WB_GO;
414	88	mohor
415
416	97	mohor	`// Latching instruction`
417	88	mohor	`always @ (posedge tck_i)`
418			`begin`
419			`if (update_dr_i)`
420	91	mohor	`begin`
421	99	mohor	`dr_cmd_latched <= #1 3'h0;`
422	91	mohor	`dr_read_latched <= #1 1'b0;`
423			`dr_write_latched <= #1 1'b0;`
424			`dr_go_latched <= #1 1'b0;`
425			`end`
426	88	mohor	`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
427	91	mohor	`begin`
428	99	mohor	`dr_cmd_latched <= #1 dr[2:0];`
429	91	mohor	`dr_read_latched <= #1 dr_read;`
430			`dr_write_latched <= #1 dr_write;`
431			`dr_go_latched <= #1 dr_go;`
432			`end`
433	88	mohor	`end`
434
435
436	97	mohor	`// Upper limit. Address/length counter counts until this value is reached`
437	88	mohor	`always @ (posedge tck_i)`
438			`begin`
439	90	mohor	`if (cmd_cnt == 2'h2)`
440	88	mohor	`begin`
441	95	mohor	`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
442	99	mohor	`addr_len_cnt_limit <= #1 6'd0;`
443	90	mohor	`else // (current command is WB_WRITEx or WB_READx)`
444	99	mohor	`addr_len_cnt_limit <= #1 6'd48;`
445	88	mohor	`end`
446			`end`
447
448
449	94	mohor	`assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);`
450
451	88	mohor
452	97	mohor	`// Upper limit. Data counter counts until this value is reached.`
453	94	mohor	`always @ (posedge tck_i)`
454			`begin`
455			`if (update_dr_i)`
456	99	mohor	`data_cnt_limit <= #1 {len, 3'b000};`
457	94	mohor	`end`
458	88	mohor
459	90	mohor
460	94	mohor	`assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) \| (data_cnt_end & write_cycle));`
461
462	97	mohor
463	82	mohor	`// crc counter`
464	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
465	82	mohor	`begin`
466	95	mohor	`if (rst_i)`
467	82	mohor	`crc_cnt <= #1 'h0;`
468	90	mohor	`else if(crc_cnt_en)`
469	82	mohor	`crc_cnt <= #1 crc_cnt + 1'b1;`
470			`else if (update_dr_i)`
471			`crc_cnt <= #1 'h0;`
472			`end`
473
474	87	mohor	`assign cmd_cnt_end = cmd_cnt == 2'h3;`
475	88	mohor	`assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;`
476	87	mohor	`assign crc_cnt_end = crc_cnt == 6'd32;`
477	93	mohor	`assign crc_cnt_31 = crc_cnt == 6'd31;`
478	89	mohor	`assign data_cnt_end = (data_cnt == data_cnt_limit);`
479	82	mohor
480			`always @ (posedge tck_i)`
481			`begin`
482	90	mohor	`crc_cnt_end_q <= #1 crc_cnt_end;`
483			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
484			`data_cnt_end_q <= #1 data_cnt_end;`
485	82	mohor	`end`
486
487	90	mohor
488	97	mohor	`// Status counter is made of 4 serialy connected registers`
489	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
490	82	mohor	`begin`
491	95	mohor	`if (rst_i)`
492	90	mohor	`status_cnt1 <= #1 1'b0;`
493	82	mohor	`else if (update_dr_i)`
494	90	mohor	`status_cnt1 <= #1 1'b0;`
495	94	mohor	`else if (data_cnt_end & read_cycle \|`
496	95	mohor	`crc_cnt_end & (~read_cycle)`
497	90	mohor	`)`
498			`status_cnt1 <= #1 1'b1;`
499	82	mohor	`end`
500

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