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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/12/23 16:22:46  mohor
// Tmp version.
//
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg [`WB_DR_LEN -1:0] dr;
wire enable;
reg [1:0] cmd_cnt;
reg [5:0] data_cnt;
reg [5:0] crc_cnt;
wire      cmd_cnt_end;
wire      data_cnt_end;
wire      crc_cnt_end;
reg       crc_cnt_end_q;
reg       status_reset_en;
 
 
reg [`STATUS_CNT -1:0]      status_cnt;
wire status_cnt_end;
 
assign enable = wishbone_ce_i & shift_dr_i;
assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i;  // Signals dbg module to shift out the CRC
 
 
always @ (posedge tck_i)
begin
  if (enable & (~data_cnt_end))
    dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (enable & (~cmd_cnt_end))
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (enable & cmd_cnt_end & (~data_cnt_end))
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
  else if(enable & data_cnt_end & (~crc_cnt_end))
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign data_cnt_end = data_cnt == 6'd48;
assign crc_cnt_end  = crc_cnt  == 6'd32;
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q <= #1 crc_cnt_end;
end
 
// status counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt <= #1 'h0;
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
    status_cnt <= #1 'h0;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
reg [`STATUS_LEN -1:0] status;
reg address_unaligned;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_timeout, wb_timeout_sync, wb_timeout_tck;
 
reg busy_wb;
reg busy_tck;
reg wb_end;
reg wb_end_rst;
reg wb_end_rst_sync;
reg wb_end_sync;
reg wb_end_tck;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status <= #1 'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    begin
      if (dr[2:0] == `WB_STATUS)
        status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, busy_tck};
      else
        status <= #1 {crc_match_i, 2'b10, address_unaligned};
    end
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
// Following status is shifted out after each command except WB_STATUS: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 if address is unaligned, else 0
// 3. bit:          always 0
// 4. bit:          always 1
 
// Following status is shifted out after WB_STATUS: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if WB timeout occured, else 0
// 4. bit:          1 if WB error occured, else 0
 
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
    end
  else if (crc_cnt_end & (~crc_cnt_end_q))
    begin
      tdo_o = crc_match_i;
      TDO_WISHBONE = "crc_match_i";
    end
  else if (crc_cnt_end)
    begin
      tdo_o = status[0];
      TDO_WISHBONE = "status";
    end
  else
    begin
      tdo_o = 1'b0;
      TDO_WISHBONE = "zero while CRC is shifted in";
    end
end
 
assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
 
reg [2:0]  cmd, cmd_old;
reg [31:0] adr;
reg [15:0] len;
reg start_tck;
reg start_sync1;
reg start_wb;
reg start_wb_q;
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd <= #1 dr[2:0];
      cmd_old <= #1 cmd;
      adr <= #1 dr[34:3];
      len <= #1 dr[50:35];
      start_tck <= #1 1'b1;
    end
  else
    start_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_sync1 <= #1 start_tck;
  start_wb <= #1 start_sync1;
  start_wb_q <= #1 start_wb;
end
 
reg [7:0] acc_cnt;
wire acc_cnt_limit;
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_cyc_o <= #1 1'b0;
  else if (start_wb & (~start_wb_q) & cmd[2])     // "read" or "go" command   igor !!! tu pride se nekaj, ki starta vse naslednje accesse
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i | acc_cnt_limit)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
  if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((cmd == `WB_WRITE8) | (cmd == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((cmd == `WB_WRITE16) | (cmd == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
always @ (wb_adr_o or cmd)
begin
  wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
  wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
  wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
  wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
end
//      byte  |  short  |  long
//  0   1000     1100      1111
//  1   0100     err       err
//  2   0010     0011      err
//  3   0001     err       err
 
 
always @ (dr)
begin
  address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
end
 
`define WB_STATUS     3'h0  // 000
`define WB_WRITE8     3'h1  // 001
`define WB_WRITE16    3'h2  // 010
`define WB_WRITE32    3'h3  // 011
`define WB_GO         3'h4  // 100
`define WB_READ8      3'h5  // 101
`define WB_READ16     3'h6  // 110
`define WB_READ32     3'h7  // 111
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    acc_cnt<= #1 8'h0;
  else
  if(wb_ack_i | wb_err_i | acc_cnt_limit)
    acc_cnt<= #1 8'h0;
  else
  if(wb_cyc_o)
    acc_cnt<= #1 acc_cnt + 1'b1;
end
 
assign acc_cnt_limit = acc_cnt==8'hff;
 
 
assign wb_we_o = ~cmd[2];   // Status or write (for simpler logic status is allowed)
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
reg [31:0] input_data;
 
always @ (posedge wb_clk_i)
begin
  if(wb_ack_i)
    input_data <= #1 wb_dat_i;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i | acc_cnt_limit)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
    end
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if((wb_ack_i | acc_cnt_limit) & status_reset_en) // error remains active until STATUS read is performed
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_timeout <= #1 1'b0;
  else if(acc_cnt_limit)
    wb_timeout <= #1 1'b1;
  else if((wb_ack_i | wb_err_i) & status_reset_en)  // error remains active until STATUS read is performed
    wb_timeout <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_timeout_sync <= #1 wb_timeout;
  wb_timeout_tck  <= #1 wb_timeout_sync;
end
 
 
 
// wb_timeout and wb_error are locked until WB_STATUS is performed
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_reset_en <= 1'b0;
  else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
    status_reset_en <= #1 1'b1;
  else
    status_reset_en <= #1 1'b0;
end
 
endmodule
 

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	87	mohor	`// Revision 1.3 2003/12/23 16:22:46 mohor`
47			`// Tmp version.`
48			`//`
49	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
50			`// Small fix.`
51			`//`
52	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
53			`// New directory structure. New version of the debug interface.`
54	82	mohor	`//`
55			`//`
56	83	mohor	`//`
57	82	mohor
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "dbg_wb_defines.v"
62
63			`// Top module`
64			`module dbg_wb(`
65			`// JTAG signals`
66			`trst_i, // trst_i is active high (inverted on higher layers)`
67			`tck_i,`
68			`tdi_i,`
69			`tdo_o,`
70
71			`// TAP states`
72			`shift_dr_i,`
73			`pause_dr_i,`
74			`update_dr_i,`
75
76			`wishbone_ce_i,`
77			`crc_match_i,`
78			`crc_en_o,`
79			`shift_crc_o,`
80
81			`// WISHBONE common signals`
82			`wb_rst_i, wb_clk_i,`
83
84			`// WISHBONE master interface`
85			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
86			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
87
88			`);`
89
90			`// JTAG signals`
91			`input trst_i;`
92			`input tck_i;`
93			`input tdi_i;`
94			`output tdo_o;`
95
96			`// TAP states`
97			`input shift_dr_i;`
98			`input pause_dr_i;`
99			`input update_dr_i;`
100
101			`input wishbone_ce_i;`
102			`input crc_match_i;`
103			`output crc_en_o;`
104			`output shift_crc_o;`
105
106			`// WISHBONE common signals`
107			`input wb_rst_i; // WISHBONE reset`
108			`input wb_clk_i; // WISHBONE clock`
109
110			`// WISHBONE master interface`
111			`output [31:0] wb_adr_o;`
112			`output [31:0] wb_dat_o;`
113			`input [31:0] wb_dat_i;`
114			`output wb_cyc_o;`
115			`output wb_stb_o;`
116			`output [3:0] wb_sel_o;`
117			`output wb_we_o;`
118			`input wb_ack_i;`
119			`output wb_cab_o;`
120			`input wb_err_i;`
121			`output [2:0] wb_cti_o;`
122			`output [1:0] wb_bte_o;`
123
124			`reg wb_cyc_o;`
125			`reg [31:0] wb_adr_o;`
126			`reg [3:0] wb_sel_o;`
127
128			`reg tdo_o;`
129
130			reg [`WB_DR_LEN -1:0] dr;
131			`wire enable;`
132	87	mohor	`reg [1:0] cmd_cnt;`
133			`reg [5:0] data_cnt;`
134	82	mohor	`reg [5:0] crc_cnt;`
135	87	mohor	`wire cmd_cnt_end;`
136			`wire data_cnt_end;`
137	82	mohor	`wire crc_cnt_end;`
138			`reg crc_cnt_end_q;`
139	87	mohor	`reg status_reset_en;`
140	82	mohor
141
142			reg [`STATUS_CNT -1:0] status_cnt;
143			`wire status_cnt_end;`
144
145			`assign enable = wishbone_ce_i & shift_dr_i;`
146			`assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC`
147
148
149			`always @ (posedge tck_i)`
150			`begin`
151	87	mohor	`if (enable & (~data_cnt_end))`
152	82	mohor	dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
153			`end`
154
155
156			`always @ (posedge tck_i or posedge trst_i)`
157			`begin`
158			`if (trst_i)`
159	87	mohor	`cmd_cnt <= #1 'h0;`
160	82	mohor	`else if (update_dr_i)`
161	87	mohor	`cmd_cnt <= #1 'h0;`
162			`else if (enable & (~cmd_cnt_end))`
163			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
164	82	mohor	`end`
165
166
167	87	mohor	`always @ (posedge tck_i or posedge trst_i)`
168			`begin`
169			`if (trst_i)`
170			`data_cnt <= #1 'h0;`
171			`else if (update_dr_i)`
172			`data_cnt <= #1 'h0;`
173			`else if (enable & cmd_cnt_end & (~data_cnt_end))`
174			`data_cnt <= #1 data_cnt + 1'b1;`
175			`end`
176	82	mohor
177	87	mohor
178	82	mohor	`// crc counter`
179			`always @ (posedge tck_i or posedge trst_i)`
180			`begin`
181			`if (trst_i)`
182			`crc_cnt <= #1 'h0;`
183	87	mohor	`else if(enable & data_cnt_end & (~crc_cnt_end))`
184	82	mohor	`crc_cnt <= #1 crc_cnt + 1'b1;`
185			`else if (update_dr_i)`
186			`crc_cnt <= #1 'h0;`
187			`end`
188
189	87	mohor	`assign cmd_cnt_end = cmd_cnt == 2'h3;`
190			`assign data_cnt_end = data_cnt == 6'd48;`
191			`assign crc_cnt_end = crc_cnt == 6'd32;`
192	82	mohor
193			`always @ (posedge tck_i)`
194			`begin`
195			`crc_cnt_end_q <= #1 crc_cnt_end;`
196			`end`
197
198			`// status counter`
199			`always @ (posedge tck_i or posedge trst_i)`
200			`begin`
201			`if (trst_i)`
202			`status_cnt <= #1 'h0;`
203			`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
204			`status_cnt <= #1 status_cnt + 1'b1;`
205			`else if (update_dr_i)`
206			`status_cnt <= #1 'h0;`
207			`end`
208
209			assign status_cnt_end = status_cnt == `STATUS_LEN;
210			reg [`STATUS_LEN -1:0] status;
211			`reg address_unaligned;`
212
213			`reg wb_error, wb_error_sync, wb_error_tck;`
214			`reg wb_timeout, wb_timeout_sync, wb_timeout_tck;`
215
216	86	mohor	`reg busy_wb;`
217			`reg busy_tck;`
218			`reg wb_end;`
219			`reg wb_end_rst;`
220			`reg wb_end_rst_sync;`
221			`reg wb_end_sync;`
222			`reg wb_end_tck;`
223			`reg busy_sync;`
224			`reg [799:0] TDO_WISHBONE;`
225	82	mohor
226			`always @ (posedge tck_i or posedge trst_i)`
227			`begin`
228			`if (trst_i)`
229			`status <= #1 'h0;`
230			`else if(crc_cnt_end & (~crc_cnt_end_q))`
231			`begin`
232			if (dr[2:0] == `WB_STATUS)
233	86	mohor	`status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, busy_tck};`
234			`else`
235	82	mohor	`status <= #1 {crc_match_i, 2'b10, address_unaligned};`
236			`end`
237			`else if (shift_dr_i & (~status_cnt_end))`
238			status <= #1 {status[0], status[`STATUS_LEN -1:1]};
239			`end`
240	86	mohor	`// Following status is shifted out after each command except WB_STATUS:`
241	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
242			`// 2. bit: 1 if address is unaligned, else 0`
243			`// 3. bit: always 0`
244			`// 4. bit: always 1`
245
246	86	mohor	`// Following status is shifted out after WB_STATUS:`
247	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
248	86	mohor	`// 2. bit: 1 while WB access is in progress (busy_tck), else 0`
249	82	mohor	`// 3. bit: 1 if WB timeout occured, else 0`
250			`// 4. bit: 1 if WB error occured, else 0`
251
252
253			`always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)`
254			`begin`
255			`if (pause_dr_i)`
256	87	mohor	`begin`
257	82	mohor	`tdo_o = busy_tck;`
258			`TDO_WISHBONE = "busy_tck";`
259	87	mohor	`end`
260	82	mohor	`else if (crc_cnt_end & (~crc_cnt_end_q))`
261	87	mohor	`begin`
262			`tdo_o = crc_match_i;`
263			`TDO_WISHBONE = "crc_match_i";`
264			`end`
265			`else if (crc_cnt_end)`
266			`begin`
267			`tdo_o = status[0];`
268			`TDO_WISHBONE = "status";`
269			`end`
270	82	mohor	`else`
271	87	mohor	`begin`
272			`tdo_o = 1'b0;`
273			`TDO_WISHBONE = "zero while CRC is shifted in";`
274			`end`
275	82	mohor	`end`
276
277			`assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;`
278
279	87	mohor	`reg [2:0] cmd, cmd_old;`
280	82	mohor	`reg [31:0] adr;`
281			`reg [15:0] len;`
282			`reg start_tck;`
283			`reg start_sync1;`
284			`reg start_wb;`
285			`reg start_wb_q;`
286
287			`always @ (posedge tck_i)`
288			`begin`
289			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
290			`begin`
291			`cmd <= #1 dr[2:0];`
292	87	mohor	`cmd_old <= #1 cmd;`
293	82	mohor	`adr <= #1 dr[34:3];`
294			`len <= #1 dr[50:35];`
295			`start_tck <= #1 1'b1;`
296			`end`
297			`else`
298			`start_tck <= #1 1'b0;`
299			`end`
300
301
302			`always @ (posedge wb_clk_i)`
303			`begin`
304			`start_sync1 <= #1 start_tck;`
305			`start_wb <= #1 start_sync1;`
306			`start_wb_q <= #1 start_wb;`
307			`end`
308
309			`reg [7:0] acc_cnt;`
310			`wire acc_cnt_limit;`
311
312			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
313			`begin`
314			`if (wb_rst_i)`
315			`wb_cyc_o <= #1 1'b0;`
316			`else if (start_wb & (~start_wb_q) & cmd[2]) // "read" or "go" command igor !!! tu pride se nekaj, ki starta vse naslednje accesse`
317			`wb_cyc_o <= #1 1'b1;`
318			`else if (wb_ack_i \| wb_err_i \| acc_cnt_limit)`
319			`wb_cyc_o <= #1 1'b0;`
320			`end`
321
322
323
324			`always @ (posedge wb_clk_i)`
325			`begin`
326			if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
327			`wb_adr_o <= #1 adr;`
328			`else if (wb_ack_i)`
329			`begin`
330			if ((cmd == `WB_WRITE8) \| (cmd == `WB_READ8))
331			`wb_adr_o <= #1 wb_adr_o + 1'd1;`
332			else if ((cmd == `WB_WRITE16) \| (cmd == `WB_READ16))
333			`wb_adr_o <= #1 wb_adr_o + 2'd2;`
334			`else`
335			`wb_adr_o <= #1 wb_adr_o + 3'd4;`
336			`end`
337			`end`
338
339
340			`always @ (wb_adr_o or cmd)`
341			`begin`
342			`wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) \|`
343			`(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);`
344			`wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);`
345			`wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);`
346			`wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);`
347			`end`
348			`// byte \| short \| long`
349			`// 0 1000 1100 1111`
350			`// 1 0100 err err`
351			`// 2 0010 0011 err`
352			`// 3 0001 err err`
353
354
355			`always @ (dr)`
356			`begin`
357			`address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) \| (dr[1:0] == 2'b10) & (dr[3]);`
358			`end`
359
360			`define WB_STATUS 3'h0 // 000
361			`define WB_WRITE8 3'h1 // 001
362			`define WB_WRITE16 3'h2 // 010
363			`define WB_WRITE32 3'h3 // 011
364			`define WB_GO 3'h4 // 100
365			`define WB_READ8 3'h5 // 101
366			`define WB_READ16 3'h6 // 110
367			`define WB_READ32 3'h7 // 111
368
369			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
370			`begin`
371			`if(wb_rst_i)`
372			`acc_cnt<= #1 8'h0;`
373			`else`
374			`if(wb_ack_i \| wb_err_i \| acc_cnt_limit)`
375			`acc_cnt<= #1 8'h0;`
376			`else`
377			`if(wb_cyc_o)`
378			`acc_cnt<= #1 acc_cnt + 1'b1;`
379			`end`
380
381			`assign acc_cnt_limit = acc_cnt==8'hff;`
382
383
384			`assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)`
385			`assign wb_cab_o = 1'b0;`
386			`assign wb_stb_o = wb_cyc_o;`
387			`assign wb_cti_o = 3'h0; // always performing single access`
388			`assign wb_bte_o = 2'h0; // always performing single access`
389
390	86	mohor	`reg [31:0] input_data;`
391	82	mohor
392			`always @ (posedge wb_clk_i)`
393			`begin`
394			`if(wb_ack_i)`
395	86	mohor	`input_data <= #1 wb_dat_i;`
396	82	mohor	`end`
397
398
399
400			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
401			`begin`
402			`if (wb_rst_i)`
403	86	mohor	`wb_end <= #1 1'b0;`
404			`else if (wb_ack_i \| wb_err_i \| acc_cnt_limit)`
405			`wb_end <= #1 1'b1;`
406			`else if (wb_end_rst)`
407			`wb_end <= #1 1'b0;`
408	82	mohor	`end`
409
410
411			`always @ (posedge tck_i or posedge trst_i)`
412			`begin`
413			`if (trst_i)`
414			`begin`
415	86	mohor	`wb_end_sync <= #1 1'b0;`
416			`wb_end_tck <= #1 1'b0;`
417	82	mohor	`end`
418			`else`
419			`begin`
420	86	mohor	`wb_end_sync <= #1 wb_end;`
421			`wb_end_tck <= #1 wb_end_sync;`
422	82	mohor	`end`
423			`end`
424
425
426			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
427			`begin`
428			`if (wb_rst_i)`
429			`busy_wb <= #1 1'b0;`
430	86	mohor	`else if (wb_end_rst)`
431	82	mohor	`busy_wb <= #1 1'b0;`
432			`else if (wb_cyc_o)`
433			`busy_wb <= #1 1'b1;`
434			`end`
435
436
437			`always @ (posedge tck_i or posedge trst_i)`
438			`begin`
439			`if (trst_i)`
440			`begin`
441			`busy_sync <= #1 1'b0;`
442			`busy_tck <= #1 1'b0;`
443			`end`
444			`else`
445			`begin`
446			`busy_sync <= #1 busy_wb;`
447			`busy_tck <= #1 busy_sync;`
448			`end`
449			`end`
450
451
452			`always @ (posedge wb_clk_i)`
453			`begin`
454	86	mohor	`wb_end_rst_sync <= #1 wb_end_tck;`
455			`wb_end_rst <= #1 wb_end_rst_sync;`
456	82	mohor	`end`
457
458
459			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
460			`begin`
461			`if (wb_rst_i)`
462			`wb_error <= #1 1'b0;`
463			`else if(wb_err_i)`
464			`wb_error <= #1 1'b1;`
465	87	mohor	`else if((wb_ack_i \| acc_cnt_limit) & status_reset_en) // error remains active until STATUS read is performed`
466	82	mohor	`wb_error <= #1 1'b0;`
467			`end`
468
469			`always @ (posedge tck_i)`
470			`begin`
471			`wb_error_sync <= #1 wb_error;`
472			`wb_error_tck <= #1 wb_error_sync;`
473			`end`
474
475
476			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
477			`begin`
478			`if (wb_rst_i)`
479			`wb_timeout <= #1 1'b0;`
480			`else if(acc_cnt_limit)`
481			`wb_timeout <= #1 1'b1;`
482	87	mohor	`else if((wb_ack_i \| wb_err_i) & status_reset_en) // error remains active until STATUS read is performed`
483	82	mohor	`wb_timeout <= #1 1'b0;`
484			`end`
485
486			`always @ (posedge tck_i)`
487			`begin`
488			`wb_timeout_sync <= #1 wb_timeout;`
489			`wb_timeout_tck <= #1 wb_timeout_sync;`
490			`end`
491
492
493	87	mohor
494			`// wb_timeout and wb_error are locked until WB_STATUS is performed`
495			`always @ (posedge tck_i or posedge trst_i)`
496			`begin`
497			`if (trst_i)`
498			`status_reset_en <= 1'b0;`
499			else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
500			`status_reset_en <= #1 1'b1;`

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