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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2004/01/05 12:16:00  mohor
// tmp2 version.
//
// Revision 1.3  2003/12/23 16:22:46  mohor
// Tmp version.
//
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg    [31:0] wb_dat_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg    [50:0] dr;
wire          enable;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
reg     [5:0] addr_len_cnt;
reg     [5:0] addr_len_cnt_limit;
wire          addr_len_cnt_end;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
reg    [18:0] data_cnt;
reg    [18:0] data_cnt_limit;
wire          data_cnt_end;
reg           status_reset_en;
 
 
reg [`STATUS_CNT -1:0]      status_cnt;
// reg [31:0] data_tck;
 
 
reg [2:0]  cmd, cmd_old;
reg [31:0] adr;
reg [15:0] len;
reg start_tck;
reg start_sync1;
reg start_wb;
reg start_wb_q;
 
 
wire status_cnt_end;
 
assign enable = wishbone_ce_i & shift_dr_i;
assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i;  // Signals dbg module to shift out the CRC
 
 
always @ (posedge tck_i)
begin
//  if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end)))
  if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
    dr <= #1 {dr[49:0], tdi_i};
end
 
 
//always @ (posedge tck_i)
//begin
//  if (enable & (data_cnt_end))  // Igor !!! perhaps not needed data_cnt_end
//    data_tck <= #1 {data_tck[30:0], tdi_i};
//end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (enable & (~cmd_cnt_end))
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    addr_len_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_len_cnt <= #1 'h0;
  else if (enable & cmd_cnt_end & (~addr_len_cnt_end))
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (enable & cmd_cnt_end & (~data_cnt_end))
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
wire byte, half, long;
reg byte_q, half_q, long_q;
 
 
assign byte = data_cnt[2:0] == 3'h0;
assign half = data_cnt[3:0] == 4'h0;
assign long = data_cnt[4:0] == 5'h0;
 
 
always @ (posedge tck_i)
begin
  byte_q <= #1 byte;
  half_q <= #1 half;
  long_q <= #1 long;
end
 
 
 
reg cmd_write;
reg cmd_read;
reg cmd_go;
 
//wire previous_cmd_read;
wire previous_cmd_write;
//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
 
reg [2:0] cmd_new;
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cmd_new  <= #1 3'h0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_new <= #1 dr[2:0];
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cmd_read  <= #1 1'b0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_read <= #1 (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cmd_write  <= #1 1'b0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_write <= #1 (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    cmd_go  <= #1 1'b0;
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    cmd_go <= #1 (dr[2:0] == `WB_GO);
end
 
 
 
 
 
always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
begin
  if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      // (current command is WB_STATUS or WB_GO)
      if ( (dr[2:0] == `WB_STATUS) | (dr[2:0] == `WB_GO) )
        addr_len_cnt_limit = 6'd0;
      // (current command is WB_WRITEx or WB_READx)
      else
        addr_len_cnt_limit = 6'd48;
    end
end
 
 
 
always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
begin
  if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      // (current command is WB_GO and previous command is WB_WRITEx)
      if ( (dr[2:0] == `WB_GO) & previous_cmd_write )
        data_cnt_limit = (len<<3);
      else
        data_cnt_limit = 19'h0;
    end
end
 
 
 
`define WB_STATUS     3'h0
`define WB_WRITE8     3'h1
`define WB_WRITE16    3'h2
`define WB_WRITE32    3'h3
`define WB_GO         3'h4
`define WB_READ8      3'h5
`define WB_READ16     3'h6
`define WB_READ32     3'h7
 
 
 
 
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
//  else if(enable & addr_len_cnt_end & (~crc_cnt_end))
  else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign data_cnt_end = data_cnt == data_cnt_limit;
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q <= #1 crc_cnt_end;
  cmd_cnt_end_q <= #1 cmd_cnt_end;
end
 
// status counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt <= #1 'h0;
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
    status_cnt <= #1 'h0;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
reg [`STATUS_LEN -1:0] status;
//reg address_unaligned;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
 
reg busy_wb;
reg busy_tck;
reg wb_end;
reg wb_end_rst;
reg wb_end_rst_sync;
reg wb_end_sync;
reg wb_end_tck;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status <= #1 'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if overrun occured during write (data couldn't be written fast enough)
// 4. bit:          1 if WB error occured, else 0
 
 
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
    end
  else if (crc_cnt_end & (~crc_cnt_end_q))
    begin
      tdo_o = crc_match_i;
      TDO_WISHBONE = "crc_match_i";
    end
  else if (crc_cnt_end)
    begin
      tdo_o = status[0];
      TDO_WISHBONE = "status";
    end
  else
    begin
      tdo_o = 1'b0;
      TDO_WISHBONE = "zero while CRC is shifted in";
    end
end
 
assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
 
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (cmd_write | cmd_read)
        begin
          cmd <= #1 dr[50:48];
          adr <= #1 dr[47:16];
          len <= #1 dr[15:0];
          set_addr <= #1 1'b1;
        end
      else
        begin
          cmd <= #1 dr[2:0];
        end
 
      cmd_old <= #1 cmd;
    end
  else
    set_addr <= #1 1'b0;
end
 
 
always @ (posedge tck_i)
begin
  if (cmd_go & previous_cmd_write)
    begin
      case (cmd)  // synthesis parallel_case full_case
        `WB_WRITE8  : begin
                        if (byte & (~byte_q))
                          begin
                            start_tck <= #1 1'b1;
                            wb_dat_o <= #1 {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE16 : begin
                        if (half & (~half_q))
                          begin
                            start_tck <= #1 1'b1;
                            wb_dat_o <= #1 {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE32 : begin
                        if (long & (~long_q))
                          begin
                            start_tck <= #1 1'b1;
                            wb_dat_o <= #1 dr[31:0];
                          end
                        else
                          begin
                            start_tck <= #1 1'b0;
                          end
                      end
      endcase
    end
  else
    start_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_sync1 <= #1 start_tck;
  start_wb <= #1 start_sync1;
  start_wb_q <= #1 start_wb;
  set_addr_sync <= #1 set_addr;
  set_addr_wb <= #1 set_addr_sync;
  set_addr_wb_q <= #1 set_addr_wb;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_cyc_o <= #1 1'b0;
  else if (start_wb & (~start_wb_q))
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
  if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((cmd_new == `WB_WRITE8) | (cmd == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((cmd_new == `WB_WRITE16) | (cmd == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
//    adr   byte  |  short  |  long
//     0    1000     1100      1111
//     1    0100     err       err
//     2    0010     0011      err
//     3    0001     err       err
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    begin
      wb_sel_o[3:0] <= #1 4'h0;
    end
  else
    begin
      wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                        (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
      wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
    end
end
 
 
 
 
/*
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_dat_o[31:0] <= #1 32'h0;
  else if (start_wb & (~start_wb_q))
    begin
      if (cmd[1:0] == 2'd1)                       // 8-bit access
        wb_dat_o[31:0] <= #1 {4{8'h0}};
      else if (cmd[1:0] == 2'd2)                  // 16-bit access
        wb_dat_o[31:0] <= #1 {2{16'h0}};
      else
        wb_dat_o[31:0] <= #1 32'h0;               //32-bit access
    end
end
*/
 
//always @ (wb_adr_o or cmd)
//begin
//  wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) | 
//                (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
//  wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
//  wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
//  wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
//end
 
 
 
// always @ (dr)
// begin
//   address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
// end
 
 
 
assign wb_we_o = ~cmd[2];   // Status or write (for simpler logic status is allowed)
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
reg [31:0] input_data;
 
always @ (posedge wb_clk_i)
begin
  if(wb_ack_i)
    input_data <= #1 wb_dat_i;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
    end
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_overrun <= #1 1'b0;
  else if(start_wb & (~start_wb_q) & wb_cyc_o)
    wb_overrun <= #1 1'b1;
  else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
    wb_overrun <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_overrun_sync <= #1 wb_overrun;
  wb_overrun_tck  <= #1 wb_overrun_sync;
end
 
 
 
 
 
 
// wb_error is locked until WB_STATUS is performed
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_reset_en <= 1'b0;
  else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
    status_reset_en <= #1 1'b1;
  else
    status_reset_en <= #1 1'b0;
end
 
 
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	88	mohor	`// Revision 1.4 2004/01/05 12:16:00 mohor`
47			`// tmp2 version.`
48			`//`
49	87	mohor	`// Revision 1.3 2003/12/23 16:22:46 mohor`
50			`// Tmp version.`
51			`//`
52	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
53			`// Small fix.`
54			`//`
55	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
56			`// New directory structure. New version of the debug interface.`
57	82	mohor	`//`
58			`//`
59	83	mohor	`//`
60	82	mohor
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "dbg_wb_defines.v"
65
66			`// Top module`
67			`module dbg_wb(`
68			`// JTAG signals`
69			`trst_i, // trst_i is active high (inverted on higher layers)`
70			`tck_i,`
71			`tdi_i,`
72			`tdo_o,`
73
74			`// TAP states`
75			`shift_dr_i,`
76			`pause_dr_i,`
77			`update_dr_i,`
78
79			`wishbone_ce_i,`
80			`crc_match_i,`
81			`crc_en_o,`
82			`shift_crc_o,`
83
84			`// WISHBONE common signals`
85			`wb_rst_i, wb_clk_i,`
86
87			`// WISHBONE master interface`
88			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
89			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
90
91			`);`
92
93			`// JTAG signals`
94			`input trst_i;`
95			`input tck_i;`
96			`input tdi_i;`
97			`output tdo_o;`
98
99			`// TAP states`
100			`input shift_dr_i;`
101			`input pause_dr_i;`
102			`input update_dr_i;`
103
104			`input wishbone_ce_i;`
105			`input crc_match_i;`
106			`output crc_en_o;`
107			`output shift_crc_o;`
108
109			`// WISHBONE common signals`
110			`input wb_rst_i; // WISHBONE reset`
111			`input wb_clk_i; // WISHBONE clock`
112
113			`// WISHBONE master interface`
114			`output [31:0] wb_adr_o;`
115			`output [31:0] wb_dat_o;`
116			`input [31:0] wb_dat_i;`
117			`output wb_cyc_o;`
118			`output wb_stb_o;`
119			`output [3:0] wb_sel_o;`
120			`output wb_we_o;`
121			`input wb_ack_i;`
122			`output wb_cab_o;`
123			`input wb_err_i;`
124			`output [2:0] wb_cti_o;`
125			`output [1:0] wb_bte_o;`
126
127			`reg wb_cyc_o;`
128			`reg [31:0] wb_adr_o;`
129	88	mohor	`reg [31:0] wb_dat_o;`
130	82	mohor	`reg [3:0] wb_sel_o;`
131
132			`reg tdo_o;`
133
134	88	mohor	`reg [50:0] dr;`
135			`wire enable;`
136			`reg [1:0] cmd_cnt;`
137			`wire cmd_cnt_end;`
138			`reg cmd_cnt_end_q;`
139			`reg [5:0] addr_len_cnt;`
140			`reg [5:0] addr_len_cnt_limit;`
141			`wire addr_len_cnt_end;`
142			`reg [5:0] crc_cnt;`
143			`wire crc_cnt_end;`
144			`reg crc_cnt_end_q;`
145			`reg [18:0] data_cnt;`
146			`reg [18:0] data_cnt_limit;`
147			`wire data_cnt_end;`
148			`reg status_reset_en;`
149	82	mohor
150
151			reg [`STATUS_CNT -1:0] status_cnt;
152	88	mohor	`// reg [31:0] data_tck;`
153
154
155			`reg [2:0] cmd, cmd_old;`
156			`reg [31:0] adr;`
157			`reg [15:0] len;`
158			`reg start_tck;`
159			`reg start_sync1;`
160			`reg start_wb;`
161			`reg start_wb_q;`
162
163
164	82	mohor	`wire status_cnt_end;`
165
166			`assign enable = wishbone_ce_i & shift_dr_i;`
167			`assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC`
168
169
170			`always @ (posedge tck_i)`
171			`begin`
172	88	mohor	`// if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end)))`
173			`if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end) \| (~data_cnt_end)))`
174			`dr <= #1 {dr[49:0], tdi_i};`
175	82	mohor	`end`
176
177
178	88	mohor	`//always @ (posedge tck_i)`
179			`//begin`
180			`// if (enable & (data_cnt_end)) // Igor !!! perhaps not needed data_cnt_end`
181			`// data_tck <= #1 {data_tck[30:0], tdi_i};`
182			`//end`
183
184
185	82	mohor	`always @ (posedge tck_i or posedge trst_i)`
186			`begin`
187			`if (trst_i)`
188	87	mohor	`cmd_cnt <= #1 'h0;`
189	82	mohor	`else if (update_dr_i)`
190	87	mohor	`cmd_cnt <= #1 'h0;`
191			`else if (enable & (~cmd_cnt_end))`
192			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
193	82	mohor	`end`
194
195
196	87	mohor	`always @ (posedge tck_i or posedge trst_i)`
197			`begin`
198			`if (trst_i)`
199	88	mohor	`addr_len_cnt <= #1 'h0;`
200			`else if (update_dr_i)`
201			`addr_len_cnt <= #1 'h0;`
202			`else if (enable & cmd_cnt_end & (~addr_len_cnt_end))`
203			`addr_len_cnt <= #1 addr_len_cnt + 1'b1;`
204			`end`
205
206
207			`always @ (posedge tck_i or posedge trst_i)`
208			`begin`
209			`if (trst_i)`
210	87	mohor	`data_cnt <= #1 'h0;`
211			`else if (update_dr_i)`
212			`data_cnt <= #1 'h0;`
213			`else if (enable & cmd_cnt_end & (~data_cnt_end))`
214			`data_cnt <= #1 data_cnt + 1'b1;`
215			`end`
216	82	mohor
217	87	mohor
218	88	mohor	`wire byte, half, long;`
219			`reg byte_q, half_q, long_q;`
220
221
222			`assign byte = data_cnt[2:0] == 3'h0;`
223			`assign half = data_cnt[3:0] == 4'h0;`
224			`assign long = data_cnt[4:0] == 5'h0;`
225
226
227			`always @ (posedge tck_i)`
228			`begin`
229			`byte_q <= #1 byte;`
230			`half_q <= #1 half;`
231			`long_q <= #1 long;`
232			`end`
233
234
235
236			`reg cmd_write;`
237			`reg cmd_read;`
238			`reg cmd_go;`
239
240			`//wire previous_cmd_read;`
241			`wire previous_cmd_write;`
242			//assign previous_cmd_read = (cmd == `WB_READ8) \| (cmd == `WB_READ16) \| (cmd == `WB_READ32);
243			assign previous_cmd_write = (cmd == `WB_WRITE8) \| (cmd == `WB_WRITE16) \| (cmd == `WB_WRITE32);
244
245			`reg [2:0] cmd_new;`
246
247			`always @ (posedge tck_i or posedge trst_i)`
248			`begin`
249			`if (trst_i)`
250			`cmd_new <= #1 3'h0;`
251			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
252			`cmd_new <= #1 dr[2:0];`
253			`end`
254
255
256			`always @ (posedge tck_i)`
257			`begin`
258			`if (update_dr_i)`
259			`cmd_read <= #1 1'b0;`
260			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
261			cmd_read <= #1 (dr[2:0] == `WB_READ8) \| (dr[2:0] == `WB_READ16) \| (dr[2:0] == `WB_READ32);
262			`end`
263
264
265			`always @ (posedge tck_i)`
266			`begin`
267			`if (update_dr_i)`
268			`cmd_write <= #1 1'b0;`
269			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
270			cmd_write <= #1 (dr[2:0] == `WB_WRITE8) \| (dr[2:0] == `WB_WRITE16) \| (dr[2:0] == `WB_WRITE32);
271			`end`
272
273
274			`always @ (posedge tck_i)`
275			`begin`
276			`if (update_dr_i)`
277			`cmd_go <= #1 1'b0;`
278			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
279			cmd_go <= #1 (dr[2:0] == `WB_GO);
280			`end`
281
282
283
284
285
286			`always @ (cmd_cnt_end or cmd_cnt_end_q or dr)`
287			`begin`
288			`if (cmd_cnt_end & (~cmd_cnt_end_q))`
289			`begin`
290			`// (current command is WB_STATUS or WB_GO)`
291			if ( (dr[2:0] == `WB_STATUS) \| (dr[2:0] == `WB_GO) )
292			`addr_len_cnt_limit = 6'd0;`
293			`// (current command is WB_WRITEx or WB_READx)`
294			`else`
295			`addr_len_cnt_limit = 6'd48;`
296			`end`
297			`end`
298
299
300
301			`always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)`
302			`begin`
303			`if (cmd_cnt_end & (~cmd_cnt_end_q))`
304			`begin`
305			`// (current command is WB_GO and previous command is WB_WRITEx)`
306			if ( (dr[2:0] == `WB_GO) & previous_cmd_write )
307			`data_cnt_limit = (len<<3);`
308			`else`
309			`data_cnt_limit = 19'h0;`
310			`end`
311			`end`
312
313
314
315			`define WB_STATUS 3'h0
316			`define WB_WRITE8 3'h1
317			`define WB_WRITE16 3'h2
318			`define WB_WRITE32 3'h3
319			`define WB_GO 3'h4
320			`define WB_READ8 3'h5
321			`define WB_READ16 3'h6
322			`define WB_READ32 3'h7
323
324
325
326
327
328	82	mohor	`// crc counter`
329			`always @ (posedge tck_i or posedge trst_i)`
330			`begin`
331			`if (trst_i)`
332			`crc_cnt <= #1 'h0;`
333	88	mohor	`// else if(enable & addr_len_cnt_end & (~crc_cnt_end))`
334			`else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))`
335	82	mohor	`crc_cnt <= #1 crc_cnt + 1'b1;`
336			`else if (update_dr_i)`
337			`crc_cnt <= #1 'h0;`
338			`end`
339
340	87	mohor	`assign cmd_cnt_end = cmd_cnt == 2'h3;`
341	88	mohor	`//assign addr_len_cnt_end = addr_len_cnt == 6'd48;`
342			`assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;`
343	87	mohor	`assign crc_cnt_end = crc_cnt == 6'd32;`
344	88	mohor	`assign data_cnt_end = data_cnt == data_cnt_limit;`
345	82	mohor
346			`always @ (posedge tck_i)`
347			`begin`
348			`crc_cnt_end_q <= #1 crc_cnt_end;`
349	88	mohor	`cmd_cnt_end_q <= #1 cmd_cnt_end;`
350	82	mohor	`end`
351
352			`// status counter`
353			`always @ (posedge tck_i or posedge trst_i)`
354			`begin`
355			`if (trst_i)`
356			`status_cnt <= #1 'h0;`
357			`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
358			`status_cnt <= #1 status_cnt + 1'b1;`
359			`else if (update_dr_i)`
360			`status_cnt <= #1 'h0;`
361			`end`
362
363			assign status_cnt_end = status_cnt == `STATUS_LEN;
364			reg [`STATUS_LEN -1:0] status;
365	88	mohor	`//reg address_unaligned;`
366	82	mohor
367			`reg wb_error, wb_error_sync, wb_error_tck;`
368	88	mohor	`reg wb_overrun, wb_overrun_sync, wb_overrun_tck;`
369	82	mohor
370	86	mohor	`reg busy_wb;`
371			`reg busy_tck;`
372			`reg wb_end;`
373			`reg wb_end_rst;`
374			`reg wb_end_rst_sync;`
375			`reg wb_end_sync;`
376			`reg wb_end_tck;`
377			`reg busy_sync;`
378			`reg [799:0] TDO_WISHBONE;`
379	82	mohor
380			`always @ (posedge tck_i or posedge trst_i)`
381			`begin`
382			`if (trst_i)`
383			`status <= #1 'h0;`
384			`else if(crc_cnt_end & (~crc_cnt_end_q))`
385	88	mohor	`status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,`
386	82	mohor	`else if (shift_dr_i & (~status_cnt_end))`
387			status <= #1 {status[0], status[`STATUS_LEN -1:1]};
388			`end`
389	88	mohor	`// Following status is shifted out:`
390	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
391	86	mohor	`// 2. bit: 1 while WB access is in progress (busy_tck), else 0`
392	88	mohor	`// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)`
393	82	mohor	`// 4. bit: 1 if WB error occured, else 0`
394
395
396	88	mohor
397	82	mohor	`always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)`
398			`begin`
399			`if (pause_dr_i)`
400	87	mohor	`begin`
401	82	mohor	`tdo_o = busy_tck;`
402			`TDO_WISHBONE = "busy_tck";`
403	87	mohor	`end`
404	82	mohor	`else if (crc_cnt_end & (~crc_cnt_end_q))`
405	87	mohor	`begin`
406			`tdo_o = crc_match_i;`
407			`TDO_WISHBONE = "crc_match_i";`
408			`end`
409			`else if (crc_cnt_end)`
410			`begin`
411			`tdo_o = status[0];`
412			`TDO_WISHBONE = "status";`
413			`end`
414	82	mohor	`else`
415	87	mohor	`begin`
416			`tdo_o = 1'b0;`
417			`TDO_WISHBONE = "zero while CRC is shifted in";`
418			`end`
419	82	mohor	`end`
420
421			`assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;`
422
423	88	mohor	`reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;`
424	82	mohor
425			`always @ (posedge tck_i)`
426			`begin`
427			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
428			`begin`
429	88	mohor	`if (cmd_write \| cmd_read)`
430			`begin`
431			`cmd <= #1 dr[50:48];`
432			`adr <= #1 dr[47:16];`
433			`len <= #1 dr[15:0];`
434			`set_addr <= #1 1'b1;`
435			`end`
436			`else`
437			`begin`
438			`cmd <= #1 dr[2:0];`
439			`end`
440
441	87	mohor	`cmd_old <= #1 cmd;`
442	82	mohor	`end`
443			`else`
444	88	mohor	`set_addr <= #1 1'b0;`
445			`end`
446
447
448			`always @ (posedge tck_i)`
449			`begin`
450			`if (cmd_go & previous_cmd_write)`
451			`begin`
452			`case (cmd) // synthesis parallel_case full_case`
453			`WB_WRITE8 : begin
454			`if (byte & (~byte_q))`
455			`begin`
456			`start_tck <= #1 1'b1;`
457			`wb_dat_o <= #1 {4{dr[7:0]}};`
458			`end`
459			`else`
460			`begin`
461			`start_tck <= #1 1'b0;`
462			`end`
463			`end`
464			`WB_WRITE16 : begin
465			`if (half & (~half_q))`
466			`begin`
467			`start_tck <= #1 1'b1;`
468			`wb_dat_o <= #1 {2{dr[15:0]}};`
469			`end`
470			`else`
471			`begin`
472			`start_tck <= #1 1'b0;`
473			`end`
474			`end`
475			`WB_WRITE32 : begin
476			`if (long & (~long_q))`
477			`begin`
478			`start_tck <= #1 1'b1;`
479			`wb_dat_o <= #1 dr[31:0];`
480			`end`
481			`else`
482			`begin`
483			`start_tck <= #1 1'b0;`
484			`end`
485			`end`
486			`endcase`
487			`end`
488			`else`
489	82	mohor	`start_tck <= #1 1'b0;`
490			`end`
491
492
493			`always @ (posedge wb_clk_i)`
494			`begin`
495			`start_sync1 <= #1 start_tck;`
496			`start_wb <= #1 start_sync1;`
497			`start_wb_q <= #1 start_wb;`
498	88	mohor	`set_addr_sync <= #1 set_addr;`
499			`set_addr_wb <= #1 set_addr_sync;`
500			`set_addr_wb_q <= #1 set_addr_wb;`

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