URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 95

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2004/01/14 12:29:40  mohor
// temp version. Resets will be changed in next version.
//
// Revision 1.10  2004/01/13 11:28:14  mohor
// tmp version.
//
// Revision 1.9  2004/01/10 07:50:24  mohor
// temp version.
//
// Revision 1.8  2004/01/09 12:48:44  mohor
// tmp version.
//
// Revision 1.7  2004/01/08 17:53:36  mohor
// tmp version.
//
// Revision 1.6  2004/01/07 11:58:56  mohor
// temp4 version.
//
// Revision 1.5  2004/01/06 17:15:19  mohor
// temp3 version.
//
// Revision 1.4  2004/01/05 12:16:00  mohor
// tmp2 version.
//
// Revision 1.3  2003/12/23 16:22:46  mohor
// Tmp version.
//
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
 
                // WISHBONE common signals
                wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
input   rst_i;
// WISHBONE common signals
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg    [31:0] wb_dat_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg    [50:0] dr;
wire          enable;
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_len_cnt_en;
reg     [5:0] addr_len_cnt;
reg     [5:0] addr_len_cnt_limit;
wire          addr_len_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg    [18:0] data_cnt;
reg    [18:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
reg           status_reset_en;
 
reg           crc_match_reg;
 
reg     [2:0] cmd, cmd_old, dr_cmd_latched;
reg    [31:0] adr;
reg    [15:0] len;
reg           start_rd_tck;
reg           start_rd_sync1;
reg           start_wb_rd;
reg           start_wb_rd_q;
reg           start_wr_tck;
reg           start_wr_sync1;
reg           start_wb_wr;
reg           start_wb_wr_q;
 
wire          dr_read;
wire          dr_write;
wire          dr_go;
 
reg           dr_write_latched;
reg           dr_read_latched;
reg           dr_go_latched;
 
wire          status_cnt_end;
 
wire          byte, half, long;
reg           byte_q, half_q, long_q;
reg           byte_q2, half_q2, long_q2;
reg           cmd_read;
reg           cmd_write;
reg           cmd_go;
 
reg           status_cnt1, status_cnt2, status_cnt3, status_cnt4;
 
reg [`STATUS_LEN -1:0] status;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
 
reg busy_wb;
reg busy_tck;
reg wb_end;
reg wb_end_rst;
reg wb_end_rst_sync;
reg wb_end_sync;
reg wb_end_tck, wb_end_tck_q;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
reg [399:0] latching_data;
 
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
reg read_cycle;
reg write_cycle;
reg [2:0] rw_type;
wire [31:0] input_data;
 
wire len_eq_0;
wire crc_cnt_31;
 
assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
reg [1:0] ptr;
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    ptr <= #1 2'h0;
  else if (read_cycle & crc_cnt_31) // first latch
    ptr <= #1 ptr + 1'b1;
  else if (read_cycle & byte & (~byte_q))
    ptr <= ptr + 1'd1;
end
 
 
 
always @ (posedge tck_i)
begin
  if (read_cycle & crc_cnt_31)
    begin
      dr[31:0] <= #1 input_data[31:0];
      latching_data = "First latch";
    end
  else if (read_cycle & crc_cnt_end)
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : begin
                      if(byte & (~byte_q))
                        begin
                          case (ptr)    // synthesis parallel_case
                            2'b00 : dr[31:24] <= #1 input_data[31:24];
                            2'b01 : dr[31:24] <= #1 input_data[23:16];
                            2'b10 : dr[31:24] <= #1 input_data[15:8];
                            2'b11 : dr[31:24] <= #1 input_data[7:0];
                          endcase
                          latching_data = "8 bit latched";
                        end
                      else
                        begin
                          dr[31:24] <= #1 {dr[30:24], 1'b0};
                          latching_data = "8 bit shifted";
                        end
                    end
        `WB_READ16: begin
                      if(half & (~half_q))
                        begin
                          if (ptr[1])
                            dr[31:16] <= #1 input_data[31:16];
                          else
                            dr[31:16] <= #1 input_data[15:0];
                          latching_data = "16 bit latched";
                        end
                      else
                        begin
                          dr[31:16] <= #1 {dr[30:16], 1'b0};
                          latching_data = "16 bit shifted";
                        end
                    end
        `WB_READ32: begin
                      if(long & (~long_q))
                        begin
                          dr[31:0] <= #1 input_data[31:0];
                          latching_data = "32 bit latched";
                        end
                      else
                        begin
                          dr[31:0] <= #1 {dr[30:0], 1'b0};
                          latching_data = "32 bit shifted";
                        end
                    end
      endcase
    end
  else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
    begin
    dr <= #1 {dr[49:0], tdi_i};
    latching_data = "tdi shifted in";
    end
  else
    latching_data = "nothing";
end
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_len_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_len_cnt <= #1 'h0;
  else if (addr_len_cnt_en)
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
 
assign byte = data_cnt[2:0] == 3'd7;
assign half = data_cnt[3:0] == 4'd15;
assign long = data_cnt[4:0] == 5'd31;
 
 
always @ (posedge tck_i)
begin
  byte_q <= #1 byte;
  half_q <= #1 half;
  long_q <= #1 long;
  byte_q2 <= #1 byte_q;
  half_q2 <= #1 half_q;
  long_q2 <= #1 long_q;
end
 
 
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
assign dr_go = dr[2:0] == `WB_GO;
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    begin
      dr_cmd_latched = 3'h0;
      dr_read_latched  <= #1 1'b0;
      dr_write_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_cmd_latched = dr[2:0];
      dr_read_latched <= #1 dr_read;
      dr_write_latched <= #1 dr_write;
      dr_go_latched <= #1 dr_go;
    end
end
 
 
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))                                   // (current command is WB_STATUS or WB_GO)
        addr_len_cnt_limit = 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_len_cnt_limit = 6'd48;
    end
end
 
 
wire go_prelim;
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    data_cnt_limit = {len, 3'b000};
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end  & (~write_cycle) | (data_cnt_end & write_cycle));
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <= #1 'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign crc_cnt_31 = crc_cnt  == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q  <= #1 crc_cnt_end;
  cmd_cnt_end_q  <= #1 cmd_cnt_end;
  data_cnt_end_q <= #1 data_cnt_end;
end
 
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & read_cycle |
           crc_cnt_end & (~read_cycle)
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
assign status_cnt_end = status_cnt4;
 
reg [199:0] status_text;
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
    status <= #1 'h0;
    status_text <= #1 "reset";
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
    begin
    status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
    status_text <= #1 "!!!READ";
    end
  else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
    begin
    status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
    status_text <= #1 "READ";
    end
  else if (shift_dr_i & (~status_cnt_end))
    begin
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
    status_text <= #1 "shift";
    end
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if overrun occured during write (data couldn't be written fast enough)
// 4. bit:          1 if WB error occured, else 0
 
 
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or cmd_read or crc_match_i or
          data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr or cmd_go)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
    end
  else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
    begin
      tdo_o = crc_match_i;
      TDO_WISHBONE = "crc_match_i";
    end
  else if (read_cycle & crc_cnt_end & (~data_cnt_end))
    begin
    tdo_o = dr[31];
    TDO_WISHBONE = "read data";
    end
  else if (read_cycle & data_cnt_end & (~data_cnt_end_q))     // cmd is already updated
    begin
      tdo_o = crc_match_reg;
      TDO_WISHBONE = "crc_match_reg";
    end
  else if (crc_cnt_end & data_cnt_end)  // cmd is already updated
    begin
      tdo_o = status[0];
      TDO_WISHBONE = "status";
    end
  else
    begin
      tdo_o = 1'b0;
      TDO_WISHBONE = "zero while CRC is shifted in";
    end
end
 
 
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <= #1 crc_match_i;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cmd <= #1 'h0;
      cmd_old <= #1 'h0;
      cmd_read <= #1 1'b0;
      cmd_write <= #1 1'b0;
      cmd_go <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd <= #1 dr_cmd_latched;
      cmd_old <= #1 cmd;
      cmd_read <= #1 dr_read_latched;
      cmd_write <= #1 dr_write_latched;
      cmd_go <= #1 dr_go_latched;
    end
end
 
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (dr_write_latched | dr_read_latched)
        begin
          adr <= #1 dr[47:16];
          set_addr <= #1 1'b1;
        end
    end
  else
    set_addr <= #1 1'b0;
end
 
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
    len <= #1 dr[15:0];
//  else if (wb_end_tck & (~wb_end_tck_q))
  else if (start_rd_tck)
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : len <= #1 len - 1'd1;
        `WB_READ16: len <= #1 len - 2'd2;
        `WB_READ32: len <= #1 len - 3'd4;
      endcase
    end
end
 
 
assign len_eq_0 = len == 16'h0;
 
 
// Start wishbone read cycle
always @ (posedge tck_i)
begin
  if (read_cycle & (~dr_go_latched) & (~len_eq_0))              // First read after cmd is entered
    start_rd_tck <= #1 1'b1;
  else if (read_cycle & crc_cnt_31 & (~len_eq_0))               // Second read after first data is latched
    start_rd_tck <= #1 1'b1;
  else if (read_cycle & (~len_eq_0))
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_READ8 : begin
                      if(byte & (~byte_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
        `WB_READ16: begin
                      if(half & (~half_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
        `WB_READ32: begin
                      if(long & (~long_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
      endcase
    end
  else
    start_rd_tck <= #1 1'b0;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle <= #1 1'b0;
  else if (cmd_read & go_prelim)
    read_cycle <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if ((cmd_read | cmd_write) & go_prelim)
    rw_type <= #1 cmd;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle <= #1 1'b0;
  else if (cmd_write & go_prelim)
    write_cycle <= #1 1'b1;
end
 
 
// Start wishbone write cycle
always @ (posedge tck_i)
begin
  if (write_cycle)
    begin
      case (rw_type)  // synthesis parallel_case full_case
        `WB_WRITE8  : begin
                        if (byte_q & (~byte_q2))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE16 : begin
                        if (half_q & (~half_q2))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE32 : begin
                        if (long_q & (~long_q2))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 dr[31:0];
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
      endcase
    end
  else
    start_wr_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_rd_sync1  <= #1 start_rd_tck;
  start_wb_rd     <= #1 start_rd_sync1;
  start_wb_rd_q   <= #1 start_wb_rd;
 
  start_wr_sync1  <= #1 start_wr_tck;
  start_wb_wr     <= #1 start_wr_sync1;
  start_wb_wr_q   <= #1 start_wb_wr;
 
  set_addr_sync   <= #1 set_addr;
  set_addr_wb     <= #1 set_addr_sync;
  set_addr_wb_q   <= #1 set_addr_wb;
end
 
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_cyc_o <= #1 1'b0;
  else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
  if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((rw_type == `WB_WRITE16) | (rw_type == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
 
//    adr   byte  |  short  |  long
//     0    1000     1100      1111
//     1    0100     err       err
//     2    0010     0011      err
//     3    0001     err       err
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_sel_o[3:0] <= #1 4'h0;
  else
    begin
      wb_sel_o[0] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                        (rw_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[1] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1] ^ rw_type[0]) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[2] <= #1 (rw_type[1]) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
      wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
    end
end
 
 
assign wb_we_o = write_cycle;
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
      wb_end_tck_q<= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
      wb_end_tck_q<= #1 wb_end_tck;
    end
end
 
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
 
always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_overrun <= #1 1'b0;
  else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
    wb_overrun <= #1 1'b1;
  else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
    wb_overrun <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_overrun_sync <= #1 wb_overrun;
  wb_overrun_tck  <= #1 wb_overrun_sync;
end
 
 
 
 
 
 
// wb_error is locked until WB_STATUS is performed
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_reset_en <= 1'b0;
  else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
    status_reset_en <= #1 1'b1;
  else
    status_reset_en <= #1 1'b0;
end
 
 
reg [7:0] mem [0:3];
reg [2:0] mem_ptr;
reg wishbone_ce_sync;
reg wishbone_ce_rst;
 
always @ (posedge wb_clk_i)
begin
  wishbone_ce_sync <= #1  wishbone_ce_i;
  wishbone_ce_rst  <= #1 ~wishbone_ce_sync;
end
 
 
always @ (posedge wb_clk_i)
begin
  if(wishbone_ce_rst)
    mem_ptr <= #1 'h0;
  else if (wb_ack_i)
    begin
      if (rw_type == `WB_READ8)
        mem_ptr <= #1 mem_ptr + 1'd1;
      else if (rw_type == `WB_READ16)
        mem_ptr <= #1 mem_ptr + 2'd2;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  if (wb_ack_i)
    begin
      case (wb_sel_o)    // synthesis parallel_case full_case 
        4'b1000  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24];            // byte 
        4'b0100  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16];            // byte
        4'b0010  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08];            // byte
        4'b0001  :  mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:00];            // byte
 
        4'b1100  :                                                      // half
                    begin
                      mem[mem_ptr[1:0]]      <= #1 wb_dat_i[31:24];
                      mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16];
                    end
        4'b0011  :                                                      // half
                    begin
                      mem[mem_ptr[1:0]]      <= #1 wb_dat_i[15:08];
                      mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:00];
                    end
        4'b1111  :                                                      // long
                    begin
                      mem[0] <= #1 wb_dat_i[31:24];
                      mem[1] <= #1 wb_dat_i[23:16];
                      mem[2] <= #1 wb_dat_i[15:08];
                      mem[3] <= #1 wb_dat_i[07:00];
                    end
      endcase
    end
end
 
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	95	mohor	`// Revision 1.11 2004/01/14 12:29:40 mohor`
47			`// temp version. Resets will be changed in next version.`
48			`//`
49	94	mohor	`// Revision 1.10 2004/01/13 11:28:14 mohor`
50			`// tmp version.`
51			`//`
52	93	mohor	`// Revision 1.9 2004/01/10 07:50:24 mohor`
53			`// temp version.`
54			`//`
55	92	mohor	`// Revision 1.8 2004/01/09 12:48:44 mohor`
56			`// tmp version.`
57			`//`
58	91	mohor	`// Revision 1.7 2004/01/08 17:53:36 mohor`
59			`// tmp version.`
60			`//`
61	90	mohor	`// Revision 1.6 2004/01/07 11:58:56 mohor`
62			`// temp4 version.`
63			`//`
64	89	mohor	`// Revision 1.5 2004/01/06 17:15:19 mohor`
65			`// temp3 version.`
66			`//`
67	88	mohor	`// Revision 1.4 2004/01/05 12:16:00 mohor`
68			`// tmp2 version.`
69			`//`
70	87	mohor	`// Revision 1.3 2003/12/23 16:22:46 mohor`
71			`// Tmp version.`
72			`//`
73	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
74			`// Small fix.`
75			`//`
76	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
77			`// New directory structure. New version of the debug interface.`
78	82	mohor	`//`
79			`//`
80	83	mohor	`//`
81	82	mohor
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "dbg_wb_defines.v"
86
87			`// Top module`
88			`module dbg_wb(`
89			`// JTAG signals`
90			`tck_i,`
91			`tdi_i,`
92			`tdo_o,`
93
94			`// TAP states`
95			`shift_dr_i,`
96			`pause_dr_i,`
97			`update_dr_i,`
98
99			`wishbone_ce_i,`
100			`crc_match_i,`
101			`crc_en_o,`
102			`shift_crc_o,`
103	95	mohor	`rst_i,`
104	82	mohor
105			`// WISHBONE common signals`
106	95	mohor	`wb_clk_i,`
107	82	mohor
108			`// WISHBONE master interface`
109			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
110			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
111
112			`);`
113
114			`// JTAG signals`
115			`input tck_i;`
116			`input tdi_i;`
117			`output tdo_o;`
118
119			`// TAP states`
120			`input shift_dr_i;`
121			`input pause_dr_i;`
122			`input update_dr_i;`
123
124			`input wishbone_ce_i;`
125			`input crc_match_i;`
126			`output crc_en_o;`
127			`output shift_crc_o;`
128	95	mohor	`input rst_i;`
129	82	mohor	`// WISHBONE common signals`
130			`input wb_clk_i; // WISHBONE clock`
131
132			`// WISHBONE master interface`
133			`output [31:0] wb_adr_o;`
134			`output [31:0] wb_dat_o;`
135			`input [31:0] wb_dat_i;`
136			`output wb_cyc_o;`
137			`output wb_stb_o;`
138			`output [3:0] wb_sel_o;`
139			`output wb_we_o;`
140			`input wb_ack_i;`
141			`output wb_cab_o;`
142			`input wb_err_i;`
143			`output [2:0] wb_cti_o;`
144			`output [1:0] wb_bte_o;`
145
146			`reg wb_cyc_o;`
147			`reg [31:0] wb_adr_o;`
148	88	mohor	`reg [31:0] wb_dat_o;`
149	82	mohor	`reg [3:0] wb_sel_o;`
150
151			`reg tdo_o;`
152
153	88	mohor	`reg [50:0] dr;`
154			`wire enable;`
155	90	mohor	`wire cmd_cnt_en;`
156	88	mohor	`reg [1:0] cmd_cnt;`
157			`wire cmd_cnt_end;`
158			`reg cmd_cnt_end_q;`
159	90	mohor	`wire addr_len_cnt_en;`
160	88	mohor	`reg [5:0] addr_len_cnt;`
161			`reg [5:0] addr_len_cnt_limit;`
162			`wire addr_len_cnt_end;`
163	90	mohor	`wire crc_cnt_en;`
164	88	mohor	`reg [5:0] crc_cnt;`
165			`wire crc_cnt_end;`
166			`reg crc_cnt_end_q;`
167	90	mohor	`wire data_cnt_en;`
168	88	mohor	`reg [18:0] data_cnt;`
169			`reg [18:0] data_cnt_limit;`
170			`wire data_cnt_end;`
171	90	mohor	`reg data_cnt_end_q;`
172	88	mohor	`reg status_reset_en;`
173	82	mohor
174	90	mohor	`reg crc_match_reg;`
175	82	mohor
176	92	mohor	`reg [2:0] cmd, cmd_old, dr_cmd_latched;`
177			`reg [31:0] adr;`
178			`reg [15:0] len;`
179			`reg start_rd_tck;`
180			`reg start_rd_sync1;`
181			`reg start_wb_rd;`
182			`reg start_wb_rd_q;`
183			`reg start_wr_tck;`
184			`reg start_wr_sync1;`
185			`reg start_wb_wr;`
186			`reg start_wb_wr_q;`
187	88	mohor
188	92	mohor	`wire dr_read;`
189			`wire dr_write;`
190			`wire dr_go;`
191	88	mohor
192	92	mohor	`reg dr_write_latched;`
193			`reg dr_read_latched;`
194			`reg dr_go_latched;`
195	82	mohor
196	92	mohor	`wire status_cnt_end;`
197	89	mohor
198	92	mohor	`wire byte, half, long;`
199			`reg byte_q, half_q, long_q;`
200	94	mohor	`reg byte_q2, half_q2, long_q2;`
201	92	mohor	`reg cmd_read;`
202			`reg cmd_write;`
203			`reg cmd_go;`
204	90	mohor
205	92	mohor	`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
206	90	mohor
207	92	mohor	reg [`STATUS_LEN -1:0] status;
208
209			`reg wb_error, wb_error_sync, wb_error_tck;`
210			`reg wb_overrun, wb_overrun_sync, wb_overrun_tck;`
211
212			`reg busy_wb;`
213			`reg busy_tck;`
214			`reg wb_end;`
215			`reg wb_end_rst;`
216			`reg wb_end_rst_sync;`
217			`reg wb_end_sync;`
218	93	mohor	`reg wb_end_tck, wb_end_tck_q;`
219	92	mohor	`reg busy_sync;`
220			`reg [799:0] TDO_WISHBONE;`
221			`reg [399:0] latching_data;`
222
223			`reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;`
224			`reg read_cycle;`
225	94	mohor	`reg write_cycle;`
226	95	mohor	`reg [2:0] rw_type;`
227	92	mohor	`wire [31:0] input_data;`
228
229	93	mohor	`wire len_eq_0;`
230			`wire crc_cnt_31;`
231
232	82	mohor	`assign enable = wishbone_ce_i & shift_dr_i;`
233	90	mohor	`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
234	89	mohor	`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
235	82	mohor
236	93	mohor	`reg [1:0] ptr;`
237	82	mohor
238	90	mohor
239	82	mohor	`always @ (posedge tck_i)`
240			`begin`
241	93	mohor	`if (update_dr_i)`
242			`ptr <= #1 2'h0;`
243	95	mohor	`else if (read_cycle & crc_cnt_31) // first latch`
244	93	mohor	`ptr <= #1 ptr + 1'b1;`
245	95	mohor	`else if (read_cycle & byte & (~byte_q))`
246	93	mohor	`ptr <= ptr + 1'd1;`
247			`end`
248
249
250
251			`always @ (posedge tck_i)`
252			`begin`
253	95	mohor	`if (read_cycle & crc_cnt_31)`
254	90	mohor	`begin`
255	93	mohor	`dr[31:0] <= #1 input_data[31:0];`
256			`latching_data = "First latch";`
257			`end`
258			`else if (read_cycle & crc_cnt_end)`
259			`begin`
260	95	mohor	`case (rw_type) // synthesis parallel_case full_case`
261	90	mohor	`WB_READ8 : begin
262			`if(byte & (~byte_q))`
263	92	mohor	`begin`
264	93	mohor	`case (ptr) // synthesis parallel_case`
265			`2'b00 : dr[31:24] <= #1 input_data[31:24];`
266			`2'b01 : dr[31:24] <= #1 input_data[23:16];`
267			`2'b10 : dr[31:24] <= #1 input_data[15:8];`
268			`2'b11 : dr[31:24] <= #1 input_data[7:0];`
269			`endcase`
270			`latching_data = "8 bit latched";`
271	92	mohor	`end`
272	90	mohor	`else`
273	92	mohor	`begin`
274	93	mohor	`dr[31:24] <= #1 {dr[30:24], 1'b0};`
275			`latching_data = "8 bit shifted";`
276	92	mohor	`end`
277	90	mohor	`end`
278			`WB_READ16: begin
279			`if(half & (~half_q))`
280	92	mohor	`begin`
281	93	mohor	`if (ptr[1])`
282			`dr[31:16] <= #1 input_data[31:16];`
283			`else`
284			`dr[31:16] <= #1 input_data[15:0];`
285			`latching_data = "16 bit latched";`
286	92	mohor	`end`
287	90	mohor	`else`
288	92	mohor	`begin`
289	93	mohor	`dr[31:16] <= #1 {dr[30:16], 1'b0};`
290			`latching_data = "16 bit shifted";`
291	92	mohor	`end`
292	90	mohor	`end`
293			`WB_READ32: begin
294			`if(long & (~long_q))`
295	92	mohor	`begin`
296	93	mohor	`dr[31:0] <= #1 input_data[31:0];`
297			`latching_data = "32 bit latched";`
298	92	mohor	`end`
299	90	mohor	`else`
300	92	mohor	`begin`
301	93	mohor	`dr[31:0] <= #1 {dr[30:0], 1'b0};`
302			`latching_data = "32 bit shifted";`
303	92	mohor	`end`
304	90	mohor	`end`
305			`endcase`
306			`end`
307	94	mohor	`else if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle)))`
308	92	mohor	`begin`
309	88	mohor	`dr <= #1 {dr[49:0], tdi_i};`
310	92	mohor	`latching_data = "tdi shifted in";`
311			`end`
312	94	mohor	`else`
313			`latching_data = "nothing";`
314	82	mohor	`end`
315
316
317	90	mohor	`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
318	88	mohor
319	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
320	82	mohor	`begin`
321	95	mohor	`if (rst_i)`
322	87	mohor	`cmd_cnt <= #1 'h0;`
323	82	mohor	`else if (update_dr_i)`
324	87	mohor	`cmd_cnt <= #1 'h0;`
325	90	mohor	`else if (cmd_cnt_en)`
326	87	mohor	`cmd_cnt <= #1 cmd_cnt + 1'b1;`
327	82	mohor	`end`
328
329
330	90	mohor	`assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);`
331
332	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
333	87	mohor	`begin`
334	95	mohor	`if (rst_i)`
335	88	mohor	`addr_len_cnt <= #1 'h0;`
336			`else if (update_dr_i)`
337			`addr_len_cnt <= #1 'h0;`
338	90	mohor	`else if (addr_len_cnt_en)`
339	88	mohor	`addr_len_cnt <= #1 addr_len_cnt + 1'b1;`
340			`end`
341
342
343	95	mohor	`assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle \| crc_cnt_end & read_cycle);`
344	90	mohor
345	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
346	88	mohor	`begin`
347	95	mohor	`if (rst_i)`
348	87	mohor	`data_cnt <= #1 'h0;`
349			`else if (update_dr_i)`
350			`data_cnt <= #1 'h0;`
351	90	mohor	`else if (data_cnt_en)`
352	87	mohor	`data_cnt <= #1 data_cnt + 1'b1;`
353			`end`
354	82	mohor
355	87	mohor
356	88	mohor
357	93	mohor	`assign byte = data_cnt[2:0] == 3'd7;`
358			`assign half = data_cnt[3:0] == 4'd15;`
359			`assign long = data_cnt[4:0] == 5'd31;`
360	88	mohor
361
362			`always @ (posedge tck_i)`
363			`begin`
364	95	mohor	`byte_q <= #1 byte;`
365			`half_q <= #1 half;`
366			`long_q <= #1 long;`
367			`byte_q2 <= #1 byte_q;`
368			`half_q2 <= #1 half_q;`
369			`long_q2 <= #1 long_q;`
370	88	mohor	`end`
371
372
373	89	mohor	assign dr_read = (dr[2:0] == `WB_READ8) \| (dr[2:0] == `WB_READ16) \| (dr[2:0] == `WB_READ32);
374			assign dr_write = (dr[2:0] == `WB_WRITE8) \| (dr[2:0] == `WB_WRITE16) \| (dr[2:0] == `WB_WRITE32);
375			assign dr_go = dr[2:0] == `WB_GO;
376	88	mohor
377
378			`always @ (posedge tck_i)`
379			`begin`
380			`if (update_dr_i)`
381	91	mohor	`begin`
382			`dr_cmd_latched = 3'h0;`
383			`dr_read_latched <= #1 1'b0;`
384			`dr_write_latched <= #1 1'b0;`
385			`dr_go_latched <= #1 1'b0;`
386			`end`
387	88	mohor	`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
388	91	mohor	`begin`
389			`dr_cmd_latched = dr[2:0];`
390			`dr_read_latched <= #1 dr_read;`
391			`dr_write_latched <= #1 dr_write;`
392			`dr_go_latched <= #1 dr_go;`
393			`end`
394	88	mohor	`end`
395
396
397			`always @ (posedge tck_i)`
398			`begin`
399	90	mohor	`if (cmd_cnt == 2'h2)`
400	88	mohor	`begin`
401	95	mohor	`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
402	88	mohor	`addr_len_cnt_limit = 6'd0;`
403	90	mohor	`else // (current command is WB_WRITEx or WB_READx)`
404	88	mohor	`addr_len_cnt_limit = 6'd48;`
405			`end`
406			`end`
407
408
409	94	mohor	`wire go_prelim;`
410
411			`assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);`
412
413	88	mohor
414	94	mohor	`always @ (posedge tck_i)`
415			`begin`
416			`if (update_dr_i)`
417			`data_cnt_limit = {len, 3'b000};`
418			`end`
419	88	mohor
420	90	mohor
421	94	mohor	`assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) \| (data_cnt_end & write_cycle));`
422
423	82	mohor	`// crc counter`
424	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
425	82	mohor	`begin`
426	95	mohor	`if (rst_i)`
427	82	mohor	`crc_cnt <= #1 'h0;`
428	90	mohor	`else if(crc_cnt_en)`
429	82	mohor	`crc_cnt <= #1 crc_cnt + 1'b1;`
430			`else if (update_dr_i)`
431			`crc_cnt <= #1 'h0;`
432			`end`
433
434	87	mohor	`assign cmd_cnt_end = cmd_cnt == 2'h3;`
435	88	mohor	`assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;`
436	87	mohor	`assign crc_cnt_end = crc_cnt == 6'd32;`
437	93	mohor	`assign crc_cnt_31 = crc_cnt == 6'd31;`
438	89	mohor	`assign data_cnt_end = (data_cnt == data_cnt_limit);`
439	82	mohor
440			`always @ (posedge tck_i)`
441			`begin`
442	90	mohor	`crc_cnt_end_q <= #1 crc_cnt_end;`
443			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
444			`data_cnt_end_q <= #1 data_cnt_end;`
445	82	mohor	`end`
446
447	90	mohor
448
449	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
450	82	mohor	`begin`
451	95	mohor	`if (rst_i)`
452	90	mohor	`status_cnt1 <= #1 1'b0;`
453	82	mohor	`else if (update_dr_i)`
454	90	mohor	`status_cnt1 <= #1 1'b0;`
455	94	mohor	`else if (data_cnt_end & read_cycle \|`
456	95	mohor	`crc_cnt_end & (~read_cycle)`
457	90	mohor	`)`
458			`status_cnt1 <= #1 1'b1;`
459	82	mohor	`end`
460
461	90	mohor
462	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
463	90	mohor	`begin`
464	95	mohor	`if (rst_i)`
465	90	mohor	`begin`
466			`status_cnt2 <= #1 1'b0;`
467			`status_cnt3 <= #1 1'b0;`
468			`status_cnt4 <= #1 1'b0;`
469			`end`
470			`else if (update_dr_i)`
471			`begin`
472			`status_cnt2 <= #1 1'b0;`
473			`status_cnt3 <= #1 1'b0;`
474			`status_cnt4 <= #1 1'b0;`
475			`end`
476			`else`
477			`begin`
478			`status_cnt2 <= #1 status_cnt1;`
479			`status_cnt3 <= #1 status_cnt2;`
480			`status_cnt4 <= #1 status_cnt3;`
481			`end`
482			`end`
483
484
485			`assign status_cnt_end = status_cnt4;`
486	82	mohor
487	92	mohor	`reg [199:0] status_text;`
488	95	mohor	`always @ (posedge tck_i or posedge rst_i)`
489	82	mohor	`begin`
490	95	mohor	`if (rst_i)`
491	92	mohor	`begin`
492	82	mohor	`status <= #1 'h0;`
493	92	mohor	`status_text <= #1 "reset";`
494			`end`
495			`else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))`
496			`begin`
497	88	mohor	`status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,`
498	92	mohor	`status_text <= #1 "!!!READ";`
499			`end`
500			`else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)`

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 95