Subversion Repositories dblclockfft

////////////////////////////////////////////////////////////////////////////

//

// Filename:    qtrstage_tb.cpp

//

// Project:     A Doubletime Pipelined FFT

//

// Purpose:     A test-bench for the qtrstage.v subfile of the double

//              clocked FFT.  This file may be run autonomously.  If so,

//              the last line output will either read "SUCCESS" on success,

//              or some other failure message otherwise.

//

//              This file depends upon verilator to both compile, run, and

//              therefore test qtrstage.v

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Tecnology, LLC

//

///////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory, run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

///////////////////////////////////////////////////////////////////////////

#include <stdio.h>

#include <stdint.h>

#include "Vqtrstage.h"

#include "verilated.h"

#define IWIDTH  16

#define OWIDTH  (IWIDTH+1)

#define LGWIDTH 8

void    tick(Vqtrstage *qstage) {

        qstage->i_clk = 0;

        qstage->eval();

        qstage->i_clk = 1;

        qstage->eval();

}

void    reset(Vqtrstage *qstage) {

        qstage->i_ce  = 0;

        qstage->i_rst = 1;

        tick(qstage);

        qstage->i_ce  = 0;

        qstage->i_rst = 0;

        tick(qstage);

}

int     main(int argc, char **argv, char **envp) {

        Verilated::commandArgs(argc, argv);

        Vqtrstage       *qstage = new Vqtrstage;

        int16_t         ir0, ii0, lstr, lsti;

        int32_t         sumr, sumi, difr, difi;

        int32_t         smr, smi, dfr, dfi;

        int             rnd = 0;

        reset(qstage);

        for(int k=0; k<1060; k++) {

                int32_t or0, oi0, or1, oi1;

                qstage->i_ce = 1;

                qstage->i_sync = ((k&0x0ff)==0);

                // Let's pick some random values, ...

                ir0 = rand(); if (ir0&4) ir0 = -ir0;

                ii0 = rand(); if (ii0&2) ii0 = -ii0;

                qstage->i_data  = ((ir0&0x0ffff) << 16) | (ii0 & 0x0ffff);

                tick(qstage);

                printf("k=%4d: ISYNC=%d, IN = %08x, OUT =%09lx, SYNC=%d\n",

                        k, qstage->i_sync, qstage->i_data,

                        qstage->o_data, qstage->o_sync);

                or0 = (qstage->o_data  >> 17) & 0x01ffff;

                oi0 =  qstage->o_data         & 0x01ffff;

                if (or0 & 0x010000)     or0 |= (-1<<16);

                if (oi0 & 0x010000)     oi0 |= (-1<<16);

                if (k>3) {

                        /*

                        printf("\tOR0 = %6x, OI0 = %6x, SUM = %6x + %6x, DIF = %6x + %6x\n",

                                or0, oi0, sumr, sumi, difr, difi);

                        */

                        if (0==(k&1)) {

                                if (or0 != sumr)        {fprintf(stderr, "FAIL 1\n"); exit(-1);}

                                if (oi0 != sumi)        {fprintf(stderr, "FAIL 2\n"); exit(-1);}

                        } else if (1==(k&1)) {

                                if (or0 != difr)        {fprintf(stderr, "FAIL 3\n"); exit(-1);}

                                if (oi0 != difi)        {fprintf(stderr, "FAIL 4\n"); exit(-1);}

                        }

                }

                if (((4==(k&0x07f))?1:0) != qstage->o_sync) { fprintf(stderr, "BAD O-SYNC\n"); exit(-1); }

                if (1 == (k&1)) {

                        sumr = smr; sumi = smi; difr=dfr, difi= dfi;

                        smr = lstr + ir0 + rnd;

                        smi = lsti + ii0 + rnd;

                        dfr = lstr - ir0 + rnd;

                        dfi = lsti - ii0 + rnd;

                }

                lstr = ir0;

                lsti = ii0;

        }

        delete  qstage;

        printf("SUCCESS!\n");

        exit(0);

}