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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ../rtl/abs_longbimpy.v
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//
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// Project: A General Purpose Pipelined FFT Implementation
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//
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// Purpose: A portable shift and add multiply, built with the knowledge
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// of the existence of a six bit LUT and carry chain. That knowledge
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// allows us to multiply two bits from one value at a time against all
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// of the bits of the other value. This sub multiply is called the
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// bimpy.
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//
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// For minimal processing delay, make the first parameter the one with
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// the least bits, so that AWIDTH <= BWIDTH.
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module longbimpy(i_clk, i_ce, i_a_unsorted, i_b_unsorted, o_r);
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parameter IAW=8, // The width of i_a, min width is 5
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IBW=12, // The width of i_b, can be anything
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// The following three parameters should not be changed
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// by any implementation, but are based upon hardware
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// and the above values:
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OW=IAW+IBW; // The output width
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localparam AW = (IAW<IBW) ? IAW : IBW,
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BW = (IAW<IBW) ? IBW : IAW,
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LUTB=2, // How many bits we can multiply by at once
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TLEN=(AW+(LUTB-1))/LUTB; // Nmbr of rows in our tableau
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input wire i_clk, i_ce;
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input wire [(IAW-1):0] i_a_unsorted;
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input wire [(IBW-1):0] i_b_unsorted;
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output reg [(AW+BW-1):0] o_r;
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//
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// Swap parameter order, so that AW <= BW -- for performance
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// reasons
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wire [AW-1:0] i_a;
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wire [BW-1:0] i_b;
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generate if (IAW <= IBW)
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begin : NO_PARAM_CHANGE
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assign i_a = i_a_unsorted;
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assign i_b = i_b_unsorted;
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end else begin : SWAP_PARAMETERS
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assign i_a = i_b_unsorted;
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assign i_b = i_a_unsorted;
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end endgenerate
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`ifndef FORMAL
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// This file should only be used in a formal context.
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// The following line should therefore yield a syntax error
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assert(0);
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`endif
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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reg [AW-1:0] f_past_a [0:TLEN+1];
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reg [BW-1:0] f_past_b [0:TLEN+1];
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initial f_past_a[0] = 0;
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initial f_past_b[0] = 0;
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always @(posedge i_clk)
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if (i_ce)
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begin
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f_past_a[0] <= i_a;
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f_past_b[0] <= i_b;
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end
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genvar k;
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generate for(k=0; k<TLEN+1; k=k+1)
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begin
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initial f_past_a[k+1] = 0;
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initial f_past_b[k+1] = 0;
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always @(posedge i_clk)
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if (i_ce)
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begin
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f_past_a[k+1] <= f_past_a[k];
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f_past_b[k+1] <= f_past_b[k];
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end
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end endgenerate
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// abs_mpy #(.AW(AW), .BW(BW)) thempy(f_past_a[TLEN+1], f_past_b[TLEN+1], o_r);
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(* anyseq *) reg [AW+BW-1:0] result;
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wire [AW+BW-1:0] f_neg_a, f_neg_b;
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assign f_neg_a = - {{(BW){f_past_a[TLEN+1][AW-1]}}, f_past_a[TLEN+1]};
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assign f_neg_b = - {{(AW){f_past_b[TLEN+1][BW-1]}}, f_past_b[TLEN+1]};
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always @(*)
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if (f_past_a[TLEN+1] == 0)
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assume(result == 0);
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else if (f_past_b[TLEN+1] == 0)
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assume(result == 0);
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else if (f_past_a[TLEN+1] == 1)
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begin
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assume(result[BW-1:0] == f_past_b[TLEN+1]);
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assume(result[AW+BW-1:BW] == {(AW){f_past_b[TLEN+1][BW-1]}});
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end else if (f_past_b[TLEN+1] == 1)
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begin
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assume(result[AW-1:0] == f_past_a[TLEN+1]);
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assume(result[AW+BW-1:AW] == {(BW){f_past_a[TLEN+1][AW-1]}});
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end else if (&f_past_a[TLEN+1])
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assume(result == f_neg_b);
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else if (&f_past_b[TLEN+1])
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assume(result == f_neg_a);
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else
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assume(result[AW+BW-1] == (f_past_a[TLEN+1][AW-1]
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^f_past_b[TLEN+1][BW-1]));
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always @(*)
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o_r = result;
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endmodule
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