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[/] [dblclockfft/] [trunk/] [bench/] [formal/] [butterfly.sby] - Blame information for rev 36

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Line No. Rev Author Line
1 36 dgisselq 
[tasks]
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ck1
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ck2_r0
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ck2_r1
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ck3_r0
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ck3_r1
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[options]
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mode prove
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depth   30
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[engines]
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smtbmc
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[script]
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read_verilog -formal -DHWBFLY abs_mpy.v
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read_verilog -formal -DHWBFLY convround.v
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read_verilog -formal -DHWBFLY longbimpy.v
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read_verilog -formal -DHWBFLY bimpy.v
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read_verilog -formal -DHWBFLY butterfly.v
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# While I'd love to change the width of the inputs and the coefficients,
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# doing so would adjust the width of the firmware multiplies, and so defeat
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# our purpose here.
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# ck1:    chparam -set CKPCE 1 butterfly
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ck1:    chparam -set CKPCE 1 -set CWIDTH 19 -set IWIDTH 15 butterfly
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#
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ck2_r0: chparam -set CKPCE 2 -set CWIDTH 20 -set IWIDTH 12 -set F_CHECK 1 butterfly
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ck2_r1: chparam -set CKPCE 2 -set CWIDTH 16 -set IWIDTH 6 -set F_CHECK 0 butterfly
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#
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ck3_r0: chparam -set CKPCE 3 -set CWIDTH 16 -set IWIDTH 12 -set F_CHECK 0 butterfly
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ck3_r1: chparam -set CKPCE 3 -set CWIDTH 18 -set IWIDTH 14 -set F_CHECK 1 butterfly
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ck3_r2: chparam -set CKPCE 3 -set CWIDTH 20 -set IWIDTH 16 -set F_CHECK 2 butterfly
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prep -top butterfly
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[files]
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abs_mpy.v
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../../rtl/convround.v
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../../rtl/bimpy.v
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../../rtl/longbimpy.v
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../../rtl/butterfly.v

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